Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18211

1

T7

4

T8

87

T10

28

auto[1]

12354

1

T5

2

T8

85

T25

75

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4114	1			T25	45		T30	111		T48	47
values[1]	3622	1			T20	10		T146	8		T25	48
values[2]	3644	1			T5	2		T93	14		T30	21
values[3]	3834	1			T8	60		T11	14		T25	20
values[4]	4111	1			T7	4		T34	20		T35	20
values[5]	3723	1			T8	89		T34	21		T35	40
values[6]	3275	1			T8	23		T10	28		T46	8
values[7]	4242	1			T145	2		T28	18		T33	16

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3455	1			T7	4		T11	14		T28	18
values[1]	3690	1			T35	68		T32	22		T36	14
values[2]	4204	1			T33	16		T25	40		T158	6
values[3]	3725	1			T8	39		T10	28		T20	10
values[4]	3980	1			T146	8		T25	48		T31	12
values[5]	3768	1			T5	2		T8	20		T145	2
values[6]	4407	1			T8	39		T25	23		T102	12
values[7]	3336	1			T8	74		T25	20		T30	41

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	437	1			T25	10		T166	23		T70	11
auto[0]	values[0]	values[1]	254	1			T35	57		T58	12		T198	9
auto[0]	values[0]	values[2]	365	1			T25	12		T38	48		T210	12
auto[0]	values[0]	values[3]	192	1			T39	11		T239	8		T240	15
auto[0]	values[0]	values[4]	204	1			T34	17		T188	13		T200	13
auto[0]	values[0]	values[5]	234	1			T167	13		T241	20		T84	66
auto[0]	values[0]	values[6]	399	1			T30	81		T48	36		T34	14
auto[0]	values[0]	values[7]	231	1			T30	8		T37	59		T216	9
auto[0]	values[1]	values[0]	141	1			T242	8		T166	12		T54	11
auto[0]	values[1]	values[1]	182	1			T32	16		T195	13		T216	12
auto[0]	values[1]	values[2]	408	1			T34	7		T32	9		T167	12
auto[0]	values[1]	values[3]	276	1			T20	10		T243	10		T54	11
auto[0]	values[1]	values[4]	335	1			T146	8		T25	25		T31	12
auto[0]	values[1]	values[5]	435	1			T38	24		T198	13		T189	6
auto[0]	values[1]	values[6]	248	1			T244	10		T245	10		T193	18
auto[0]	values[1]	values[7]	241	1			T94	4		T39	83		T166	14
auto[0]	values[2]	values[0]	153	1			T34	10		T37	28		T41	11
auto[0]	values[2]	values[1]	348	1			T210	13		T212	77		T246	2
auto[0]	values[2]	values[2]	348	1			T35	11		T70	22		T220	13
auto[0]	values[2]	values[3]	208	1			T93	14		T39	13		T167	32
auto[0]	values[2]	values[4]	217	1			T167	16		T208	8		T69	18
auto[0]	values[2]	values[5]	280	1			T34	12		T38	10		T247	2
auto[0]	values[2]	values[6]	439	1			T35	10		T69	7		T50	13
auto[0]	values[2]	values[7]	308	1			T30	11		T32	11		T210	11
auto[0]	values[3]	values[0]	256	1			T11	14		T34	8		T168	43
auto[0]	values[3]	values[1]	354	1			T37	15		T210	11		T216	7
auto[0]	values[3]	values[2]	355	1			T25	11		T209	20		T188	12
auto[0]	values[3]	values[3]	188	1			T8	10		T34	13		T32	36
auto[0]	values[3]	values[4]	311	1			T38	8		T167	15		T41	9
auto[0]	values[3]	values[5]	443	1			T34	19		T39	9		T248	4
auto[0]	values[3]	values[6]	364	1			T102	12		T249	14		T250	26
auto[0]	values[3]	values[7]	102	1			T8	12		T167	14		T188	12
auto[0]	values[4]	values[0]	356	1			T7	4		T226	18		T32	11
auto[0]	values[4]	values[1]	206	1			T166	9		T70	10		T189	14
auto[0]	values[4]	values[2]	372	1			T38	11		T166	7		T188	11
auto[0]	values[4]	values[3]	516	1			T35	14		T37	11		T251	20
auto[0]	values[4]	values[4]	217	1			T167	11		T41	15		T188	13
auto[0]	values[4]	values[5]	270	1			T39	117		T195	12		T197	13
auto[0]	values[4]	values[6]	274	1			T34	12		T252	4		T210	18
auto[0]	values[4]	values[7]	187	1			T41	11		T216	17		T235	10
auto[0]	values[5]	values[0]	250	1			T35	6		T185	13		T128	12
auto[0]	values[5]	values[1]	301	1			T37	17		T39	14		T190	20
auto[0]	values[5]	values[2]	135	1			T39	16		T167	8		T95	8
auto[0]	values[5]	values[3]	261	1			T34	9		T32	15		T166	12
auto[0]	values[5]	values[4]	425	1			T32	18		T253	16		T70	9
auto[0]	values[5]	values[5]	265	1			T8	12		T37	10		T188	17
auto[0]	values[5]	values[6]	404	1			T8	11		T35	12		T32	13
auto[0]	values[5]	values[7]	336	1			T8	27		T233	24		T39	52
auto[0]	values[6]	values[0]	180	1			T38	9		T69	14		T200	8
auto[0]	values[6]	values[1]	282	1			T37	11		T39	59		T254	8
auto[0]	values[6]	values[2]	172	1			T34	7		T32	9		T38	7
auto[0]	values[6]	values[3]	270	1			T10	28		T46	8		T41	7
auto[0]	values[6]	values[4]	340	1			T34	11		T39	10		T41	19
auto[0]	values[6]	values[5]	197	1			T255	2		T166	9		T195	15
auto[0]	values[6]	values[6]	269	1			T165	10		T32	32		T214	12
auto[0]	values[6]	values[7]	157	1			T8	15		T25	10		T215	8
auto[0]	values[7]	values[0]	231	1			T28	18		T35	9		T167	9
auto[0]	values[7]	values[1]	395	1			T188	15		T256	14		T54	8
auto[0]	values[7]	values[2]	259	1			T33	16		T158	6		T257	2
auto[0]	values[7]	values[3]	288	1			T37	10		T258	2		T167	5
auto[0]	values[7]	values[4]	275	1			T34	8		T39	40		T69	9
auto[0]	values[7]	values[5]	227	1			T145	2		T41	11		T69	10
auto[0]	values[7]	values[6]	370	1			T25	13		T34	13		T37	70
auto[0]	values[7]	values[7]	268	1			T160	6		T37	12		T54	31
auto[1]	values[0]	values[0]	191	1			T25	15		T166	20		T70	9
auto[1]	values[0]	values[1]	298	1			T35	11		T198	11		T224	12
auto[1]	values[0]	values[2]	373	1			T25	8		T38	9		T210	8
auto[1]	values[0]	values[3]	195	1			T39	9		T240	9		T22	9
auto[1]	values[0]	values[4]	171	1			T34	3		T188	9		T200	9
auto[1]	values[0]	values[5]	142	1			T167	10		T84	4		T22	34
auto[1]	values[0]	values[6]	185	1			T30	10		T48	11		T34	6
auto[1]	values[0]	values[7]	243	1			T30	12		T37	10		T216	17
auto[1]	values[1]	values[0]	144	1			T166	11		T54	20		T84	8
auto[1]	values[1]	values[1]	200	1			T32	6		T36	14		T195	7
auto[1]	values[1]	values[2]	207	1			T34	13		T32	11		T167	8
auto[1]	values[1]	values[3]	268	1			T29	22		T54	9		T224	13
auto[1]	values[1]	values[4]	177	1			T25	23		T37	18		T167	8
auto[1]	values[1]	values[5]	148	1			T38	5		T198	7		T189	14
auto[1]	values[1]	values[6]	136	1			T245	10		T259	16		T193	10
auto[1]	values[1]	values[7]	76	1			T39	5		T166	6		T69	9
auto[1]	values[2]	values[0]	119	1			T34	10		T37	9		T41	9
auto[1]	values[2]	values[1]	149	1			T210	7		T212	17		T260	8
auto[1]	values[2]	values[2]	162	1			T35	9		T225	6		T70	4
auto[1]	values[2]	values[3]	105	1			T39	7		T167	4		T261	4
auto[1]	values[2]	values[4]	191	1			T167	9		T69	6		T237	12
auto[1]	values[2]	values[5]	148	1			T5	2		T34	8		T38	10
auto[1]	values[2]	values[6]	269	1			T35	11		T69	13		T50	13
auto[1]	values[2]	values[7]	200	1			T30	10		T32	10		T210	12
auto[1]	values[3]	values[0]	209	1			T34	12		T167	13		T210	11
auto[1]	values[3]	values[1]	160	1			T37	6		T210	15		T216	27
auto[1]	values[3]	values[2]	122	1			T25	9		T188	10		T197	10
auto[1]	values[3]	values[3]	177	1			T8	29		T34	7		T32	11
auto[1]	values[3]	values[4]	196	1			T38	14		T167	6		T41	12
auto[1]	values[3]	values[5]	401	1			T34	4		T39	27		T70	16
auto[1]	values[3]	values[6]	110	1			T206	9		T84	5		T22	13
auto[1]	values[3]	values[7]	86	1			T8	9		T229	16		T167	10
auto[1]	values[4]	values[0]	217	1			T32	12		T220	9		T189	12
auto[1]	values[4]	values[1]	122	1			T166	12		T70	12		T189	9
auto[1]	values[4]	values[2]	363	1			T38	9		T166	16		T188	9
auto[1]	values[4]	values[3]	129	1			T35	6		T37	9		T251	6
auto[1]	values[4]	values[4]	227	1			T167	14		T262	16		T41	8
auto[1]	values[4]	values[5]	88	1			T39	18		T195	9		T197	7
auto[1]	values[4]	values[6]	190	1			T34	8		T210	7		T70	10
auto[1]	values[4]	values[7]	377	1			T194	12		T41	11		T216	3
auto[1]	values[5]	values[0]	184	1			T35	14		T185	7		T128	12
auto[1]	values[5]	values[1]	111	1			T37	6		T39	6		T190	8
auto[1]	values[5]	values[2]	169	1			T39	4		T167	12		T54	9
auto[1]	values[5]	values[3]	152	1			T34	12		T32	7		T166	8
auto[1]	values[5]	values[4]	203	1			T32	9		T70	11		T200	11
auto[1]	values[5]	values[5]	166	1			T8	8		T37	60		T188	3
auto[1]	values[5]	values[6]	305	1			T8	28		T35	8		T32	13
auto[1]	values[5]	values[7]	56	1			T8	3		T39	9		T155	4
auto[1]	values[6]	values[0]	130	1			T38	11		T69	8		T200	12
auto[1]	values[6]	values[1]	192	1			T37	9		T39	10		T41	17
auto[1]	values[6]	values[2]	205	1			T34	19		T32	17		T38	24
auto[1]	values[6]	values[3]	155	1			T41	16		T70	5		T50	5
auto[1]	values[6]	values[4]	223	1			T34	9		T39	10		T41	5
auto[1]	values[6]	values[5]	120	1			T166	11		T195	5		T22	7
auto[1]	values[6]	values[6]	230	1			T32	11		T210	12		T190	6
auto[1]	values[6]	values[7]	153	1			T8	8		T25	10		T200	9
auto[1]	values[7]	values[0]	257	1			T35	11		T167	11		T69	9
auto[1]	values[7]	values[1]	136	1			T188	7		T256	6		T54	29
auto[1]	values[7]	values[2]	189	1			T216	13		T197	10		T206	9
auto[1]	values[7]	values[3]	345	1			T37	10		T167	15		T41	8
auto[1]	values[7]	values[4]	268	1			T34	12		T39	6		T69	14
auto[1]	values[7]	values[5]	204	1			T41	10		T263	2		T69	11
auto[1]	values[7]	values[6]	215	1			T25	10		T34	11		T37	19
auto[1]	values[7]	values[7]	315	1			T37	8		T54	14		T198	13