Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2779084	1			T1	1614		T3	1702		T4	1
all_pins[1]	2779084	1			T1	1614		T3	1702		T4	1
all_pins[2]	2779084	1			T1	1614		T3	1702		T4	1
all_pins[3]	2779084	1			T1	1614		T3	1702		T4	1
all_pins[4]	2779084	1			T1	1614		T3	1702		T4	1
all_pins[5]	2779084	1			T1	1614		T3	1702		T4	1
all_pins[6]	2779084	1			T1	1614		T3	1702		T4	1
all_pins[7]	2779084	1			T1	1614		T3	1702		T4	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	22195391	1			T1	12912		T3	13616		T4	8
values[0x1]	37281	1			T26	35		T30	21		T64	12
transitions[0x0=>0x1]	35877	1			T26	26		T30	17		T64	10
transitions[0x1=>0x0]	35887	1			T26	26		T30	17		T64	10

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2778277	1			T1	1614		T3	1702		T4	1
all_pins[0]	values[0x1]	807	1			T26	4		T30	4		T64	1
all_pins[0]	transitions[0x0=>0x1]	551	1			T26	2		T30	3		T64	1
all_pins[0]	transitions[0x1=>0x0]	285	1			T26	3		T30	3		T64	2
all_pins[1]	values[0x0]	2778543	1			T1	1614		T3	1702		T4	1
all_pins[1]	values[0x1]	541	1			T26	5		T30	4		T64	2
all_pins[1]	transitions[0x0=>0x1]	418	1			T26	4		T30	3		T64	2
all_pins[1]	transitions[0x1=>0x0]	157	1			T26	6		T30	4		T64	1
all_pins[2]	values[0x0]	2778804	1			T1	1614		T3	1702		T4	1
all_pins[2]	values[0x1]	280	1			T26	7		T30	5		T64	1
all_pins[2]	transitions[0x0=>0x1]	237	1			T26	6		T30	4		T64	1
all_pins[2]	transitions[0x1=>0x0]	153	1			T26	3		T30	1		T64	2
all_pins[3]	values[0x0]	2778888	1			T1	1614		T3	1702		T4	1
all_pins[3]	values[0x1]	196	1			T26	4		T30	2		T64	2
all_pins[3]	transitions[0x0=>0x1]	140	1			T26	2		T30	2		T69	2
all_pins[3]	transitions[0x1=>0x0]	165	1			T26	2		T64	1		T69	1
all_pins[4]	values[0x0]	2778863	1			T1	1614		T3	1702		T4	1
all_pins[4]	values[0x1]	221	1			T26	4		T64	3		T69	1
all_pins[4]	transitions[0x0=>0x1]	180	1			T26	3		T64	3		T70	2
all_pins[4]	transitions[0x1=>0x0]	878	1			T26	3		T69	2		T70	4
all_pins[5]	values[0x0]	2778165	1			T1	1614		T3	1702		T4	1
all_pins[5]	values[0x1]	919	1			T26	4		T69	3		T70	4
all_pins[5]	transitions[0x0=>0x1]	134	1			T26	4		T69	2		T70	2
all_pins[5]	transitions[0x1=>0x0]	33350	1			T26	3		T30	4		T64	3
all_pins[6]	values[0x0]	2744949	1			T1	1614		T3	1702		T4	1
all_pins[6]	values[0x1]	34135	1			T26	3		T30	4		T64	3
all_pins[6]	transitions[0x0=>0x1]	34088	1			T26	3		T30	4		T64	3
all_pins[6]	transitions[0x1=>0x0]	135	1			T26	4		T30	2		T69	1
all_pins[7]	values[0x0]	2778902	1			T1	1614		T3	1702		T4	1
all_pins[7]	values[0x1]	182	1			T26	4		T30	2		T69	1
all_pins[7]	transitions[0x0=>0x1]	129	1			T26	2		T30	1		T69	1
all_pins[7]	transitions[0x1=>0x0]	764	1			T26	2		T30	3		T64	1