Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	390	1			T28	8		T93	2		T30	1
auto[ReadAddrCrossIntoMailbox]	276	1			T25	1		T30	2		T34	3
auto[ReadAddrCrossOutOfMailbox]	280	1			T8	1		T25	1		T93	2
auto[ReadAddrCrossAllMailbox]	194	1			T25	1		T34	1		T35	1
auto[ReadAddrOutsideMailbox]	3555	1			T8	25		T46	4		T33	8

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2406

1

T8

17

T46

2

T28

4

auto[1]

2289

1

T8

9

T46

2

T28

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	790	1			T8	4		T33	2		T25	5
read_ops[0x0b]	794	1			T8	2		T46	4		T33	2
read_ops[0x3b]	765	1			T8	6		T28	4		T33	2
read_ops[0x6b]	766	1			T8	2		T25	1		T93	4
read_ops[0xbb]	796	1			T8	8		T28	4		T33	2
read_ops[0xeb]	784	1			T8	4		T25	3		T93	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	26	1			T34	1		T32	1		T37	2
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	22	1			T39	1		T166	1		T210	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T32	1		T188	2		T200	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T32	1		T37	1		T210	3
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T8	1		T39	1		T167	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T39	1		T210	1		T188	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T34	1		T38	1		T41	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T167	1		T41	1		T69	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	336	1			T8	2		T33	1		T25	3
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	274	1			T8	1		T33	1		T25	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	41	1			T34	1		T37	1		T242	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	41	1			T37	1		T242	1		T167	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T37	2		T166	1		T214	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T35	1		T39	2		T214	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T34	1		T39	2		T214	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	30	1			T37	1		T38	1		T166	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T39	1		T210	1		T235	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T32	1		T235	1		T221	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	276	1			T8	1		T46	2		T33	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	293	1			T8	1		T46	2		T33	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	26	1			T28	2		T166	1		T195	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	29	1			T28	2		T37	2		T39	3
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	15	1			T195	1		T70	1		T206	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T34	2		T37	2		T210	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T198	1		T224	2		T206	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T34	1		T35	1		T37	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	13	1			T224	1		T207	1		T232	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	11	1			T37	1		T70	1		T54	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	305	1			T8	6		T33	1		T25	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	301	1			T33	1		T25	3		T93	3
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	26	1			T93	1		T34	1		T226	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T93	1		T34	1		T226	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T34	1		T37	1		T39	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T38	1		T39	2		T166	2
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T93	1		T37	1		T39	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	19	1			T93	1		T34	1		T37	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T37	1		T167	1		T95	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T95	1		T198	1		T237	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	297	1			T8	1		T29	1		T30	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	284	1			T8	1		T25	1		T29	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T28	2		T34	1		T226	3
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	42	1			T28	2		T226	3		T39	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T25	1		T32	1		T37	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T30	1		T32	1		T39	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	19	1			T167	1		T41	2		T264	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T25	1		T34	1		T37	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T39	1		T41	1		T69	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T35	1		T155	1		T265	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	334	1			T8	3		T33	1		T25	3
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	265	1			T8	5		T33	1		T31	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T30	1		T226	2		T210	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T226	2		T37	4		T166	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T30	1		T32	2		T166	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	19	1			T41	3		T188	1		T235	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	19	1			T37	1		T166	1		T210	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T41	1		T220	1		T213	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	25	1			T25	1		T37	3		T210	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T167	1		T215	1		T200	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	300	1			T8	3		T25	2		T93	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	290	1			T8	1		T93	1		T30	3