Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3181	1			T5	2		T8	39		T25	65
values[1]	3449	1			T7	4		T46	8		T33	16
values[2]	3830	1			T20	10		T145	2		T146	8
values[3]	3723	1			T8	64		T25	48		T30	91
values[4]	3412	1			T8	39		T11	14		T28	18
values[5]	4479	1			T255	2		T34	44		T35	68
values[6]	3769	1			T10	28		T34	41		T35	20
values[7]	4722	1			T8	30		T25	20		T29	22

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3388	1			T8	21		T146	8		T158	6
values[1]	4351	1			T8	39		T10	28		T33	16
values[2]	3826	1			T8	73		T25	40		T255	2
values[3]	3654	1			T5	2		T11	14		T30	21
values[4]	3287	1			T8	39		T20	10		T25	20
values[5]	3897	1			T145	2		T25	73		T102	12
values[6]	4145	1			T7	4		T28	18		T30	91
values[7]	4017	1			T46	8		T34	21		T35	20

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30073

1

T5

2

T7

4

T8

167

auto[1]

492

1

T8

5

T25

6

T29

2

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	428	1			T38	31		T188	20		T69	23
auto[0]	values[0]	values[1]	372	1			T8	39		T70	20		T197	18
auto[0]	values[0]	values[2]	300	1			T25	40		T34	20		T37	20
auto[0]	values[0]	values[3]	267	1			T5	2		T39	20		T167	40
auto[0]	values[0]	values[4]	246	1			T160	6		T39	36		T168	43
auto[0]	values[0]	values[5]	631	1			T25	24		T34	18		T70	40
auto[0]	values[0]	values[6]	381	1			T202	22		T41	20		T266	6
auto[0]	values[0]	values[7]	508	1			T32	26		T267	53		T210	25
auto[0]	values[1]	values[0]	410	1			T239	8		T95	8		T22	21
auto[0]	values[1]	values[1]	378	1			T33	16		T25	23		T32	19
auto[0]	values[1]	values[2]	364	1			T37	93		T167	25		T210	20
auto[0]	values[1]	values[3]	336	1			T214	12		T70	17		T243	10
auto[0]	values[1]	values[4]	519	1			T37	68		T41	41		T188	17
auto[0]	values[1]	values[5]	398	1			T34	47		T38	20		T70	20
auto[0]	values[1]	values[6]	571	1			T7	4		T39	20		T210	26
auto[0]	values[1]	values[7]	408	1			T46	8		T190	47		T249	14
auto[0]	values[2]	values[0]	435	1			T146	8		T158	6		T32	21
auto[0]	values[2]	values[1]	567	1			T34	20		T39	20		T201	16
auto[0]	values[2]	values[2]	520	1			T34	20		T37	20		T216	20
auto[0]	values[2]	values[3]	517	1			T30	21		T38	55		T167	20
auto[0]	values[2]	values[4]	605	1			T20	10		T31	12		T34	19
auto[0]	values[2]	values[5]	357	1			T145	2		T94	4		T35	20
auto[0]	values[2]	values[6]	310	1			T190	20		T220	19		T189	21
auto[0]	values[2]	values[7]	439	1			T226	18		T167	19		T257	2
auto[0]	values[3]	values[0]	306	1			T8	21		T268	2		T258	2
auto[0]	values[3]	values[1]	736	1			T34	18		T32	21		T39	67
auto[0]	values[3]	values[2]	625	1			T8	42		T48	47		T37	20
auto[0]	values[3]	values[3]	268	1			T210	22		T195	20		T269	18
auto[0]	values[3]	values[4]	468	1			T25	20		T210	23		T270	38
auto[0]	values[3]	values[5]	460	1			T25	27		T39	88		T166	19
auto[0]	values[3]	values[6]	334	1			T30	90		T166	20		T41	23
auto[0]	values[3]	values[7]	471	1			T251	26		T188	26		T271	12
auto[0]	values[4]	values[0]	332	1			T39	20		T194	12		T166	20
auto[0]	values[4]	values[1]	561	1			T35	20		T200	32		T272	8
auto[0]	values[4]	values[2]	317	1			T32	23		T166	23		T41	24
auto[0]	values[4]	values[3]	461	1			T11	14		T165	10		T198	23
auto[0]	values[4]	values[4]	350	1			T8	38		T37	21		T216	20
auto[0]	values[4]	values[5]	368	1			T102	12		T93	14		T35	20
auto[0]	values[4]	values[6]	400	1			T28	18		T254	8		T262	16
auto[0]	values[4]	values[7]	584	1			T37	41		T273	8		T240	20
auto[0]	values[5]	values[0]	543	1			T34	23		T70	68		T190	20
auto[0]	values[5]	values[1]	450	1			T38	19		T234	20		T220	22
auto[0]	values[5]	values[2]	509	1			T255	2		T36	12		T195	20
auto[0]	values[5]	values[3]	585	1			T39	18		T54	37		T234	20
auto[0]	values[5]	values[4]	425	1			T233	24		T195	20		T274	8
auto[0]	values[5]	values[5]	613	1			T34	20		T32	46		T39	91
auto[0]	values[5]	values[6]	821	1			T35	65		T39	20		T69	22
auto[0]	values[5]	values[7]	457	1			T32	21		T167	19		T195	18
auto[0]	values[6]	values[0]	382	1			T34	20		T237	19		T84	44
auto[0]	values[6]	values[1]	358	1			T10	28		T38	19		T69	20
auto[0]	values[6]	values[2]	312	1			T188	20		T183	20		T275	28
auto[0]	values[6]	values[3]	548	1			T35	20		T32	22		T166	21
auto[0]	values[6]	values[4]	274	1			T242	8		T208	8		T189	20
auto[0]	values[6]	values[5]	615	1			T32	27		T166	21		T188	22
auto[0]	values[6]	values[6]	746	1			T205	8		T70	65		T200	22
auto[0]	values[6]	values[7]	472	1			T34	21		T167	23		T197	20
auto[0]	values[7]	values[0]	516	1			T37	37		T39	20		T167	20
auto[0]	values[7]	values[1]	855	1			T252	4		T195	49		T190	43
auto[0]	values[7]	values[2]	824	1			T8	27		T29	20		T30	20
auto[0]	values[7]	values[3]	611	1			T35	20		T38	20		T209	20
auto[0]	values[7]	values[4]	341	1			T34	18		T237	26		T276	18
auto[0]	values[7]	values[5]	388	1			T25	16		T34	20		T38	28
auto[0]	values[7]	values[6]	513	1			T229	14		T70	69		T200	20
auto[0]	values[7]	values[7]	607	1			T35	20		T32	47		T37	70
auto[1]	values[0]	values[0]	5	1			T50	1		T237	2		T277	2
auto[1]	values[0]	values[1]	6	1			T197	2		T261	1		T278	2
auto[1]	values[0]	values[2]	7	1			T195	1		T198	1		T22	1
auto[1]	values[0]	values[3]	8	1			T167	1		T210	2		T190	1
auto[1]	values[0]	values[4]	2	1			T279	2		-	-		-	-
auto[1]	values[0]	values[5]	7	1			T25	1		T34	2		T128	2
auto[1]	values[0]	values[6]	5	1			T54	2		T224	2		T280	1
auto[1]	values[0]	values[7]	8	1			T153	1		T129	3		T281	2
auto[1]	values[1]	values[0]	5	1			T22	1		T193	1		T282	1
auto[1]	values[1]	values[1]	8	1			T32	1		T216	4		T240	1
auto[1]	values[1]	values[2]	4	1			T37	2		T283	2		-	-
auto[1]	values[1]	values[3]	5	1			T70	3		T284	1		T285	1
auto[1]	values[1]	values[4]	12	1			T37	1		T188	3		T284	4
auto[1]	values[1]	values[5]	9	1			T34	2		T185	1		T286	2
auto[1]	values[1]	values[6]	13	1			T206	1		T240	2		T287	1
auto[1]	values[1]	values[7]	9	1			T190	3		T206	2		T221	2
auto[1]	values[2]	values[0]	5	1			T188	1		T207	1		T128	1
auto[1]	values[2]	values[1]	13	1			T41	3		T192	5		T288	2
auto[1]	values[2]	values[2]	6	1			T224	1		T24	4		T289	1
auto[1]	values[2]	values[3]	16	1			T38	2		T167	5		T210	1
auto[1]	values[2]	values[4]	14	1			T34	1		T188	1		T50	2
auto[1]	values[2]	values[5]	8	1			T216	2		T219	1		T204	1
auto[1]	values[2]	values[6]	7	1			T220	1		T189	3		T260	1
auto[1]	values[2]	values[7]	11	1			T167	2		T41	1		T190	1
auto[1]	values[3]	values[0]	1	1			T265	1		-	-		-	-
auto[1]	values[3]	values[1]	14	1			T34	2		T39	2		T221	1
auto[1]	values[3]	values[2]	9	1			T8	1		T38	1		T216	1
auto[1]	values[3]	values[3]	4	1			T269	2		T189	1		T128	1
auto[1]	values[3]	values[4]	6	1			T50	2		T219	3		T279	1
auto[1]	values[3]	values[5]	6	1			T25	1		T166	1		T290	3
auto[1]	values[3]	values[6]	9	1			T30	1		T22	4		T286	1
auto[1]	values[3]	values[7]	6	1			T271	2		T198	2		T129	1
auto[1]	values[4]	values[0]	1	1			T219	1		-	-		-	-
auto[1]	values[4]	values[1]	6	1			T200	1		T291	1		T154	1
auto[1]	values[4]	values[2]	2	1			T197	2		-	-		-	-
auto[1]	values[4]	values[3]	5	1			T281	2		T228	1		T292	1
auto[1]	values[4]	values[4]	4	1			T8	1		T206	2		T22	1
auto[1]	values[4]	values[5]	4	1			T153	3		T185	1		-	-
auto[1]	values[4]	values[6]	6	1			T218	1		T281	4		T282	1
auto[1]	values[4]	values[7]	11	1			T37	2		T293	3		T294	2
auto[1]	values[5]	values[0]	8	1			T34	1		T197	3		T22	1
auto[1]	values[5]	values[1]	11	1			T38	1		T220	1		T295	8
auto[1]	values[5]	values[2]	11	1			T36	2		T256	1		T206	1
auto[1]	values[5]	values[3]	11	1			T39	2		T154	1		T296	4
auto[1]	values[5]	values[4]	9	1			T128	1		T297	2		T281	1
auto[1]	values[5]	values[5]	5	1			T32	1		T39	1		T51	1
auto[1]	values[5]	values[6]	8	1			T35	3		T189	1		T285	1
auto[1]	values[5]	values[7]	13	1			T32	1		T167	1		T195	2
auto[1]	values[6]	values[0]	5	1			T237	1		T185	2		T294	1
auto[1]	values[6]	values[1]	7	1			T38	1		T206	2		T185	1
auto[1]	values[6]	values[2]	1	1			T282	1		-	-		-	-
auto[1]	values[6]	values[3]	8	1			T198	1		T224	2		T22	3
auto[1]	values[6]	values[4]	2	1			T286	1		T292	1		-	-
auto[1]	values[6]	values[5]	19	1			T166	2		T54	1		T128	2
auto[1]	values[6]	values[6]	15	1			T54	1		T84	1		T22	3
auto[1]	values[6]	values[7]	5	1			T224	2		T298	2		T299	1
auto[1]	values[7]	values[0]	6	1			T237	4		T300	2		-	-
auto[1]	values[7]	values[1]	9	1			T190	1		T22	6		T51	2
auto[1]	values[7]	values[2]	15	1			T8	3		T29	2		T128	2
auto[1]	values[7]	values[3]	4	1			T35	1		T301	2		T132	1
auto[1]	values[7]	values[4]	10	1			T34	2		T237	1		T281	3
auto[1]	values[7]	values[5]	9	1			T25	4		T38	1		T216	1
auto[1]	values[7]	values[6]	6	1			T229	2		T70	3		T22	1
auto[1]	values[7]	values[7]	8	1			T32	1		T22	2		T212	4