Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1806

1

T1

3

T4

3

T8

9

auto[1]

1803

1

T1

8

T4

6

T8

8

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1999

1

T1

11

T8

11

T12

1

auto[1]

1610

1

T4

9

T8

6

T13

5

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2859

1

T1

5

T4

9

T8

12

auto[1]

750

1

T1

6

T8

5

T14

2

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	706	1			T1	2		T4	1		T8	4
valid[1]	768	1			T1	4		T8	2		T14	2
valid[2]	719	1			T1	3		T4	3		T12	1
valid[3]	711	1			T1	1		T4	3		T8	7
valid[4]	705	1			T1	1		T4	2		T8	4

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	127	1			T8	1		T14	3		T17	1
auto[0]	auto[0]	valid[0]	auto[1]	137	1			T8	1		T14	1		T18	1
auto[0]	auto[0]	valid[1]	auto[0]	154	1			T14	1		T18	1		T26	1
auto[0]	auto[0]	valid[1]	auto[1]	166	1			T86	1		T159	7		T34	1
auto[0]	auto[0]	valid[2]	auto[0]	127	1			T1	1		T12	1		T17	1
auto[0]	auto[0]	valid[2]	auto[1]	154	1			T4	2		T18	2		T86	1
auto[0]	auto[0]	valid[3]	auto[0]	112	1			T14	1		T18	1		T26	2
auto[0]	auto[0]	valid[3]	auto[1]	171	1			T4	1		T8	3		T86	2
auto[0]	auto[0]	valid[4]	auto[0]	126	1			T8	1		T26	1		T307	1
auto[0]	auto[0]	valid[4]	auto[1]	155	1			T13	3		T91	1		T92	1
auto[0]	auto[1]	valid[0]	auto[0]	126	1			T1	1		T14	1		T17	1
auto[0]	auto[1]	valid[0]	auto[1]	169	1			T4	1		T8	1		T13	1
auto[0]	auto[1]	valid[1]	auto[0]	120	1			T1	1		T8	2		T17	1
auto[0]	auto[1]	valid[1]	auto[1]	169	1			T14	1		T18	1		T86	1
auto[0]	auto[1]	valid[2]	auto[0]	110	1			T1	1		T26	1		T25	1
auto[0]	auto[1]	valid[2]	auto[1]	173	1			T4	1		T86	1		T25	1
auto[0]	auto[1]	valid[3]	auto[0]	118	1			T1	1		T8	1		T17	1
auto[0]	auto[1]	valid[3]	auto[1]	152	1			T4	2		T8	1		T18	1
auto[0]	auto[1]	valid[4]	auto[0]	129	1			T8	1		T26	1		T27	1
auto[0]	auto[1]	valid[4]	auto[1]	164	1			T4	2		T13	1		T18	1
auto[1]	auto[0]	valid[0]	auto[0]	86	1			T14	1		T27	1		T30	1
auto[1]	auto[0]	valid[1]	auto[0]	88	1			T1	1		T18	2		T37	1
auto[1]	auto[0]	valid[2]	auto[0]	71	1			T35	1		T251	1		T315	1
auto[1]	auto[0]	valid[3]	auto[0]	76	1			T8	2		T18	1		T25	2
auto[1]	auto[0]	valid[4]	auto[0]	56	1			T1	1		T8	1		T26	1
auto[1]	auto[1]	valid[0]	auto[0]	61	1			T1	1		T8	1		T30	1
auto[1]	auto[1]	valid[1]	auto[0]	71	1			T1	2		T26	1		T27	1
auto[1]	auto[1]	valid[2]	auto[0]	84	1			T1	1		T18	1		T27	1
auto[1]	auto[1]	valid[3]	auto[0]	82	1			T18	2		T230	1		T37	1
auto[1]	auto[1]	valid[4]	auto[0]	75	1			T8	1		T14	1		T17	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal