Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	847	1			T26	24		T30	14		T64	8
all_values[1]	847	1			T26	24		T30	14		T64	8
all_values[2]	847	1			T26	24		T30	14		T64	8
all_values[3]	847	1			T26	24		T30	14		T64	8
all_values[4]	847	1			T26	24		T30	14		T64	8
all_values[5]	847	1			T26	24		T30	14		T64	8
all_values[6]	847	1			T26	24		T30	14		T64	8
all_values[7]	847	1			T26	24		T30	14		T64	8

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3615

1

T26

106

T30

69

T64

40

auto[1]

3161

1

T26

86

T30

43

T64

24

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2713

1

T26

83

T30

43

T64

29

auto[1]

4063

1

T26

109

T30

69

T64

35

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3858

1

T26

116

T30

64

T64

39

auto[1]

2918

1

T26

76

T30

48

T64

25

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	177	1			T26	6		T30	3		T64	1
all_values[0]	auto[0]	auto[0]	auto[1]	76	1			T26	3		T30	4		T64	1
all_values[0]	auto[0]	auto[1]	auto[0]	137	1			T26	1		T64	2		T69	2
all_values[0]	auto[0]	auto[1]	auto[1]	89	1			T26	5		T70	2		T164	2
all_values[0]	auto[1]	auto[0]	auto[1]	219	1			T26	7		T30	5		T64	3
all_values[0]	auto[1]	auto[1]	auto[1]	149	1			T26	2		T30	2		T64	1
all_values[1]	auto[0]	auto[0]	auto[0]	160	1			T26	8		T30	3		T69	1
all_values[1]	auto[0]	auto[0]	auto[1]	77	1			T26	1		T30	2		T64	2
all_values[1]	auto[0]	auto[1]	auto[0]	140	1			T26	1		T64	1		T69	4
all_values[1]	auto[0]	auto[1]	auto[1]	79	1			T26	2		T30	1		T64	2
all_values[1]	auto[1]	auto[0]	auto[1]	227	1			T26	8		T30	3		T64	2
all_values[1]	auto[1]	auto[1]	auto[1]	164	1			T26	4		T30	5		T64	1
all_values[2]	auto[0]	auto[0]	auto[0]	151	1			T26	5		T64	2		T69	1
all_values[2]	auto[0]	auto[0]	auto[1]	87	1			T26	3		T30	1		T64	1
all_values[2]	auto[0]	auto[1]	auto[0]	161	1			T26	3		T30	1		T64	3
all_values[2]	auto[0]	auto[1]	auto[1]	86	1			T26	3		T30	4		T64	1
all_values[2]	auto[1]	auto[0]	auto[1]	189	1			T26	5		T30	5		T64	1
all_values[2]	auto[1]	auto[1]	auto[1]	173	1			T26	5		T30	3		T70	2
all_values[3]	auto[0]	auto[0]	auto[0]	155	1			T26	5		T30	4		T64	4
all_values[3]	auto[0]	auto[0]	auto[1]	92	1			T26	1		T30	2		T69	2
all_values[3]	auto[0]	auto[1]	auto[0]	151	1			T26	5		T30	4		T64	1
all_values[3]	auto[0]	auto[1]	auto[1]	70	1			T26	4		T64	1		T69	1
all_values[3]	auto[1]	auto[0]	auto[1]	202	1			T26	4		T30	2		T64	1
all_values[3]	auto[1]	auto[1]	auto[1]	177	1			T26	5		T30	2		T64	1
all_values[4]	auto[0]	auto[0]	auto[0]	173	1			T26	7		T30	4		T64	2
all_values[4]	auto[0]	auto[0]	auto[1]	81	1			T30	2		T69	2		T164	2
all_values[4]	auto[0]	auto[1]	auto[0]	131	1			T26	4		T30	3		T64	2
all_values[4]	auto[0]	auto[1]	auto[1]	105	1			T26	4		T64	1		T69	1
all_values[4]	auto[1]	auto[0]	auto[1]	179	1			T26	5		T30	3		T64	1
all_values[4]	auto[1]	auto[1]	auto[1]	178	1			T26	4		T30	2		T64	2
all_values[5]	auto[0]	auto[0]	auto[0]	262	1			T26	9		T30	6		T64	3
all_values[5]	auto[0]	auto[1]	auto[0]	225	1			T26	6		T30	3		T69	3
all_values[5]	auto[1]	auto[0]	auto[1]	206	1			T26	3		T30	5		T64	5
all_values[5]	auto[1]	auto[1]	auto[1]	154	1			T26	6		T69	1		T70	4
all_values[6]	auto[0]	auto[0]	auto[0]	184	1			T26	5		T30	5		T64	2
all_values[6]	auto[0]	auto[0]	auto[1]	76	1			T26	3		T30	3		T70	2
all_values[6]	auto[0]	auto[1]	auto[0]	154	1			T26	4		T69	2		T70	2
all_values[6]	auto[0]	auto[1]	auto[1]	74	1			T26	1		T30	1		T64	1
all_values[6]	auto[1]	auto[0]	auto[1]	198	1			T26	6		T30	4		T64	3
all_values[6]	auto[1]	auto[1]	auto[1]	161	1			T26	5		T30	1		T64	2
all_values[7]	auto[0]	auto[0]	auto[0]	176	1			T26	6		T64	4		T69	2
all_values[7]	auto[0]	auto[0]	auto[1]	76	1			T26	1		T30	1		T69	1
all_values[7]	auto[0]	auto[1]	auto[0]	176	1			T26	8		T30	7		T64	2
all_values[7]	auto[0]	auto[1]	auto[1]	77	1			T26	2		T164	1		T152	3
all_values[7]	auto[1]	auto[0]	auto[1]	192	1			T26	5		T30	2		T64	2
all_values[7]	auto[1]	auto[1]	auto[1]	150	1			T26	2		T30	4		T69	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal