Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

50552

1

T1

326

T8

315

T9

11

auto[1]

16524

1

T1

59

T4

9

T8

62

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48774

1

T1

240

T4

9

T8

237

auto[1]

18302

1

T1

145

T8

140

T9

6

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	34315	1			T1	195		T4	9		T8	204
others[1]	5642	1			T1	29		T8	36		T9	1
others[2]	5656	1			T1	39		T8	31		T9	1
others[3]	6471	1			T1	41		T8	36		T12	2
interest[1]	3764	1			T1	21		T8	18		T9	2
interest[4]	22474	1			T1	131		T4	9		T8	123
interest[64]	11228	1			T1	60		T8	52		T9	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	16382	1			T1	100		T8	97		T9	4
auto[0]	auto[0]	others[1]	2707	1			T1	13		T8	18		T14	15
auto[0]	auto[0]	others[2]	2843	1			T1	17		T8	12		T14	11
auto[0]	auto[0]	others[3]	3133	1			T1	18		T8	19		T12	1
auto[0]	auto[0]	interest[1]	1820	1			T1	9		T8	9		T12	1
auto[0]	auto[0]	interest[4]	10710	1			T1	67		T8	63		T9	3
auto[0]	auto[0]	interest[64]	5365	1			T1	24		T8	20		T9	1
auto[0]	auto[1]	others[0]	8509	1			T1	26		T4	9		T8	28
auto[0]	auto[1]	others[1]	1396	1			T1	10		T8	5		T13	5
auto[0]	auto[1]	others[2]	1333	1			T1	7		T8	8		T13	6
auto[0]	auto[1]	others[3]	1547	1			T1	4		T8	7		T13	5
auto[0]	auto[1]	interest[1]	969	1			T1	5		T8	2		T13	3
auto[0]	auto[1]	interest[4]	5660	1			T1	17		T4	9		T8	15
auto[0]	auto[1]	interest[64]	2770	1			T1	7		T8	12		T13	14
auto[1]	auto[0]	others[0]	9424	1			T1	69		T8	79		T9	1
auto[1]	auto[0]	others[1]	1539	1			T1	6		T8	13		T9	1
auto[1]	auto[0]	others[2]	1480	1			T1	15		T8	11		T9	1
auto[1]	auto[0]	others[3]	1791	1			T1	19		T8	10		T12	1
auto[1]	auto[0]	interest[1]	975	1			T1	7		T8	7		T9	2
auto[1]	auto[0]	interest[4]	6104	1			T1	47		T8	45		T9	1
auto[1]	auto[0]	interest[64]	3093	1			T1	29		T8	20		T9	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal