Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2115600	1			T1	1		T2	208		T3	2414
all_values[1]	2115600	1			T1	1		T2	208		T3	2414
all_values[2]	2115600	1			T1	1		T2	208		T3	2414
all_values[3]	2115600	1			T1	1		T2	208		T3	2414
all_values[4]	2115600	1			T1	1		T2	208		T3	2414
all_values[5]	2115600	1			T1	1		T2	208		T3	2414
all_values[6]	2115600	1			T1	1		T2	208		T3	2414
all_values[7]	2115600	1			T1	1		T2	208		T3	2414

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15523784

1

T1

8

T2

1664

T3

19312

auto[1]

1401016

1

T18

590215

T31

35

T23

30

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16906192

1

T1

8

T2

1660

T3

19312

auto[1]

18608

1

T2

4

T15

118

T17

1

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	1882732	1			T1	1		T2	208		T3	2414
all_values[0]	auto[0]	auto[1]	9065	1			T15	90		T17	1		T18	7
all_values[0]	auto[1]	auto[0]	223069	1			T18	98148		T31	2		T23	2
all_values[0]	auto[1]	auto[1]	734	1			T18	214		T31	3		T23	1
all_values[1]	auto[0]	auto[0]	1996170	1			T1	1		T2	208		T3	2414
all_values[1]	auto[0]	auto[1]	4714	1			T15	28		T18	191		T19	8
all_values[1]	auto[1]	auto[0]	114412	1			T18	2		T23	2		T61	2317
all_values[1]	auto[1]	auto[1]	304	1			T18	3		T31	2		T23	1
all_values[2]	auto[0]	auto[0]	1916338	1			T1	1		T2	208		T3	2414
all_values[2]	auto[0]	auto[1]	1506	1			T18	5		T19	8		T25	12
all_values[2]	auto[1]	auto[0]	197440	1			T18	98312		T31	4		T23	1
all_values[2]	auto[1]	auto[1]	316	1			T18	55		T31	2		T61	3
all_values[3]	auto[0]	auto[0]	1930818	1			T1	1		T2	208		T3	2414
all_values[3]	auto[0]	auto[1]	160	1			T18	1		T31	3		T61	1
all_values[3]	auto[1]	auto[0]	184441	1			T18	98363		T31	4		T61	2320
all_values[3]	auto[1]	auto[1]	181	1			T18	8		T23	3		T165	4
all_values[4]	auto[0]	auto[0]	1970825	1			T1	1		T2	208		T3	2414
all_values[4]	auto[0]	auto[1]	189	1			T18	2		T31	3		T140	1
all_values[4]	auto[1]	auto[0]	144401	1			T18	98361		T23	1		T61	2318
all_values[4]	auto[1]	auto[1]	185	1			T18	7		T31	2		T23	2
all_values[5]	auto[0]	auto[0]	1881430	1			T1	1		T2	204		T3	2414
all_values[5]	auto[0]	auto[1]	322	1			T2	4		T18	1		T31	1
all_values[5]	auto[1]	auto[0]	233679	1			T18	98362		T31	1		T23	7
all_values[5]	auto[1]	auto[1]	169	1			T18	8		T31	2		T61	3
all_values[6]	auto[0]	auto[0]	1897701	1			T1	1		T2	208		T3	2414
all_values[6]	auto[0]	auto[1]	183	1			T18	4		T31	1		T165	3
all_values[6]	auto[1]	auto[0]	217512	1			T18	98360		T31	2		T23	5
all_values[6]	auto[1]	auto[1]	204	1			T18	2		T31	6		T23	3
all_values[7]	auto[0]	auto[0]	2031425	1			T1	1		T2	208		T3	2414
all_values[7]	auto[0]	auto[1]	206	1			T31	2		T23	1		T61	3
all_values[7]	auto[1]	auto[0]	83799	1			T18	5		T31	3		T61	1
all_values[7]	auto[1]	auto[1]	170	1			T18	5		T31	2		T23	2