Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	27969	1			T5	6		T6	8		T8	34
auto[SpiFlashAddrCfg]	5771	1			T5	10		T6	2		T8	6
auto[SpiFlashAddr3b]	7235	1			T5	4		T6	6		T7	2
auto[SpiFlashAddr4b]	5897	1			T5	2		T6	6		T8	5

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27253

1

T5

22

T6

22

T7

2

auto[1]

19619

1

T8

18

T10

24

T13

6

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24791

1

T5

8

T6

16

T7

2

auto[1]

22081

1

T5

14

T6

6

T8

31

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	31647	1			T5	8		T6	12		T8	33
values[1]	794	1			T8	3		T15	5		T17	2
values[2]	1124	1			T8	7		T15	4		T17	3
values[3]	1078	1			T8	1		T12	2		T15	8
values[4]	1110	1			T5	4		T8	1		T15	15
values[5]	1179	1			T11	6		T13	2		T15	5
values[6]	1132	1			T5	8		T8	3		T15	12
values[7]	1048	1			T8	3		T15	7		T17	3
values[8]	7760	1			T5	2		T6	10		T7	2

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24729

1

T5

22

T6

22

T8

60

auto[1]

22143

1

T7

2

T15

267

T17

81

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

45269

1

T5

20

T6

20

T7

2

write

1603

1

T5

2

T6

2

T8

2

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

15396

1

T5

8

T6

8

T7

1

valids[0x1]

31476

1

T5

14

T6

14

T7

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1183	1			T6	2		T8	1		T12	2
internal_process_ops[0x5a]	1256	1			T6	2		T8	1		T13	2
internal_process_ops[0x05]	17246	1			T5	2		T6	2		T8	22
internal_process_ops[0x35]	1249	1			T6	2		T10	8		T12	2
internal_process_ops[0x15]	1207	1			T5	4		T6	2		T8	2
internal_process_ops[0x03]	834	1			T7	1		T8	1		T12	2
internal_process_ops[0x0b]	848	1			T8	1		T10	4		T11	4
internal_process_ops[0x3b]	783	1			T8	1		T15	4		T17	1
internal_process_ops[0x6b]	893	1			T10	4		T15	5		T17	3
internal_process_ops[0xbb]	872	1			T8	2		T12	2		T15	4
internal_process_ops[0xeb]	810	1			T6	4		T7	1		T8	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46103

1

T5

22

T6

22

T7

2

auto[1]

769

1

T15

2

T17

2

T18

8

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45333

1

T5

22

T6

22

T7

2

auto[1]

1539

1

T8

3

T15

7

T17

1

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8790

1

T5

6

T6

8

T8

29

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5066

1

T8

4

T10

8

T13

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1719

1

T5

10

T6

2

T8

5

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1349

1

T8

1

T10

6

T42

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2149

1

T5

4

T6

4

T8

3

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1701

1

T8

11

T10

6

T13

4

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1699

1

T6

6

T8

4

T11

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1433

1

T8

1

T10

4

T42

8

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

43

1

T19

1

T28

2

T31

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

39

1

T25

1

T26

1

T40

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

46

1

T8

1

T19

1

T31

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

59

1

T29

2

T32

5

T22

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

49

1

T18

7

T30

4

T31

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

48

1

T25

1

T28

1

T29

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

68

1

T18

2

T25

4

T28

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

55

1

T19

2

T28

1

T30

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

76

1

T6

2

T8

1

T18

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

50

1

T28

1

T32

3

T22

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

33

1

T18

1

T31

4

T32

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

51

1

T30

1

T22

1

T167

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

62

1

T5

2

T12

2

T18

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

40

1

T18

1

T19

3

T29

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

53

1

T28

1

T32

4

T168

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

51

1

T18

1

T25

2

T169

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8214

1

T15

90

T17

21

T18

183

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5518

1

T15

36

T17

8

T18

33

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1185

1

T15

26

T17

3

T18

21

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1121

1

T15

17

T17

12

T18

21

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1492

1

T7

2

T15

34

T17

5

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1477

1

T15

21

T17

9

T18

22

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1224

1

T15

17

T17

6

T18

19

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1132

1

T15

20

T17

13

T18

11

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

52

1

T15

1

T170

1

T75

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

42

1

T85

3

T23

3

T158

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

53

1

T17

2

T171

3

T158

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

47

1

T15

1

T18

2

T158

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

42

1

T44

1

T164

1

T23

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

43

1

T15

1

T17

2

T164

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

45

1

T85

3

T23

3

T75

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

47

1

T18

2

T171

1

T158

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

52

1

T18

1

T85

1

T75

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

50

1

T18

1

T44

1

T164

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

53

1

T15

1

T44

1

T171

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

51

1

T18

1

T171

1

T172

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

53

1

T44

2

T85

4

T23

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

40

1

T76

1

T172

1

T173

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

54

1

T15

2

T18

1

T44

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

56

1

T85

2

T170

1

T174

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3347	1			T8	6		T11	2		T27	2
auto[0]	values[0]	valids[0x1]	12735	1			T5	8		T6	12		T8	27
auto[0]	values[1]	valids[0x1]	397	1			T8	3		T18	3		T19	3
auto[0]	values[2]	valids[0x0]	389	1			T8	7		T18	6		T19	2
auto[0]	values[2]	valids[0x1]	239	1			T18	5		T19	1		T25	5
auto[0]	values[3]	valids[0x0]	369	1			T12	2		T18	5		T19	7
auto[0]	values[3]	valids[0x1]	239	1			T8	1		T18	1		T25	6
auto[0]	values[4]	valids[0x0]	395	1			T8	1		T18	2		T19	2
auto[0]	values[4]	valids[0x1]	229	1			T5	4		T18	1		T19	2
auto[0]	values[5]	valids[0x0]	423	1			T18	11		T19	3		T25	5
auto[0]	values[5]	valids[0x1]	246	1			T11	6		T13	2		T18	3
auto[0]	values[6]	valids[0x0]	434	1			T5	6		T42	2		T18	5
auto[0]	values[6]	valids[0x1]	226	1			T5	2		T8	3		T18	5
auto[0]	values[7]	valids[0x0]	424	1			T8	1		T18	7		T19	3
auto[0]	values[7]	valids[0x1]	180	1			T8	2		T18	4		T19	2
auto[0]	values[8]	valids[0x0]	2785	1			T5	2		T6	8		T8	4
auto[0]	values[8]	valids[0x1]	1672	1			T6	2		T8	5		T10	4
auto[1]	values[0]	valids[0x0]	3164	1			T15	59		T17	25		T18	55
auto[1]	values[0]	valids[0x1]	12401	1			T15	98		T17	17		T18	176
auto[1]	values[1]	valids[0x1]	397	1			T15	5		T17	2		T18	13
auto[1]	values[2]	valids[0x0]	290	1			T15	3		T17	3		T18	8
auto[1]	values[2]	valids[0x1]	206	1			T15	1		T18	8		T85	4
auto[1]	values[3]	valids[0x0]	294	1			T15	7		T17	2		T18	2
auto[1]	values[3]	valids[0x1]	176	1			T15	1		T17	2		T18	1
auto[1]	values[4]	valids[0x0]	292	1			T15	6		T17	6		T18	1
auto[1]	values[4]	valids[0x1]	194	1			T15	9		T17	1		T18	2
auto[1]	values[5]	valids[0x0]	286	1			T15	1		T17	1		T18	4
auto[1]	values[5]	valids[0x1]	224	1			T15	4		T44	2		T85	2
auto[1]	values[6]	valids[0x0]	300	1			T15	4		T17	1		T18	5
auto[1]	values[6]	valids[0x1]	172	1			T15	8		T17	4		T18	2
auto[1]	values[7]	valids[0x0]	251	1			T15	4		T17	1		T18	6
auto[1]	values[7]	valids[0x1]	193	1			T15	3		T17	2		T18	5
auto[1]	values[8]	valids[0x0]	1953	1			T7	1		T15	36		T17	7
auto[1]	values[8]	valids[0x1]	1350	1			T7	1		T15	18		T17	7