Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2701565

1

T5

1281

T6

1

T7

6246

auto[1]

16015

1

T8

20

T15

27

T17

1

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

814195

1

T5

1

T6

1

T7

6246

auto[1]

1903385

1

T5

1280

T8

2856

T15

14286

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	512753	1			T5	1281		T6	1		T7	660
auto[524288:1048575]	296025	1			T15	1925		T17	644		T18	1360
auto[1048576:1572863]	346486	1			T7	8		T15	2720		T17	3
auto[1572864:2097151]	307349	1			T7	5575		T8	256		T15	3090
auto[2097152:2621439]	324155	1			T8	16		T15	1203		T17	264
auto[2621440:3145727]	302678	1			T15	2050		T17	2		T18	2086
auto[3145728:3670015]	312054	1			T15	529		T17	8		T18	4323
auto[3670016:4194303]	316080	1			T7	3		T8	21		T15	2832

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1920029

1

T5

1281

T6

1

T7

12

auto[1]

797551

1

T7

6234

T8

2

T15

2

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2377751

1

T5

1281

T6

1

T7

6246

auto[1]

339829

1

T8

256

T15

1366

T17

389

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	177341	1			T5	1		T6	1		T7	660
auto[0]	auto[0]	auto[0:524287]	auto[1]	277161	1			T5	1280		T8	2578		T18	4484
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	90226	1			T15	8		T17	2		T18	6
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	167520	1			T15	1911		T17	512		T18	258
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	91983	1			T7	8		T15	5		T17	2
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	212028	1			T15	1869		T18	6543		T19	1376
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	90990	1			T7	5575		T15	4		T18	8
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	174800	1			T15	3085		T18	268		T19	5
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	103756	1			T8	5		T15	5		T17	4
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	179159	1			T8	1		T15	1198		T17	2
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	89788	1			T15	10		T17	1		T18	9
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	175560	1			T15	2022		T18	1393		T19	259
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	77702	1			T15	11		T17	3		T18	8
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	188443	1			T15	512		T17	5		T18	3287
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	87025	1			T7	3		T8	7		T15	8
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	181336	1			T8	4		T15	2309		T18	4281
auto[0]	auto[1]	auto[0:524287]	auto[0]	657	1			T18	4		T85	2		T31	3
auto[0]	auto[1]	auto[0:524287]	auto[1]	54707	1			T18	2058		T85	260		T30	256
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	581	1			T17	2		T18	3		T44	6
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	36374	1			T17	128		T18	1089		T44	558
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	220	1			T15	1		T17	1		T18	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	40458	1			T15	845		T18	1		T26	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	462	1			T15	1		T18	2		T25	4
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	39490	1			T8	256		T18	210		T25	3755
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	1018	1			T17	1		T18	13		T29	2
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	38100	1			T17	256		T18	3225		T31	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	239	1			T17	1		T18	6		T28	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	34996	1			T18	641		T85	1		T32	231
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	312	1			T15	2		T18	4		T25	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	43159	1			T15	3		T18	1024		T25	512
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	354	1			T15	1		T18	3		T85	3
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	45620	1			T15	512		T18	128		T85	773
auto[1]	auto[0]	auto[0:524287]	auto[0]	231	1			T18	3		T25	1		T85	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	2220	1			T18	6		T85	4		T164	3
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	120	1			T15	2		T18	2		T85	3
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	954	1			T15	4		T18	2		T85	56
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	150	1			T18	3		T19	1		T25	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1211	1			T18	3		T19	3		T25	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	126	1			T18	2		T19	1		T25	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1069	1			T19	3		T28	13		T44	3
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	160	1			T8	1		T17	1		T18	4
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1672	1			T8	9		T18	32		T25	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	170	1			T15	3		T18	3		T25	3
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1666	1			T15	15		T18	31		T25	12
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	162	1			T25	2		T28	3		T29	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1530	1			T25	1		T28	41		T29	3
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	155	1			T8	2		T15	1		T18	2
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1337	1			T8	8		T15	1		T18	3
auto[1]	auto[1]	auto[0:524287]	auto[0]	35	1			T18	1		T31	1		T164	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	401	1			T18	1		T164	15		T195	23
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	23	1			T44	2		T171	1		T40	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	227	1			T171	1		T40	7		T195	6
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	42	1			T18	1		T26	1		T22	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	394	1			T18	1		T26	2		T170	25
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	34	1			T31	1		T32	1		T158	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	378	1			T32	27		T158	7		T75	4
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	31	1			T18	5		T31	1		T171	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	259	1			T18	16		T171	15		T170	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	28	1			T18	1		T85	1		T32	2
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	231	1			T18	2		T85	13		T32	2
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	44	1			T15	1		T28	1		T29	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	702	1			T28	15		T29	26		T171	10
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	30	1			T170	1		T232	1		T75	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	223	1			T170	1		T75	17		T195	22

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1569792	1			T5	1281		T6	1		T7	12
auto[0]	auto[0]	auto[1]	795026	1			T7	6234		T15	1		T27	1
auto[0]	auto[1]	auto[0]	334518	1			T8	256		T15	1365		T17	389
auto[0]	auto[1]	auto[1]	2229	1			T18	3		T29	1		T85	1
auto[1]	auto[0]	auto[0]	12691	1			T8	18		T15	25		T17	1
auto[1]	auto[0]	auto[1]	242	1			T8	2		T15	1		T18	4
auto[1]	auto[1]	auto[0]	3028	1			T15	1		T18	23		T26	2
auto[1]	auto[1]	auto[1]	54	1			T18	5		T26	1		T28	1