Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

14764

1

T5

22

T6

22

T8

42

auto[1]

9965

1

T8

18

T10

24

T13

6

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3397	1			T18	47		T19	37		T25	40
values[1]	2873	1			T10	24		T18	47		T19	24
values[2]	3443	1			T18	22		T19	20		T25	23
values[3]	2997	1			T5	22		T18	44		T19	40
values[4]	3574	1			T8	35		T12	14		T42	24
values[5]	2900	1			T6	22		T18	43		T35	6
values[6]	2524	1			T13	6		T27	2		T25	20
values[7]	3021	1			T8	25		T11	22		T18	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2616	1			T18	24		T25	51		T244	8
values[1]	3506	1			T5	22		T8	25		T12	14
values[2]	3764	1			T18	43		T28	29		T221	12
values[3]	3112	1			T18	23		T25	46		T26	53
values[4]	3137	1			T27	2		T19	24		T25	41
values[5]	2506	1			T8	35		T11	22		T13	6
values[6]	2977	1			T18	22		T19	40		T35	6
values[7]	3111	1			T6	22		T10	24		T18	46

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	379	1			T196	63		T202	41		T245	13
auto[0]	values[0]	values[1]	375	1			T19	30		T25	13		T30	14
auto[0]	values[0]	values[2]	306	1			T28	21		T32	16		T40	15
auto[0]	values[0]	values[3]	145	1			T28	27		T32	37		T246	4
auto[0]	values[0]	values[4]	312	1			T186	8		T247	18		T209	52
auto[0]	values[0]	values[5]	188	1			T18	24		T29	11		T195	16
auto[0]	values[0]	values[6]	259	1			T25	13		T22	13		T168	12
auto[0]	values[0]	values[7]	191	1			T22	13		T248	2		T166	17
auto[0]	values[1]	values[0]	163	1			T249	2		T166	12		T202	13
auto[0]	values[1]	values[1]	338	1			T26	8		T250	20		T191	43
auto[0]	values[1]	values[2]	207	1			T18	17		T30	15		T251	12
auto[0]	values[1]	values[3]	313	1			T25	11		T22	11		T252	18
auto[0]	values[1]	values[4]	146	1			T19	9		T191	16		T186	8
auto[0]	values[1]	values[5]	145	1			T25	12		T29	13		T168	10
auto[0]	values[1]	values[6]	206	1			T253	6		T232	15		T211	10
auto[0]	values[1]	values[7]	234	1			T18	20		T22	7		T40	72
auto[0]	values[2]	values[0]	275	1			T32	14		T195	13		T211	48
auto[0]	values[2]	values[1]	222	1			T19	2		T25	14		T168	12
auto[0]	values[2]	values[2]	190	1			T195	26		T196	11		T254	8
auto[0]	values[2]	values[3]	329	1			T26	43		T30	13		T40	14
auto[0]	values[2]	values[4]	290	1			T28	13		T22	19		T191	17
auto[0]	values[2]	values[5]	150	1			T186	9		T255	9		T197	19
auto[0]	values[2]	values[6]	207	1			T201	42		T208	10		T211	7
auto[0]	values[2]	values[7]	313	1			T18	17		T200	149		T166	6
auto[0]	values[3]	values[0]	220	1			T18	19		T25	26		T256	42
auto[0]	values[3]	values[1]	269	1			T5	22		T30	11		T61	12
auto[0]	values[3]	values[2]	144	1			T40	33		T189	17		T196	19
auto[0]	values[3]	values[3]	147	1			T25	16		T31	11		T32	14
auto[0]	values[3]	values[4]	193	1			T28	25		T30	12		T40	7
auto[0]	values[3]	values[5]	313	1			T18	16		T40	87		T257	4
auto[0]	values[3]	values[6]	285	1			T19	23		T190	16		T245	14
auto[0]	values[3]	values[7]	324	1			T160	14		T191	28		T222	21
auto[0]	values[4]	values[0]	192	1			T29	11		T168	13		T40	11
auto[0]	values[4]	values[1]	223	1			T12	14		T19	15		T242	10
auto[0]	values[4]	values[2]	295	1			T31	11		T258	2		T166	10
auto[0]	values[4]	values[3]	358	1			T28	17		T29	103		T259	6
auto[0]	values[4]	values[4]	189	1			T25	11		T29	9		T30	14
auto[0]	values[4]	values[5]	197	1			T8	26		T29	16		T31	14
auto[0]	values[4]	values[6]	199	1			T18	14		T25	14		T86	6
auto[0]	values[4]	values[7]	349	1			T25	15		T29	10		T31	11
auto[0]	values[5]	values[0]	115	1			T25	6		T31	10		T40	8
auto[0]	values[5]	values[1]	236	1			T29	16		T31	14		T260	12
auto[0]	values[5]	values[2]	198	1			T18	16		T40	11		T261	2
auto[0]	values[5]	values[3]	159	1			T18	12		T32	31		T262	6
auto[0]	values[5]	values[4]	206	1			T31	13		T186	16		T263	8
auto[0]	values[5]	values[5]	206	1			T29	28		T195	28		T190	18
auto[0]	values[5]	values[6]	338	1			T35	6		T264	6		T265	14
auto[0]	values[5]	values[7]	271	1			T6	22		T61	14		T191	15
auto[0]	values[6]	values[0]	140	1			T201	7		T266	18		T202	15
auto[0]	values[6]	values[1]	301	1			T267	12		T186	40		T195	17
auto[0]	values[6]	values[2]	249	1			T268	58		T189	9		T166	16
auto[0]	values[6]	values[3]	194	1			T28	7		T232	12		T189	12
auto[0]	values[6]	values[4]	390	1			T27	2		T25	11		T30	13
auto[0]	values[6]	values[5]	76	1			T31	5		T162	4		T269	4
auto[0]	values[6]	values[6]	61	1			T216	10		T270	2		T271	2
auto[0]	values[6]	values[7]	145	1			T32	25		T166	13		T77	10
auto[0]	values[7]	values[0]	185	1			T244	8		T31	10		T272	2
auto[0]	values[7]	values[1]	227	1			T8	16		T18	12		T25	7
auto[0]	values[7]	values[2]	342	1			T221	12		T217	18		T189	16
auto[0]	values[7]	values[3]	167	1			T22	14		T215	50		T273	9
auto[0]	values[7]	values[4]	191	1			T70	12		T40	64		T232	7
auto[0]	values[7]	values[5]	186	1			T11	22		T232	12		T274	2
auto[0]	values[7]	values[6]	287	1			T30	15		T22	13		T168	10
auto[0]	values[7]	values[7]	114	1			T214	4		T189	18		T209	12
auto[1]	values[0]	values[0]	126	1			T196	10		T202	10		T245	29
auto[1]	values[0]	values[1]	132	1			T19	7		T25	7		T30	6
auto[1]	values[0]	values[2]	265	1			T28	8		T32	28		T40	121
auto[1]	values[0]	values[3]	223	1			T28	85		T32	11		T202	10
auto[1]	values[0]	values[4]	145	1			T186	17		T209	14		T194	4
auto[1]	values[0]	values[5]	107	1			T18	23		T29	9		T195	4
auto[1]	values[0]	values[6]	142	1			T25	7		T22	7		T168	10
auto[1]	values[0]	values[7]	102	1			T22	11		T166	5		T202	44
auto[1]	values[1]	values[0]	100	1			T166	8		T202	7		T275	8
auto[1]	values[1]	values[1]	128	1			T26	12		T191	19		T186	8
auto[1]	values[1]	values[2]	269	1			T18	6		T30	6		T40	10
auto[1]	values[1]	values[3]	99	1			T25	10		T22	9		T189	12
auto[1]	values[1]	values[4]	142	1			T19	15		T191	7		T186	12
auto[1]	values[1]	values[5]	190	1			T25	8		T29	7		T168	21
auto[1]	values[1]	values[6]	95	1			T232	9		T211	16		T212	8
auto[1]	values[1]	values[7]	98	1			T10	24		T18	4		T22	18
auto[1]	values[2]	values[0]	201	1			T32	11		T195	96		T211	6
auto[1]	values[2]	values[1]	377	1			T19	18		T25	9		T168	8
auto[1]	values[2]	values[2]	120	1			T195	29		T196	9		T276	13
auto[1]	values[2]	values[3]	188	1			T26	10		T30	9		T40	17
auto[1]	values[2]	values[4]	92	1			T28	23		T22	8		T191	5
auto[1]	values[2]	values[5]	106	1			T186	16		T255	11		T197	4
auto[1]	values[2]	values[6]	274	1			T201	8		T157	26		T211	23
auto[1]	values[2]	values[7]	109	1			T18	5		T169	8		T166	14
auto[1]	values[3]	values[0]	86	1			T18	5		T25	5		T277	4
auto[1]	values[3]	values[1]	112	1			T30	11		T61	8		T190	8
auto[1]	values[3]	values[2]	67	1			T40	9		T189	7		T196	4
auto[1]	values[3]	values[3]	193	1			T25	9		T31	11		T32	8
auto[1]	values[3]	values[4]	200	1			T28	10		T30	8		T40	13
auto[1]	values[3]	values[5]	119	1			T18	4		T40	13		T215	46
auto[1]	values[3]	values[6]	79	1			T19	17		T278	20		T190	4
auto[1]	values[3]	values[7]	246	1			T191	26		T222	8		T279	27
auto[1]	values[4]	values[0]	136	1			T29	9		T168	8		T40	9
auto[1]	values[4]	values[1]	179	1			T19	5		T209	17		T211	5
auto[1]	values[4]	values[2]	271	1			T31	9		T33	14		T166	10
auto[1]	values[4]	values[3]	145	1			T28	3		T29	4		T40	9
auto[1]	values[4]	values[4]	150	1			T25	10		T29	11		T30	6
auto[1]	values[4]	values[5]	167	1			T8	9		T42	24		T29	10
auto[1]	values[4]	values[6]	254	1			T18	8		T25	11		T209	17
auto[1]	values[4]	values[7]	270	1			T25	5		T29	10		T31	9
auto[1]	values[5]	values[0]	98	1			T25	14		T31	10		T40	12
auto[1]	values[5]	values[1]	182	1			T29	24		T31	8		T40	59
auto[1]	values[5]	values[2]	148	1			T18	4		T40	9		T279	7
auto[1]	values[5]	values[3]	125	1			T18	11		T32	13		T215	30
auto[1]	values[5]	values[4]	214	1			T31	16		T72	24		T186	7
auto[1]	values[5]	values[5]	125	1			T29	16		T195	20		T190	2
auto[1]	values[5]	values[6]	118	1			T209	8		T194	6		T211	9
auto[1]	values[5]	values[7]	161	1			T61	6		T191	5		T194	8
auto[1]	values[6]	values[0]	136	1			T201	13		T280	2		T202	5
auto[1]	values[6]	values[1]	91	1			T186	20		T195	10		T194	8
auto[1]	values[6]	values[2]	115	1			T189	13		T166	9		T190	54
auto[1]	values[6]	values[3]	158	1			T28	38		T232	8		T189	9
auto[1]	values[6]	values[4]	199	1			T25	9		T30	8		T32	4
auto[1]	values[6]	values[5]	149	1			T13	6		T31	18		T194	25
auto[1]	values[6]	values[6]	51	1			T281	16		T282	11		T283	14
auto[1]	values[6]	values[7]	69	1			T32	6		T199	22		T166	7
auto[1]	values[7]	values[0]	64	1			T31	10		T240	9		T148	6
auto[1]	values[7]	values[1]	114	1			T8	9		T18	8		T25	13
auto[1]	values[7]	values[2]	578	1			T284	14		T189	4		T195	8
auto[1]	values[7]	values[3]	169	1			T22	6		T215	21		T273	11
auto[1]	values[7]	values[4]	78	1			T40	7		T232	14		T191	12
auto[1]	values[7]	values[5]	82	1			T232	12		T209	12		T166	6
auto[1]	values[7]	values[6]	122	1			T30	5		T22	7		T168	10
auto[1]	values[7]	values[7]	115	1			T189	5		T209	30		T196	10