Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2115600	1			T1	1		T2	208		T3	2414
all_pins[1]	2115600	1			T1	1		T2	208		T3	2414
all_pins[2]	2115600	1			T1	1		T2	208		T3	2414
all_pins[3]	2115600	1			T1	1		T2	208		T3	2414
all_pins[4]	2115600	1			T1	1		T2	208		T3	2414
all_pins[5]	2115600	1			T1	1		T2	208		T3	2414
all_pins[6]	2115600	1			T1	1		T2	208		T3	2414
all_pins[7]	2115600	1			T1	1		T2	208		T3	2414

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	16701552	1			T1	8		T2	1664		T3	19312
values[0x1]	223248	1			T18	99063		T31	19		T23	12
transitions[0x0=>0x1]	219760	1			T18	98575		T31	11		T23	10
transitions[0x1=>0x0]	219776	1			T18	98575		T31	11		T23	10

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2114801	1			T1	1		T2	208		T3	2414
all_pins[0]	values[0x1]	799	1			T18	241		T31	3		T23	1
all_pins[0]	transitions[0x0=>0x1]	634	1			T18	239		T31	3		T23	1
all_pins[0]	transitions[0x1=>0x0]	151	1			T18	1		T31	2		T23	1
all_pins[1]	values[0x0]	2115284	1			T1	1		T2	208		T3	2414
all_pins[1]	values[0x1]	316	1			T18	3		T31	2		T23	1
all_pins[1]	transitions[0x0=>0x1]	270	1			T18	3		T23	1		T61	1
all_pins[1]	transitions[0x1=>0x0]	282	1			T18	60		T61	2		T165	4
all_pins[2]	values[0x0]	2115272	1			T1	1		T2	208		T3	2414
all_pins[2]	values[0x1]	328	1			T18	60		T31	2		T61	3
all_pins[2]	transitions[0x0=>0x1]	291	1			T18	60		T31	2		T61	3
all_pins[2]	transitions[0x1=>0x0]	144	1			T18	8		T23	3		T165	4
all_pins[3]	values[0x0]	2115419	1			T1	1		T2	208		T3	2414
all_pins[3]	values[0x1]	181	1			T18	8		T23	3		T165	4
all_pins[3]	transitions[0x0=>0x1]	135	1			T18	4		T23	2		T165	3
all_pins[3]	transitions[0x1=>0x0]	139	1			T18	3		T31	2		T23	1
all_pins[4]	values[0x0]	2115415	1			T1	1		T2	208		T3	2414
all_pins[4]	values[0x1]	185	1			T18	7		T31	2		T23	2
all_pins[4]	transitions[0x0=>0x1]	145	1			T18	4		T31	2		T23	2
all_pins[4]	transitions[0x1=>0x0]	4061	1			T18	485		T31	2		T61	194
all_pins[5]	values[0x0]	2111499	1			T1	1		T2	208		T3	2414
all_pins[5]	values[0x1]	4101	1			T18	488		T31	2		T61	195
all_pins[5]	transitions[0x0=>0x1]	1048	1			T18	11		T61	195		T165	3
all_pins[5]	transitions[0x1=>0x0]	214115	1			T18	97774		T31	4		T23	3
all_pins[6]	values[0x0]	1898432	1			T1	1		T2	208		T3	2414
all_pins[6]	values[0x1]	217168	1			T18	98251		T31	6		T23	3
all_pins[6]	transitions[0x0=>0x1]	217118	1			T18	98251		T31	4		T23	2
all_pins[6]	transitions[0x1=>0x0]	120	1			T18	5		T23	1		T61	1
all_pins[7]	values[0x0]	2115430	1			T1	1		T2	208		T3	2414
all_pins[7]	values[0x1]	170	1			T18	5		T31	2		T23	2
all_pins[7]	transitions[0x0=>0x1]	119	1			T18	3		T23	2		T61	1
all_pins[7]	transitions[0x1=>0x0]	764	1			T18	239		T31	1		T23	1