Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	300	1			T18	1		T19	2		T25	5
auto[ReadAddrCrossIntoMailbox]	261	1			T18	1		T19	1		T25	7
auto[ReadAddrCrossOutOfMailbox]	240	1			T8	2		T18	3		T25	9
auto[ReadAddrCrossAllMailbox]	196	1			T19	4		T26	1		T28	2
auto[ReadAddrOutsideMailbox]	2818	1			T6	4		T8	5		T10	8

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1899

1

T6

2

T8

5

T10

4

auto[1]

1916

1

T6

2

T8

2

T10

4

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	627	1			T8	1		T12	2		T18	7
read_ops[0x0b]	641	1			T8	1		T10	4		T11	4
read_ops[0x3b]	592	1			T8	1		T18	6		T19	2
read_ops[0x6b]	684	1			T10	4		T42	6		T18	8
read_ops[0xbb]	648	1			T8	2		T12	2		T18	5
read_ops[0xeb]	623	1			T6	4		T8	2		T42	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	33	1			T19	1		T25	2		T168	2
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T29	1		T285	2		T190	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T18	1		T25	1		T22	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T22	1		T186	1		T279	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T8	1		T25	3		T32	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	16	1			T191	2		T189	1		T209	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T216	1		T165	1		T194	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T216	1		T30	2		T167	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	222	1			T12	1		T18	2		T19	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	230	1			T12	1		T18	4		T19	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	21	1			T244	1		T30	1		T166	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	24	1			T18	1		T244	1		T40	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T30	1		T218	1		T195	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T29	1		T218	1		T167	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	17	1			T8	1		T30	1		T218	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	16	1			T201	1		T218	2		T195	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T28	1		T216	2		T285	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T216	2		T209	1		T285	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	244	1			T10	2		T11	2		T18	5
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	241	1			T10	2		T11	2		T18	6
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T25	2		T29	1		T32	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	28	1			T29	2		T189	1		T209	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	19	1			T29	1		T22	1		T40	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T22	1		T167	1		T191	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T25	1		T32	1		T191	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T18	1		T25	4		T31	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T19	1		T218	1		T166	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T32	1		T168	1		T218	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	223	1			T8	1		T18	1		T19	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	189	1			T18	4		T28	2		T221	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	18	1			T25	1		T40	1		T232	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T19	1		T31	1		T32	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	17	1			T25	2		T168	1		T209	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	13	1			T32	1		T22	1		T194	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T232	1		T191	2		T189	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T201	1		T186	1		T195	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T31	1		T189	1		T209	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T19	1		T166	1		T285	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	272	1			T10	2		T42	3		T18	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	256	1			T10	2		T42	3		T18	6
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	25	1			T26	1		T29	1		T70	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	18	1			T29	1		T70	1		T207	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T25	1		T216	1		T32	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T216	1		T30	1		T22	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T25	1		T29	1		T32	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T30	2		T165	1		T186	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T26	1		T201	1		T249	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T19	1		T29	1		T249	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	228	1			T12	1		T18	2		T19	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	256	1			T8	2		T12	1		T18	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	21	1			T29	2		T40	1		T167	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	22	1			T29	1		T22	2		T168	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T19	1		T25	1		T26	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T25	2		T29	1		T32	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T18	1		T29	1		T191	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T18	1		T28	2		T191	2
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T19	1		T201	1		T194	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T28	1		T168	1		T195	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	211	1			T6	2		T8	2		T42	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	246	1			T6	2		T42	1		T18	10