Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2903	1			T42	24		T18	22		T19	20
values[1]	3026	1			T6	22		T8	25		T10	24
values[2]	3323	1			T12	14		T18	24		T25	40
values[3]	3142	1			T5	22		T11	22		T27	2
values[4]	2769	1			T18	47		T25	56		T28	64
values[5]	2879	1			T18	40		T19	24		T25	21
values[6]	3628	1			T8	35		T18	21		T19	20
values[7]	3059	1			T13	6		T18	48		T19	37

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3152	1			T42	24		T25	61		T29	20
values[1]	3401	1			T5	22		T18	47		T25	21
values[2]	2599	1			T13	6		T27	2		T18	93
values[3]	3268	1			T8	25		T11	22		T18	21
values[4]	2836	1			T10	24		T18	20		T19	20
values[5]	2663	1			T18	22		T35	6		T25	40
values[6]	3600	1			T6	22		T8	35		T18	20
values[7]	3210	1			T12	14		T18	22		T19	64

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

24336

1

T5

22

T6

22

T8

60

auto[1]

393

1

T18

2

T19

5

T25

4

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	477	1			T42	24		T25	39		T31	17
auto[0]	values[0]	values[1]	660	1			T25	21		T40	28		T284	12
auto[0]	values[0]	values[2]	319	1			T19	17		T26	20		T40	30
auto[0]	values[0]	values[3]	228	1			T189	21		T166	20		T211	20
auto[0]	values[0]	values[4]	119	1			T202	20		T254	8		T286	23
auto[0]	values[0]	values[5]	468	1			T201	50		T31	29		T22	25
auto[0]	values[0]	values[6]	282	1			T216	10		T287	14		T279	20
auto[0]	values[0]	values[7]	301	1			T18	22		T192	31		T197	20
auto[0]	values[1]	values[0]	288	1			T30	20		T165	120		T288	23
auto[0]	values[1]	values[1]	219	1			T30	21		T32	41		T289	8
auto[0]	values[1]	values[2]	411	1			T18	43		T25	22		T72	24
auto[0]	values[1]	values[3]	423	1			T8	25		T31	23		T166	20
auto[0]	values[1]	values[4]	309	1			T10	24		T277	4		T271	2
auto[0]	values[1]	values[5]	393	1			T35	6		T28	45		T190	18
auto[0]	values[1]	values[6]	494	1			T6	22		T235	14		T265	14
auto[0]	values[1]	values[7]	445	1			T19	20		T25	25		T31	22
auto[0]	values[2]	values[0]	232	1			T231	12		T195	43		T240	20
auto[0]	values[2]	values[1]	400	1			T40	42		T167	55		T280	2
auto[0]	values[2]	values[2]	539	1			T18	24		T29	19		T31	20
auto[0]	values[2]	values[3]	578	1			T25	20		T30	21		T22	20
auto[0]	values[2]	values[4]	295	1			T290	10		T217	18		T261	2
auto[0]	values[2]	values[5]	269	1			T25	20		T29	19		T232	23
auto[0]	values[2]	values[6]	719	1			T28	60		T30	18		T32	55
auto[0]	values[2]	values[7]	243	1			T12	14		T86	6		T29	20
auto[0]	values[3]	values[0]	397	1			T29	20		T31	20		T32	21
auto[0]	values[3]	values[1]	518	1			T5	22		T40	99		T291	4
auto[0]	values[3]	values[2]	213	1			T27	2		T30	20		T31	20
auto[0]	values[3]	values[3]	298	1			T11	22		T29	19		T206	20
auto[0]	values[3]	values[4]	471	1			T70	12		T61	17		T191	41
auto[0]	values[3]	values[5]	268	1			T28	49		T40	20		T279	26
auto[0]	values[3]	values[6]	551	1			T186	42		T241	18		T206	76
auto[0]	values[3]	values[7]	371	1			T19	18		T30	22		T22	20
auto[0]	values[4]	values[0]	214	1			T32	45		T214	4		T258	2
auto[0]	values[4]	values[1]	569	1			T18	47		T28	29		T195	98
auto[0]	values[4]	values[2]	145	1			T31	21		T232	24		T255	20
auto[0]	values[4]	values[3]	379	1			T25	31		T61	20		T191	20
auto[0]	values[4]	values[4]	560	1			T29	20		T40	71		T191	20
auto[0]	values[4]	values[5]	162	1			T191	25		T269	4		T209	41
auto[0]	values[4]	values[6]	416	1			T25	23		T264	6		T162	4
auto[0]	values[4]	values[7]	284	1			T28	35		T168	49		T189	22
auto[0]	values[5]	values[0]	399	1			T25	21		T22	25		T195	106
auto[0]	values[5]	values[1]	263	1			T221	12		T31	22		T32	44
auto[0]	values[5]	values[2]	235	1			T191	20		T292	8		T194	17
auto[0]	values[5]	values[3]	388	1			T29	25		T195	39		T190	19
auto[0]	values[5]	values[4]	255	1			T18	20		T267	12		T230	80
auto[0]	values[5]	values[5]	422	1			T29	20		T201	20		T157	22
auto[0]	values[5]	values[6]	294	1			T18	20		T29	19		T293	4
auto[0]	values[5]	values[7]	564	1			T19	24		T191	22		T294	33
auto[0]	values[6]	values[0]	663	1			T30	20		T200	149		T40	18
auto[0]	values[6]	values[1]	410	1			T251	12		T295	18		T191	33
auto[0]	values[6]	values[2]	371	1			T25	20		T232	20		T167	20
auto[0]	values[6]	values[3]	385	1			T18	21		T259	6		T40	19
auto[0]	values[6]	values[4]	420	1			T19	20		T279	51		T212	148
auto[0]	values[6]	values[5]	267	1			T25	20		T28	56		T296	4
auto[0]	values[6]	values[6]	488	1			T8	35		T25	20		T32	30
auto[0]	values[6]	values[7]	571	1			T29	24		T32	33		T40	20
auto[0]	values[7]	values[0]	431	1			T30	20		T22	39		T236	4
auto[0]	values[7]	values[1]	303	1			T33	12		T232	24		T207	10
auto[0]	values[7]	values[2]	312	1			T13	6		T18	25		T211	28
auto[0]	values[7]	values[3]	543	1			T19	37		T29	107		T32	26
auto[0]	values[7]	values[4]	374	1			T26	52		T246	4		T40	90
auto[0]	values[7]	values[5]	374	1			T18	21		T252	18		T189	22
auto[0]	values[7]	values[6]	304	1			T244	8		T250	20		T274	2
auto[0]	values[7]	values[7]	373	1			T191	20		T189	24		T186	20
auto[1]	values[0]	values[0]	11	1			T25	1		T31	3		T168	1
auto[1]	values[0]	values[1]	10	1			T284	2		T209	2		T297	2
auto[1]	values[0]	values[2]	12	1			T19	3		T40	1		T298	3
auto[1]	values[0]	values[3]	5	1			T166	1		T225	1		T298	1
auto[1]	values[0]	values[4]	1	1			T202	1		-	-		-	-
auto[1]	values[0]	values[5]	4	1			T222	1		T282	1		T226	1
auto[1]	values[0]	values[6]	4	1			T148	1		T299	1		T300	1
auto[1]	values[0]	values[7]	2	1			T151	2		-	-		-	-
auto[1]	values[1]	values[0]	3	1			T301	1		T302	2		-	-
auto[1]	values[1]	values[1]	7	1			T30	1		T32	3		T237	2
auto[1]	values[1]	values[2]	7	1			T25	1		T240	2		T123	4
auto[1]	values[1]	values[3]	3	1			T123	1		T46	2		-	-
auto[1]	values[1]	values[4]	5	1			T303	2		T288	1		T304	1
auto[1]	values[1]	values[5]	4	1			T190	2		T305	1		T306	1
auto[1]	values[1]	values[6]	3	1			T191	3		-	-		-	-
auto[1]	values[1]	values[7]	12	1			T167	4		T209	2		T194	3
auto[1]	values[2]	values[0]	1	1			T299	1		-	-		-	-
auto[1]	values[2]	values[1]	1	1			T307	1		-	-		-	-
auto[1]	values[2]	values[2]	8	1			T29	1		T169	2		T195	2
auto[1]	values[2]	values[3]	7	1			T202	4		T288	3		-	-
auto[1]	values[2]	values[4]	2	1			T308	2		-	-		-	-
auto[1]	values[2]	values[5]	4	1			T29	1		T211	1		T309	1
auto[1]	values[2]	values[6]	15	1			T28	1		T30	2		T32	2
auto[1]	values[2]	values[7]	10	1			T32	5		T226	4		T310	1
auto[1]	values[3]	values[0]	11	1			T32	3		T211	1		T225	1
auto[1]	values[3]	values[1]	8	1			T40	1		T206	2		T197	2
auto[1]	values[3]	values[2]	2	1			T209	1		T311	1		-	-
auto[1]	values[3]	values[3]	7	1			T29	1		T196	3		T202	1
auto[1]	values[3]	values[4]	7	1			T61	3		T191	1		T311	2
auto[1]	values[3]	values[5]	3	1			T28	2		T312	1		-	-
auto[1]	values[3]	values[6]	9	1			T186	1		T202	2		T305	1
auto[1]	values[3]	values[7]	8	1			T19	2		T209	1		T225	2
auto[1]	values[4]	values[0]	2	1			T148	1		T308	1		-	-
auto[1]	values[4]	values[1]	13	1			T195	2		T240	2		T77	1
auto[1]	values[4]	values[2]	3	1			T45	3		-	-		-	-
auto[1]	values[4]	values[3]	5	1			T209	3		T166	1		T197	1
auto[1]	values[4]	values[4]	2	1			T279	1		T198	1		-	-
auto[1]	values[4]	values[5]	2	1			T191	2		-	-		-	-
auto[1]	values[4]	values[6]	4	1			T25	2		T190	2		-	-
auto[1]	values[4]	values[7]	9	1			T168	4		T189	1		T77	1
auto[1]	values[5]	values[0]	6	1			T22	2		T195	3		T313	1
auto[1]	values[5]	values[1]	2	1			T195	1		T147	1		-	-
auto[1]	values[5]	values[2]	7	1			T194	3		T307	2		T314	1
auto[1]	values[5]	values[3]	7	1			T29	1		T195	1		T190	1
auto[1]	values[5]	values[4]	8	1			T276	2		T77	3		T154	3
auto[1]	values[5]	values[5]	13	1			T157	4		T191	1		T305	2
auto[1]	values[5]	values[6]	7	1			T29	1		T166	2		T315	2
auto[1]	values[5]	values[7]	9	1			T77	6		T151	1		T312	2
auto[1]	values[6]	values[0]	13	1			T30	1		T40	2		T189	1
auto[1]	values[6]	values[1]	7	1			T190	1		T147	3		T316	1
auto[1]	values[6]	values[2]	6	1			T279	2		T212	2		T282	1
auto[1]	values[6]	values[3]	6	1			T40	1		T298	2		T302	3
auto[1]	values[6]	values[4]	6	1			T212	2		T311	2		T154	2
auto[1]	values[6]	values[5]	5	1			T191	1		T194	1		T317	2
auto[1]	values[6]	values[6]	5	1			T32	1		T245	4		-	-
auto[1]	values[6]	values[7]	5	1			T215	2		T273	1		T77	1
auto[1]	values[7]	values[0]	4	1			T22	1		T209	2		T154	1
auto[1]	values[7]	values[1]	11	1			T33	2		T209	1		T212	2
auto[1]	values[7]	values[2]	9	1			T18	1		T211	2		T318	1
auto[1]	values[7]	values[3]	6	1			T189	2		T245	3		T45	1
auto[1]	values[7]	values[4]	2	1			T26	1		T288	1		-	-
auto[1]	values[7]	values[5]	5	1			T18	1		T196	3		T215	1
auto[1]	values[7]	values[6]	5	1			T191	1		T240	3		T148	1
auto[1]	values[7]	values[7]	3	1			T240	3		-	-		-	-