Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1667

1

T1

1

T2

1

T3

2

auto[1]

1605

1

T3

3

T15

5

T17

2

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1774

1

T2

1

T3

4

T15

6

auto[1]

1498

1

T1

1

T3

1

T17

3

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2622

1

T1

1

T3

4

T15

2

auto[1]

650

1

T2

1

T3

1

T15

4

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	666	1			T3	1		T15	2		T18	2
valid[1]	670	1			T2	1		T18	4		T19	1
valid[2]	641	1			T3	1		T15	2		T17	1
valid[3]	665	1			T1	1		T3	3		T17	2
valid[4]	630	1			T15	2		T19	2		T25	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	121	1			T15	1		T19	1		T25	1
auto[0]	auto[0]	valid[0]	auto[1]	158	1			T36	1		T82	2		T84	1
auto[0]	auto[0]	valid[1]	auto[0]	132	1			T18	3		T38	1		T43	4
auto[0]	auto[0]	valid[1]	auto[1]	165	1			T36	2		T82	4		T84	2
auto[0]	auto[0]	valid[2]	auto[0]	104	1			T25	1		T43	2		T31	1
auto[0]	auto[0]	valid[2]	auto[1]	146	1			T17	1		T36	1		T82	5
auto[0]	auto[0]	valid[3]	auto[0]	106	1			T3	1		T18	2		T38	1
auto[0]	auto[0]	valid[3]	auto[1]	162	1			T1	1		T82	3		T83	1
auto[0]	auto[0]	valid[4]	auto[0]	117	1			T25	1		T38	4		T43	2
auto[0]	auto[0]	valid[4]	auto[1]	122	1			T82	1		T156	5		T349	4
auto[0]	auto[1]	valid[0]	auto[0]	106	1			T3	1		T15	1		T18	1
auto[0]	auto[1]	valid[0]	auto[1]	158	1			T25	1		T36	1		T82	3
auto[0]	auto[1]	valid[1]	auto[0]	106	1			T18	1		T19	1		T25	1
auto[0]	auto[1]	valid[1]	auto[1]	138	1			T25	1		T36	2		T82	1
auto[0]	auto[1]	valid[2]	auto[0]	110	1			T19	1		T25	1		T38	2
auto[0]	auto[1]	valid[2]	auto[1]	165	1			T38	1		T82	3		T83	2
auto[0]	auto[1]	valid[3]	auto[0]	120	1			T3	1		T18	1		T38	2
auto[0]	auto[1]	valid[3]	auto[1]	136	1			T3	1		T17	2		T25	1
auto[0]	auto[1]	valid[4]	auto[0]	102	1			T19	1		T38	1		T43	2
auto[0]	auto[1]	valid[4]	auto[1]	148	1			T36	1		T82	5		T83	1
auto[1]	auto[0]	valid[0]	auto[0]	64	1			T18	1		T25	1		T32	1
auto[1]	auto[0]	valid[1]	auto[0]	74	1			T2	1		T43	2		T31	1
auto[1]	auto[0]	valid[2]	auto[0]	56	1			T3	1		T19	1		T38	2
auto[1]	auto[0]	valid[3]	auto[0]	67	1			T18	1		T31	1		T232	1
auto[1]	auto[0]	valid[4]	auto[0]	73	1			T43	1		T23	1		T332	2
auto[1]	auto[1]	valid[0]	auto[0]	59	1			T43	2		T31	1		T331	1
auto[1]	auto[1]	valid[1]	auto[0]	55	1			T38	1		T43	2		T31	1
auto[1]	auto[1]	valid[2]	auto[0]	60	1			T15	2		T18	1		T38	1
auto[1]	auto[1]	valid[3]	auto[0]	74	1			T18	1		T38	2		T30	2
auto[1]	auto[1]	valid[4]	auto[0]	68	1			T15	2		T19	1		T23	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal