Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	782	1			T18	17		T31	7		T23	7
all_values[1]	782	1			T18	17		T31	7		T23	7
all_values[2]	782	1			T18	17		T31	7		T23	7
all_values[3]	782	1			T18	17		T31	7		T23	7
all_values[4]	782	1			T18	17		T31	7		T23	7
all_values[5]	782	1			T18	17		T31	7		T23	7
all_values[6]	782	1			T18	17		T31	7		T23	7
all_values[7]	782	1			T18	17		T31	7		T23	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3312

1

T18

67

T31

30

T23

38

auto[1]

2944

1

T18

69

T31

26

T23

18

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2501

1

T18

56

T31

23

T23

21

auto[1]

3755

1

T18

80

T31

33

T23

35

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3575

1

T18

70

T31

34

T23

35

auto[1]

2681

1

T18

66

T31

22

T23

21

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	152	1			T18	5		T31	4		T23	1
all_values[0]	auto[0]	auto[0]	auto[1]	75	1			T18	3		T23	2		T61	1
all_values[0]	auto[0]	auto[1]	auto[0]	150	1			T18	1		T23	1		T61	2
all_values[0]	auto[0]	auto[1]	auto[1]	76	1			T31	1		T165	1		T76	3
all_values[0]	auto[1]	auto[0]	auto[1]	163	1			T18	5		T31	1		T23	2
all_values[0]	auto[1]	auto[1]	auto[1]	166	1			T18	3		T31	1		T23	1
all_values[1]	auto[0]	auto[0]	auto[0]	169	1			T18	4		T31	4		T61	2
all_values[1]	auto[0]	auto[0]	auto[1]	68	1			T18	1		T23	2		T61	1
all_values[1]	auto[0]	auto[1]	auto[0]	137	1			T18	1		T23	1		T61	1
all_values[1]	auto[0]	auto[1]	auto[1]	67	1			T18	1		T23	1		T165	2
all_values[1]	auto[1]	auto[0]	auto[1]	183	1			T18	7		T23	3		T61	2
all_values[1]	auto[1]	auto[1]	auto[1]	158	1			T18	3		T31	3		T61	1
all_values[2]	auto[0]	auto[0]	auto[0]	132	1			T31	2		T23	3		T166	4
all_values[2]	auto[0]	auto[0]	auto[1]	92	1			T18	1		T23	1		T61	2
all_values[2]	auto[0]	auto[1]	auto[0]	119	1			T18	6		T31	2		T165	8
all_values[2]	auto[0]	auto[1]	auto[1]	81	1			T31	1		T61	3		T165	3
all_values[2]	auto[1]	auto[0]	auto[1]	207	1			T18	7		T23	3		T76	1
all_values[2]	auto[1]	auto[1]	auto[1]	151	1			T18	3		T31	2		T61	2
all_values[3]	auto[0]	auto[0]	auto[0]	170	1			T18	1		T31	2		T23	3
all_values[3]	auto[0]	auto[0]	auto[1]	60	1			T31	1		T61	1		T165	1
all_values[3]	auto[0]	auto[1]	auto[0]	153	1			T18	4		T31	1		T61	4
all_values[3]	auto[0]	auto[1]	auto[1]	83	1			T18	3		T23	2		T165	2
all_values[3]	auto[1]	auto[0]	auto[1]	168	1			T18	2		T31	2		T23	1
all_values[3]	auto[1]	auto[1]	auto[1]	148	1			T18	7		T31	1		T23	1
all_values[4]	auto[0]	auto[0]	auto[0]	155	1			T18	3		T31	1		T61	1
all_values[4]	auto[0]	auto[0]	auto[1]	83	1			T31	1		T23	3		T76	3
all_values[4]	auto[0]	auto[1]	auto[0]	135	1			T18	3		T23	1		T61	2
all_values[4]	auto[0]	auto[1]	auto[1]	72	1			T18	2		T31	3		T61	2
all_values[4]	auto[1]	auto[0]	auto[1]	176	1			T18	3		T31	1		T23	1
all_values[4]	auto[1]	auto[1]	auto[1]	161	1			T18	6		T31	1		T23	2
all_values[5]	auto[0]	auto[0]	auto[0]	237	1			T18	3		T31	4		T23	2
all_values[5]	auto[0]	auto[1]	auto[0]	204	1			T18	5		T23	3		T61	1
all_values[5]	auto[1]	auto[0]	auto[1]	185	1			T18	3		T31	2		T23	1
all_values[5]	auto[1]	auto[1]	auto[1]	156	1			T18	6		T31	1		T23	1
all_values[6]	auto[0]	auto[0]	auto[0]	167	1			T18	7		T23	2		T61	4
all_values[6]	auto[0]	auto[0]	auto[1]	71	1			T18	1		T23	1		T165	1
all_values[6]	auto[0]	auto[1]	auto[0]	119	1			T18	2		T23	1		T165	1
all_values[6]	auto[0]	auto[1]	auto[1]	88	1			T18	1		T31	2		T23	1
all_values[6]	auto[1]	auto[0]	auto[1]	172	1			T18	4		T31	2		T23	1
all_values[6]	auto[1]	auto[1]	auto[1]	165	1			T18	2		T31	3		T23	1
all_values[7]	auto[0]	auto[0]	auto[0]	163	1			T18	7		T31	2		T23	3
all_values[7]	auto[0]	auto[0]	auto[1]	84	1			T23	1		T61	2		T76	3
all_values[7]	auto[0]	auto[1]	auto[0]	139	1			T18	4		T31	1		T165	4
all_values[7]	auto[0]	auto[1]	auto[1]	74	1			T18	1		T31	2		T165	2
all_values[7]	auto[1]	auto[0]	auto[1]	180	1			T31	1		T23	2		T61	1
all_values[7]	auto[1]	auto[1]	auto[1]	142	1			T18	5		T31	1		T23	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal