Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45564

1

T2

9

T3

115

T15

124

auto[1]

16137

1

T1

1

T3

16

T17

15

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45086

1

T1

1

T2

7

T3

87

auto[1]

16615

1

T2

2

T3

44

T15

50

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	31802	1			T1	1		T2	8		T3	75
others[1]	5205	1			T3	11		T15	15		T17	10
others[2]	5228	1			T3	11		T15	14		T16	1
others[3]	5902	1			T3	9		T15	9		T17	13
interest[1]	3416	1			T3	5		T15	5		T17	8
interest[4]	20815	1			T1	1		T2	4		T3	46
interest[64]	10148	1			T2	1		T3	20		T15	25

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	14783	1			T2	6		T3	35		T15	33
auto[0]	auto[0]	others[1]	2417	1			T3	6		T15	8		T17	3
auto[0]	auto[0]	others[2]	2537	1			T3	7		T15	8		T16	1
auto[0]	auto[0]	others[3]	2723	1			T3	6		T15	7		T17	3
auto[0]	auto[0]	interest[1]	1632	1			T3	4		T15	4		T17	4
auto[0]	auto[0]	interest[4]	9651	1			T2	2		T3	21		T15	18
auto[0]	auto[0]	interest[64]	4857	1			T2	1		T3	13		T15	14
auto[0]	auto[1]	others[0]	8559	1			T1	1		T3	10		T17	9
auto[0]	auto[1]	others[1]	1338	1			T17	2		T18	5		T25	2
auto[0]	auto[1]	others[2]	1267	1			T3	1		T17	1		T18	4
auto[0]	auto[1]	others[3]	1552	1			T3	3		T17	1		T18	3
auto[0]	auto[1]	interest[1]	874	1			T17	2		T18	2		T25	3
auto[0]	auto[1]	interest[4]	5693	1			T1	1		T3	6		T17	4
auto[0]	auto[1]	interest[64]	2547	1			T3	2		T18	5		T25	7
auto[1]	auto[0]	others[0]	8460	1			T2	2		T3	30		T15	23
auto[1]	auto[0]	others[1]	1450	1			T3	5		T15	7		T17	5
auto[1]	auto[0]	others[2]	1424	1			T3	3		T15	6		T17	2
auto[1]	auto[0]	others[3]	1627	1			T15	2		T17	9		T18	10
auto[1]	auto[0]	interest[1]	910	1			T3	1		T15	1		T17	2
auto[1]	auto[0]	interest[4]	5471	1			T2	2		T3	19		T15	15
auto[1]	auto[0]	interest[64]	2744	1			T3	5		T15	11		T17	6

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal