Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2154145	1			T1	1		T2	1		T3	1
all_values[1]	2154145	1			T1	1		T2	1		T3	1
all_values[2]	2154145	1			T1	1		T2	1		T3	1
all_values[3]	2154145	1			T1	1		T2	1		T3	1
all_values[4]	2154145	1			T1	1		T2	1		T3	1
all_values[5]	2154145	1			T1	1		T2	1		T3	1
all_values[6]	2154145	1			T1	1		T2	1		T3	1
all_values[7]	2154145	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16400400

1

T1

8

T2

8

T3

8

auto[1]

832760

1

T16

12991

T17

53

T18

61

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17211855

1

T1

8

T2

8

T3

8

auto[1]

21305

1

T16

185

T17

38

T24

3

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2076401	1			T1	1		T2	1		T3	1
all_values[0]	auto[0]	auto[1]	10799	1			T16	78		T17	9		T24	3
all_values[0]	auto[1]	auto[0]	66516	1			T17	8		T18	9		T19	1
all_values[0]	auto[1]	auto[1]	429	1			T16	2		T17	3		T18	2
all_values[1]	auto[0]	auto[0]	2031637	1			T1	1		T2	1		T3	1
all_values[1]	auto[0]	auto[1]	5180	1			T16	77		T17	4		T28	87
all_values[1]	auto[1]	auto[0]	116764	1			T17	6		T18	4		T19	1639
all_values[1]	auto[1]	auto[1]	564	1			T16	3		T18	1		T19	37
all_values[2]	auto[0]	auto[0]	1980294	1			T1	1		T2	1		T3	1
all_values[2]	auto[0]	auto[1]	1969	1			T16	2		T28	63		T18	5
all_values[2]	auto[1]	auto[0]	171561	1			T16	6479		T17	5		T18	1
all_values[2]	auto[1]	auto[1]	321	1			T16	4		T17	2		T18	1
all_values[3]	auto[0]	auto[0]	2024292	1			T1	1		T2	1		T3	1
all_values[3]	auto[0]	auto[1]	167	1			T17	4		T18	1		T19	1
all_values[3]	auto[1]	auto[0]	129469	1			T16	6		T17	2		T18	7
all_values[3]	auto[1]	auto[1]	217	1			T16	2		T17	1		T18	6
all_values[4]	auto[0]	auto[0]	2047231	1			T1	1		T2	1		T3	1
all_values[4]	auto[0]	auto[1]	235	1			T16	2		T17	2		T18	2
all_values[4]	auto[1]	auto[0]	106505	1			T16	1		T17	7		T18	4
all_values[4]	auto[1]	auto[1]	174	1			T16	3		T18	1		T19	1
all_values[5]	auto[0]	auto[0]	2062431	1			T1	1		T2	1		T3	1
all_values[5]	auto[0]	auto[1]	306	1			T17	1		T18	3		T19	4
all_values[5]	auto[1]	auto[0]	91229	1			T16	6476		T17	3		T18	9
all_values[5]	auto[1]	auto[1]	179	1			T16	5		T17	3		T18	3
all_values[6]	auto[0]	auto[0]	2121316	1			T1	1		T2	1		T3	1
all_values[6]	auto[0]	auto[1]	207	1			T17	2		T18	4		T19	1
all_values[6]	auto[1]	auto[0]	32441	1			T16	6		T17	2		T18	2
all_values[6]	auto[1]	auto[1]	181	1			T16	1		T17	2		T18	2
all_values[7]	auto[0]	auto[0]	2037756	1			T1	1		T2	1		T3	1
all_values[7]	auto[0]	auto[1]	179	1			T16	6		T17	1		T18	1
all_values[7]	auto[1]	auto[0]	116012	1			T16	3		T17	5		T18	6
all_values[7]	auto[1]	auto[1]	198	1			T17	4		T18	3		T19	1