Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	28451	1			T3	2		T5	2		T7	136
auto[SpiFlashAddrCfg]	6135	1			T1	2		T3	10		T7	54
auto[SpiFlashAddr3b]	7189	1			T1	6		T3	2		T7	34
auto[SpiFlashAddr4b]	6073	1			T7	33		T11	5		T13	6

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27651

1

T5

2

T7

183

T8

6

auto[1]

20197

1

T1

8

T3

14

T7

74

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25607

1

T1

6

T3

8

T7

122

auto[1]

22241

1

T1

2

T3

6

T5

2

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	32085	1			T3	2		T5	2		T7	158
values[1]	892	1			T1	2		T3	4		T7	6
values[2]	1282	1			T7	4		T15	3		T22	2
values[3]	1115	1			T7	7		T13	4		T15	1
values[4]	1130	1			T7	6		T14	8		T15	4
values[5]	1143	1			T3	2		T7	5		T8	2
values[6]	1133	1			T7	11		T15	4		T22	6
values[7]	1220	1			T3	4		T7	6		T11	2
values[8]	7848	1			T1	6		T3	2		T7	54

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23266

1

T1

8

T3

14

T5

2

auto[1]

24582

1

T11

10

T15

218

T16

652

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

46175

1

T1

8

T3

14

T5

2

write

1673

1

T7

7

T15

6

T22

6

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

15677

1

T1

6

T3

8

T7

94

valids[0x1]

32171

1

T1

2

T3

6

T5

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1283	1			T5	2		T7	6		T15	3
internal_process_ops[0x5a]	1250	1			T7	1		T13	2		T14	4
internal_process_ops[0x05]	17458	1			T7	85		T15	123		T22	65
internal_process_ops[0x35]	1282	1			T7	5		T8	2		T13	2
internal_process_ops[0x15]	1215	1			T3	2		T7	10		T8	2
internal_process_ops[0x03]	781	1			T1	2		T7	12		T11	3
internal_process_ops[0x0b]	853	1			T7	8		T15	2		T22	5
internal_process_ops[0x3b]	869	1			T7	6		T36	4		T15	1
internal_process_ops[0x6b]	847	1			T7	8		T8	2		T11	2
internal_process_ops[0xbb]	858	1			T1	2		T3	4		T7	7
internal_process_ops[0xeb]	802	1			T1	2		T7	7		T14	4

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47061

1

T1

8

T3

14

T5

2

auto[1]

787

1

T7

4

T15

4

T22

2

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46197

1

T1

8

T3

14

T5

2

auto[1]

1651

1

T7

6

T15

12

T22

6

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8068

1

T5

2

T7

119

T8

4

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

4975

1

T3

2

T7

15

T13

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1634

1

T7

30

T8

2

T12

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1415

1

T1

2

T3

10

T7

22

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1848

1

T7

14

T36

4

T22

5

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1588

1

T1

6

T3

2

T7

17

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1585

1

T7

18

T22

5

T16

21

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1434

1

T7

15

T13

6

T14

4

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

46

1

T7

2

T22

1

T40

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

47

1

T16

1

T37

1

T39

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

36

1

T17

1

T37

1

T39

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

42

1

T16

1

T37

1

T40

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

67

1

T16

4

T37

2

T168

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

44

1

T16

4

T37

2

T40

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

41

1

T7

1

T22

1

T16

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

30

1

T7

1

T41

2

T42

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

56

1

T37

1

T40

2

T30

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

42

1

T22

2

T16

1

T37

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

42

1

T17

1

T37

1

T39

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

45

1

T7

3

T16

3

T38

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

65

1

T22

1

T16

3

T17

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

37

1

T37

1

T40

2

T30

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

38

1

T22

1

T37

1

T168

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

41

1

T16

1

T37

1

T40

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9232

1

T15

116

T16

168

T24

216

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5786

1

T15

40

T16

288

T24

4

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1392

1

T11

5

T15

8

T16

32

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1290

1

T15

12

T16

21

T24

9

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1700

1

T15

13

T16

39

T24

12

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1626

1

T15

5

T16

29

T24

3

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1298

1

T11

5

T15

12

T16

24

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1304

1

T15

6

T16

28

T24

6

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

68

1

T16

1

T28

1

T65

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

46

1

T24

1

T50

2

T19

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

53

1

T16

4

T28

3

T20

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

52

1

T15

2

T65

1

T29

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

71

1

T15

2

T16

2

T28

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

51

1

T16

2

T24

1

T28

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

51

1

T16

4

T65

1

T246

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

49

1

T16

1

T29

1

T246

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

58

1

T28

2

T65

2

T50

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

65

1

T15

1

T16

2

T28

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

65

1

T28

3

T50

1

T61

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

54

1

T16

2

T65

2

T19

4

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

68

1

T16

2

T29

1

T161

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

63

1

T16

2

T29

1

T61

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

61

1

T16

1

T65

1

T50

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

79

1

T15

1

T29

1

T19

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	2931	1			T7	25		T12	2		T22	18
auto[0]	values[0]	valids[0x1]	12098	1			T3	2		T5	2		T7	133
auto[0]	values[1]	valids[0x1]	394	1			T1	2		T3	4		T7	6
auto[0]	values[2]	valids[0x0]	427	1			T7	4		T22	2		T16	6
auto[0]	values[2]	valids[0x1]	217	1			T16	3		T17	5		T39	1
auto[0]	values[3]	valids[0x0]	400	1			T7	4		T13	4		T22	2
auto[0]	values[3]	valids[0x1]	209	1			T7	3		T22	1		T16	5
auto[0]	values[4]	valids[0x0]	392	1			T7	4		T14	4		T22	1
auto[0]	values[4]	valids[0x1]	207	1			T7	2		T14	4		T16	3
auto[0]	values[5]	valids[0x0]	386	1			T3	2		T7	5		T8	2
auto[0]	values[5]	valids[0x1]	226	1			T16	1		T17	5		T38	4
auto[0]	values[6]	valids[0x0]	392	1			T7	9		T22	4		T16	2
auto[0]	values[6]	valids[0x1]	208	1			T7	2		T22	2		T16	3
auto[0]	values[7]	valids[0x0]	443	1			T3	4		T7	5		T36	4
auto[0]	values[7]	valids[0x1]	205	1			T7	1		T22	2		T16	1
auto[0]	values[8]	valids[0x0]	2717	1			T1	6		T3	2		T7	38
auto[0]	values[8]	valids[0x1]	1414	1			T7	16		T13	2		T14	2
auto[1]	values[0]	valids[0x0]	3596	1			T15	20		T16	79		T24	24
auto[1]	values[0]	valids[0x1]	13460	1			T11	3		T15	156		T16	430
auto[1]	values[1]	valids[0x1]	498	1			T15	4		T16	3		T24	3
auto[1]	values[2]	valids[0x0]	372	1			T16	7		T24	2		T28	4
auto[1]	values[2]	valids[0x1]	266	1			T15	3		T16	8		T28	5
auto[1]	values[3]	valids[0x0]	294	1			T16	10		T24	2		T28	3
auto[1]	values[3]	valids[0x1]	212	1			T15	1		T16	4		T24	1
auto[1]	values[4]	valids[0x0]	306	1			T15	1		T16	1		T24	1
auto[1]	values[4]	valids[0x1]	225	1			T15	3		T16	4		T24	1
auto[1]	values[5]	valids[0x0]	276	1			T16	6		T24	1		T65	2
auto[1]	values[5]	valids[0x1]	255	1			T16	2		T28	7		T65	3
auto[1]	values[6]	valids[0x0]	340	1			T15	3		T16	9		T28	1
auto[1]	values[6]	valids[0x1]	193	1			T15	1		T16	2		T24	2
auto[1]	values[7]	valids[0x0]	326	1			T11	2		T15	4		T16	8
auto[1]	values[7]	valids[0x1]	246	1			T15	1		T16	3		T24	2
auto[1]	values[8]	valids[0x0]	2079	1			T11	5		T15	18		T16	39
auto[1]	values[8]	valids[0x1]	1638	1			T15	3		T16	37		T24	4