Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2901981

1

T1

1

T3

1

T5

1932

auto[1]

16161

1

T7

77

T15

118

T22

62

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1077258

1

T1

1

T3

1

T5

1932

auto[1]

1840884

1

T7

15406

T15

7743

T22

4157

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	559897	1			T1	1		T3	1		T5	191
auto[524288:1048575]	356020	1			T5	799		T7	132		T11	207
auto[1048576:1572863]	328937	1			T5	454		T7	1603		T8	84
auto[1572864:2097151]	316111	1			T5	374		T7	4062		T10	198
auto[2097152:2621439]	368026	1			T5	38		T7	1812		T8	9
auto[2621440:3145727]	330748	1			T5	2		T7	2147		T11	3
auto[3145728:3670015]	327772	1			T5	74		T7	30		T8	1607
auto[3670016:4194303]	330631	1			T7	132		T8	1645		T11	2

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1861193

1

T1

1

T3

1

T5

28

auto[1]

1056949

1

T5

1904

T7

5

T8

5417

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2589239

1

T1

1

T3

1

T5

1932

auto[1]

328903

1

T7

4186

T22

267

T16

2593

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	229917	1			T1	1		T3	1		T5	191
auto[0]	auto[0]	auto[0:524287]	auto[1]	296189	1			T7	5511		T15	512		T16	7999
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	134626	1			T5	799		T7	2		T11	207
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	178764	1			T7	128		T15	512		T22	2
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	107794	1			T5	454		T7	5		T8	84
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	172703	1			T7	1593		T15	518		T22	257
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	97531	1			T5	374		T7	7		T10	198
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	172139	1			T7	3540		T15	2		T22	1
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	120229	1			T5	38		T7	7		T8	9
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	192602	1			T7	258		T15	338		T22	2
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	134939	1			T5	2		T7	3		T11	3
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	164267	1			T15	459		T16	1960		T17	1240
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	138665	1			T5	74		T7	4		T8	1607
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	155205	1			T7	2		T15	452		T16	3072
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	105904	1			T7	3		T8	1645		T11	2
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	174789	1			T7	128		T15	4844		T22	3578
auto[0]	auto[1]	auto[0:524287]	auto[0]	311	1			T16	2		T17	2		T146	74
auto[0]	auto[1]	auto[0:524287]	auto[1]	31124	1			T65	256		T19	4		T37	517
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	1140	1			T7	2		T16	4		T28	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	39862	1			T28	256		T65	1280		T37	513
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	2385	1			T7	1		T16	3		T17	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	43766	1			T7	4		T24	1981		T39	1742
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	497	1			T7	1		T22	1		T16	6
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	43688	1			T7	512		T16	641		T28	256
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	189	1			T22	4		T16	1		T65	3
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	52903	1			T7	1520		T22	261		T65	515
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	410	1			T7	5		T16	3		T17	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	29301	1			T7	2139		T16	1522		T17	768
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	836	1			T7	1		T22	1		T16	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	31279	1			T16	132		T29	1741		T50	1050
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	229	1			T7	1		T24	1		T146	46
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	47798	1			T16	256		T246	1		T40	5
auto[1]	auto[0]	auto[0:524287]	auto[0]	215	1			T7	2		T16	4		T17	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	1585	1			T7	23		T16	2		T17	1
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	144	1			T22	2		T16	15		T65	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1136	1			T22	33		T16	195		T65	34
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	185	1			T16	1		T24	1		T28	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1779	1			T16	4		T24	33		T28	3
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	180	1			T7	1		T15	2		T22	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1615	1			T7	1		T15	20		T22	3
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	168	1			T7	2		T22	2		T16	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1565	1			T7	25		T22	17		T16	10
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	156	1			T15	4		T16	3		T28	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1236	1			T15	53		T16	48		T28	5
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	148	1			T7	1		T15	4		T16	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1162	1			T7	22		T15	29		T16	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	155	1			T15	2		T22	1		T16	3
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1547	1			T15	4		T22	3		T16	13
auto[1]	auto[1]	auto[0:524287]	auto[0]	53	1			T37	3		T188	2		T85	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	503	1			T37	2		T188	4		T286	1
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	33	1			T37	1		T40	1		T20	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	315	1			T37	3		T40	49		T20	69
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	31	1			T24	4		T40	1		T30	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	294	1			T24	129		T40	14		T30	6
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	47	1			T16	1		T37	4		T258	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	414	1			T16	12		T37	69		T258	51
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	37	1			T161	1		T40	1		T20	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	333	1			T40	3		T20	34		T51	5
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	42	1			T16	1		T19	2		T40	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	397	1			T16	3		T19	6		T40	38
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	35	1			T16	1		T50	3		T19	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	442	1			T16	3		T50	22		T19	4
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	27	1			T246	1		T40	2		T30	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	182	1			T246	1		T40	4		T258	49

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1523598	1			T1	1		T3	1		T5	28
auto[0]	auto[0]	auto[1]	1052665	1			T5	1904		T7	2		T8	5417
auto[0]	auto[1]	auto[0]	321721	1			T7	4186		T22	267		T16	2570
auto[0]	auto[1]	auto[1]	3997	1			T16	2		T24	2		T146	119
auto[1]	auto[0]	auto[0]	12731	1			T7	74		T15	111		T22	60
auto[1]	auto[0]	auto[1]	245	1			T7	3		T15	7		T22	2
auto[1]	auto[1]	auto[0]	3143	1			T16	21		T24	132		T50	25
auto[1]	auto[1]	auto[1]	42	1			T24	1		T37	1		T40	1