Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13539

1

T5

2

T7

183

T8

6

auto[1]

9727

1

T1

8

T3

14

T7

74

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2772	1			T7	90		T22	45		T37	53
values[1]	3111	1			T1	8		T3	14		T8	6
values[2]	2804	1			T7	20		T22	39		T16	20
values[3]	3558	1			T7	20		T16	96		T146	8
values[4]	2582	1			T5	2		T7	20		T12	2
values[5]	2597	1			T13	14		T14	16		T16	42
values[6]	3151	1			T7	87		T22	24		T16	35
values[7]	2691	1			T7	20		T16	29		T17	80

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2623	1			T3	14		T7	20		T8	6
values[1]	2743	1			T36	8		T22	39		T16	61
values[2]	3247	1			T1	8		T16	50		T17	42
values[3]	3039	1			T5	2		T7	67		T22	54
values[4]	2772	1			T7	60		T37	71		T41	20
values[5]	2682	1			T7	20		T17	20		T100	18
values[6]	3058	1			T7	20		T14	16		T22	45
values[7]	3102	1			T7	70		T22	24		T16	20

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	213	1			T194	14		T196	4		T83	8
auto[0]	values[0]	values[1]	154	1			T37	19		T129	6		T288	8
auto[0]	values[0]	values[2]	185	1			T40	12		T132	11		T289	10
auto[0]	values[0]	values[3]	221	1			T20	11		T30	8		T217	7
auto[0]	values[0]	values[4]	194	1			T7	13		T170	12		T188	14
auto[0]	values[0]	values[5]	336	1			T185	20		T170	29		T85	11
auto[0]	values[0]	values[6]	261	1			T22	38		T37	17		T85	29
auto[0]	values[0]	values[7]	223	1			T7	62		T39	14		T183	13
auto[0]	values[1]	values[0]	174	1			T8	6		T39	10		T187	14
auto[0]	values[1]	values[1]	191	1			T16	21		T37	6		T129	5
auto[0]	values[1]	values[2]	214	1			T168	37		T85	11		T172	12
auto[0]	values[1]	values[3]	280	1			T22	6		T37	26		T167	16
auto[0]	values[1]	values[4]	156	1			T37	43		T30	15		T188	12
auto[0]	values[1]	values[5]	236	1			T173	12		T290	8		T206	13
auto[0]	values[1]	values[6]	293	1			T291	8		T222	9		T178	11
auto[0]	values[1]	values[7]	310	1			T173	16		T186	44		T229	12
auto[0]	values[2]	values[0]	139	1			T132	15		T292	10		T229	19
auto[0]	values[2]	values[1]	164	1			T22	29		T173	10		T293	16
auto[0]	values[2]	values[2]	134	1			T39	8		T40	7		T34	13
auto[0]	values[2]	values[3]	224	1			T20	17		T173	15		T170	9
auto[0]	values[2]	values[4]	253	1			T168	76		T222	13		T174	11
auto[0]	values[2]	values[5]	138	1			T17	15		T201	8		T188	44
auto[0]	values[2]	values[6]	317	1			T7	9		T16	11		T37	11
auto[0]	values[2]	values[7]	157	1			T171	10		T200	4		T85	60
auto[0]	values[3]	values[0]	233	1			T16	8		T37	15		T181	18
auto[0]	values[3]	values[1]	222	1			T37	5		T40	9		T85	18
auto[0]	values[3]	values[2]	225	1			T274	10		T178	30		T230	16
auto[0]	values[3]	values[3]	149	1			T16	13		T43	12		T188	20
auto[0]	values[3]	values[4]	231	1			T7	8		T222	14		T174	10
auto[0]	values[3]	values[5]	182	1			T40	7		T168	11		T257	14
auto[0]	values[3]	values[6]	200	1			T146	8		T37	6		T40	11
auto[0]	values[3]	values[7]	407	1			T40	57		T188	26		T85	11
auto[0]	values[4]	values[0]	112	1			T12	2		T40	13		T44	12
auto[0]	values[4]	values[1]	152	1			T36	8		T16	10		T262	12
auto[0]	values[4]	values[2]	218	1			T16	32		T20	12		T43	36
auto[0]	values[4]	values[3]	234	1			T5	2		T7	13		T22	3
auto[0]	values[4]	values[4]	166	1			T294	4		T188	11		T168	13
auto[0]	values[4]	values[5]	224	1			T170	34		T34	22		T129	61
auto[0]	values[4]	values[6]	218	1			T40	12		T43	88		T85	23
auto[0]	values[4]	values[7]	208	1			T40	11		T30	12		T173	16
auto[0]	values[5]	values[0]	179	1			T202	2		T180	12		T168	16
auto[0]	values[5]	values[1]	178	1			T168	9		T84	14		T172	11
auto[0]	values[5]	values[2]	184	1			T17	14		T206	13		T295	10
auto[0]	values[5]	values[3]	194	1			T16	13		T173	11		T265	12
auto[0]	values[5]	values[4]	164	1			T37	9		T30	8		T91	6
auto[0]	values[5]	values[5]	125	1			T100	18		T101	2		T184	6
auto[0]	values[5]	values[6]	385	1			T37	15		T296	12		T129	231
auto[0]	values[5]	values[7]	209	1			T16	14		T40	12		T209	10
auto[0]	values[6]	values[0]	208	1			T7	11		T275	6		T263	12
auto[0]	values[6]	values[1]	251	1			T17	7		T39	96		T20	15
auto[0]	values[6]	values[2]	253	1			T64	18		T129	20		T210	12
auto[0]	values[6]	values[3]	320	1			T7	41		T16	9		T84	23
auto[0]	values[6]	values[4]	238	1			T7	11		T173	13		T168	24
auto[0]	values[6]	values[5]	205	1			T188	8		T182	6		T129	52
auto[0]	values[6]	values[6]	146	1			T30	21		T188	11		T84	39
auto[0]	values[6]	values[7]	283	1			T22	19		T39	45		T40	14
auto[0]	values[7]	values[0]	138	1			T16	19		T17	22		T37	17
auto[0]	values[7]	values[1]	213	1			T17	14		T30	10		T183	7
auto[0]	values[7]	values[2]	136	1			T17	16		T188	12		T255	10
auto[0]	values[7]	values[3]	225	1			T173	38		T124	5		T206	8
auto[0]	values[7]	values[4]	138	1			T173	9		T297	12		T183	10
auto[0]	values[7]	values[5]	145	1			T7	15		T20	11		T298	6
auto[0]	values[7]	values[6]	210	1			T40	26		T183	15		T170	11
auto[0]	values[7]	values[7]	264	1			T39	49		T43	13		T173	14
auto[1]	values[0]	values[0]	92	1			T206	9		T283	56		T299	16
auto[1]	values[0]	values[1]	83	1			T37	12		T129	14		T178	9
auto[1]	values[0]	values[2]	250	1			T40	8		T132	9		T229	20
auto[1]	values[0]	values[3]	109	1			T20	11		T30	12		T217	13
auto[1]	values[0]	values[4]	103	1			T7	7		T170	12		T188	6
auto[1]	values[0]	values[5]	88	1			T170	15		T85	13		T224	9
auto[1]	values[0]	values[6]	141	1			T22	7		T37	5		T85	3
auto[1]	values[0]	values[7]	119	1			T7	8		T39	6		T183	7
auto[1]	values[1]	values[0]	198	1			T3	14		T39	89		T34	6
auto[1]	values[1]	values[1]	220	1			T16	6		T37	14		T129	118
auto[1]	values[1]	values[2]	204	1			T1	8		T168	4		T85	10
auto[1]	values[1]	values[3]	111	1			T22	28		T37	7		T183	5
auto[1]	values[1]	values[4]	216	1			T37	8		T30	7		T188	47
auto[1]	values[1]	values[5]	121	1			T173	8		T206	7		T217	31
auto[1]	values[1]	values[6]	104	1			T222	11		T178	9		T232	14
auto[1]	values[1]	values[7]	83	1			T173	4		T186	26		T229	8
auto[1]	values[2]	values[0]	197	1			T132	99		T229	21		T230	7
auto[1]	values[2]	values[1]	69	1			T22	10		T173	10		T236	7
auto[1]	values[2]	values[2]	263	1			T39	12		T40	18		T300	20
auto[1]	values[2]	values[3]	163	1			T20	3		T173	5		T170	11
auto[1]	values[2]	values[4]	167	1			T41	20		T168	12		T222	7
auto[1]	values[2]	values[5]	108	1			T17	5		T188	9		T129	86
auto[1]	values[2]	values[6]	197	1			T7	11		T16	9		T37	82
auto[1]	values[2]	values[7]	114	1			T171	14		T189	8		T85	8
auto[1]	values[3]	values[0]	226	1			T16	36		T37	50		T168	6
auto[1]	values[3]	values[1]	354	1			T37	15		T40	150		T203	8
auto[1]	values[3]	values[2]	199	1			T178	5		T230	9		T158	8
auto[1]	values[3]	values[3]	147	1			T16	39		T43	8		T188	8
auto[1]	values[3]	values[4]	178	1			T7	12		T42	12		T166	22
auto[1]	values[3]	values[5]	287	1			T40	13		T168	9		T34	7
auto[1]	values[3]	values[6]	150	1			T37	18		T40	24		T168	36
auto[1]	values[3]	values[7]	168	1			T40	9		T188	18		T85	9
auto[1]	values[4]	values[0]	72	1			T40	10		T173	8		T126	4
auto[1]	values[4]	values[1]	77	1			T16	24		T262	8		T301	7
auto[1]	values[4]	values[2]	129	1			T16	18		T20	8		T43	7
auto[1]	values[4]	values[3]	203	1			T7	7		T22	17		T40	43
auto[1]	values[4]	values[4]	179	1			T188	10		T168	7		T34	30
auto[1]	values[4]	values[5]	185	1			T170	6		T34	21		T129	10
auto[1]	values[4]	values[6]	62	1			T40	8		T43	3		T284	14
auto[1]	values[4]	values[7]	143	1			T40	9		T30	21		T173	39
auto[1]	values[5]	values[0]	83	1			T13	14		T168	32		T222	8
auto[1]	values[5]	values[1]	196	1			T168	21		T84	6		T172	9
auto[1]	values[5]	values[2]	202	1			T17	8		T206	7		T217	14
auto[1]	values[5]	values[3]	146	1			T16	9		T173	13		T132	6
auto[1]	values[5]	values[4]	108	1			T37	11		T30	15		T168	10
auto[1]	values[5]	values[5]	50	1			T302	5		T124	8		T132	19
auto[1]	values[5]	values[6]	82	1			T14	16		T37	6		T129	9
auto[1]	values[5]	values[7]	112	1			T16	6		T40	12		T170	6
auto[1]	values[6]	values[0]	139	1			T7	9		T303	18		T229	14
auto[1]	values[6]	values[1]	89	1			T17	16		T39	10		T20	5
auto[1]	values[6]	values[2]	295	1			T129	23		T233	14		T230	5
auto[1]	values[6]	values[3]	142	1			T7	6		T16	26		T84	10
auto[1]	values[6]	values[4]	159	1			T7	9		T173	7		T168	7
auto[1]	values[6]	values[5]	161	1			T188	12		T129	13		T273	24
auto[1]	values[6]	values[6]	129	1			T30	4		T188	9		T84	34
auto[1]	values[6]	values[7]	133	1			T22	5		T39	29		T40	9
auto[1]	values[7]	values[0]	220	1			T16	10		T17	18		T37	7
auto[1]	values[7]	values[1]	130	1			T17	6		T30	10		T183	14
auto[1]	values[7]	values[2]	156	1			T17	4		T38	20		T188	11
auto[1]	values[7]	values[3]	171	1			T173	12		T124	24		T206	12
auto[1]	values[7]	values[4]	122	1			T173	18		T183	13		T132	14
auto[1]	values[7]	values[5]	91	1			T7	5		T20	11		T236	8
auto[1]	values[7]	values[6]	163	1			T40	9		T183	7		T170	9
auto[1]	values[7]	values[7]	169	1			T39	12		T43	7		T173	6