Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2154145	1			T1	1		T2	1		T3	1
all_pins[1]	2154145	1			T1	1		T2	1		T3	1
all_pins[2]	2154145	1			T1	1		T2	1		T3	1
all_pins[3]	2154145	1			T1	1		T2	1		T3	1
all_pins[4]	2154145	1			T1	1		T2	1		T3	1
all_pins[5]	2154145	1			T1	1		T2	1		T3	1
all_pins[6]	2154145	1			T1	1		T2	1		T3	1
all_pins[7]	2154145	1			T1	1		T2	1		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	17197374	1			T1	8		T2	8		T3	8
values[0x1]	35786	1			T16	25		T17	15		T18	19
transitions[0x0=>0x1]	34286	1			T16	21		T17	12		T18	15
transitions[0x1=>0x0]	34307	1			T16	21		T17	12		T18	16

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2153676	1			T1	1		T2	1		T3	1
all_pins[0]	values[0x1]	469	1			T16	2		T17	3		T18	2
all_pins[0]	transitions[0x0=>0x1]	336	1			T16	1		T17	3		T18	2
all_pins[0]	transitions[0x1=>0x0]	484	1			T16	2		T18	1		T19	39
all_pins[1]	values[0x0]	2153528	1			T1	1		T2	1		T3	1
all_pins[1]	values[0x1]	617	1			T16	3		T18	1		T19	39
all_pins[1]	transitions[0x0=>0x1]	444	1			T16	2		T18	1		T19	36
all_pins[1]	transitions[0x1=>0x0]	169	1			T16	8		T17	2		T18	1
all_pins[2]	values[0x0]	2153803	1			T1	1		T2	1		T3	1
all_pins[2]	values[0x1]	342	1			T16	9		T17	2		T18	1
all_pins[2]	transitions[0x0=>0x1]	284	1			T16	9		T17	2		T18	1
all_pins[2]	transitions[0x1=>0x0]	159	1			T16	2		T17	1		T18	6
all_pins[3]	values[0x0]	2153928	1			T1	1		T2	1		T3	1
all_pins[3]	values[0x1]	217	1			T16	2		T17	1		T18	6
all_pins[3]	transitions[0x0=>0x1]	160	1			T16	2		T17	1		T18	5
all_pins[3]	transitions[0x1=>0x0]	117	1			T16	3		T19	1		T31	4
all_pins[4]	values[0x0]	2153971	1			T1	1		T2	1		T3	1
all_pins[4]	values[0x1]	174	1			T16	3		T18	1		T19	1
all_pins[4]	transitions[0x0=>0x1]	146	1			T16	1		T18	1		T19	1
all_pins[4]	transitions[0x1=>0x0]	1846	1			T16	3		T17	3		T18	3
all_pins[5]	values[0x0]	2152271	1			T1	1		T2	1		T3	1
all_pins[5]	values[0x1]	1874	1			T16	5		T17	3		T18	3
all_pins[5]	transitions[0x0=>0x1]	932	1			T16	5		T17	2		T18	2
all_pins[5]	transitions[0x1=>0x0]	30953	1			T16	1		T17	1		T18	1
all_pins[6]	values[0x0]	2122250	1			T1	1		T2	1		T3	1
all_pins[6]	values[0x1]	31895	1			T16	1		T17	2		T18	2
all_pins[6]	transitions[0x0=>0x1]	31847	1			T16	1		T18	1		T31	1
all_pins[6]	transitions[0x1=>0x0]	150	1			T17	2		T18	2		T19	1
all_pins[7]	values[0x0]	2153947	1			T1	1		T2	1		T3	1
all_pins[7]	values[0x1]	198	1			T17	4		T18	3		T19	1
all_pins[7]	transitions[0x0=>0x1]	137	1			T17	4		T18	2		T19	1
all_pins[7]	transitions[0x1=>0x0]	429	1			T16	2		T17	3		T18	2