Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	284	1			T7	4		T22	2		T16	5
auto[ReadAddrCrossIntoMailbox]	260	1			T7	11		T16	4		T17	4
auto[ReadAddrCrossOutOfMailbox]	239	1			T7	8		T36	6		T22	3
auto[ReadAddrCrossAllMailbox]	174	1			T7	3		T22	1		T17	4
auto[ReadAddrOutsideMailbox]	2611	1			T1	6		T3	4		T7	22

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1734

1

T1

3

T3

2

T7

28

auto[1]

1834

1

T1

3

T3

2

T7

20

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	548	1			T1	2		T7	12		T22	3
read_ops[0x0b]	589	1			T7	8		T22	5		T16	2
read_ops[0x3b]	629	1			T7	6		T36	4		T22	9
read_ops[0x6b]	617	1			T7	8		T8	2		T13	4
read_ops[0xbb]	588	1			T1	2		T3	4		T7	7
read_ops[0xeb]	597	1			T1	2		T7	7		T22	1

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	16	1			T7	1		T16	2		T167	2
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	19	1			T167	2		T291	1		T84	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T7	1		T20	1		T43	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	15	1			T20	1		T188	1		T132	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	19	1			T7	3		T39	1		T129	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	18	1			T20	1		T30	1		T186	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	10	1			T7	1		T39	1		T168	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T17	1		T40	1		T30	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	201	1			T1	1		T7	3		T22	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	209	1			T1	1		T7	3		T22	2
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	23	1			T22	1		T17	1		T183	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	26	1			T22	1		T37	1		T39	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	17	1			T7	2		T17	1		T37	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T7	1		T124	1		T304	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T7	2		T17	1		T187	2
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T37	1		T40	1		T183	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	22	1			T7	1		T17	1		T173	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T22	1		T37	1		T39	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	212	1			T7	1		T22	1		T16	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	204	1			T7	1		T22	1		T17	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	24	1			T37	2		T39	1		T167	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T7	1		T16	1		T39	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	17	1			T84	1		T129	1		T206	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T7	2		T17	1		T34	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	14	1			T36	2		T22	1		T37	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	18	1			T7	1		T36	2		T17	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T17	1		T37	1		T30	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T170	1		T184	1		T188	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	255	1			T7	1		T22	4		T16	7
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	210	1			T7	1		T22	4		T17	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	19	1			T7	1		T16	1		T20	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	23	1			T37	2		T171	1		T188	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T16	1		T20	2		T305	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T7	1		T84	1		T85	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T22	2		T37	1		T39	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T37	1		T188	1		T124	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	10	1			T17	1		T20	1		T183	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	11	1			T173	1		T206	1		T227	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	190	1			T7	3		T8	1		T13	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	275	1			T7	3		T8	1		T13	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T7	1		T39	1		T40	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	24	1			T16	1		T39	1		T187	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T7	1		T16	1		T37	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T39	1		T20	1		T173	2
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T36	1		T187	1		T129	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	19	1			T36	1		T16	1		T187	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T39	2		T40	1		T187	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T187	1		T291	1		T124	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	193	1			T1	1		T3	2		T7	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	223	1			T1	1		T3	2		T7	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	26	1			T167	1		T188	1		T84	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	23	1			T17	1		T37	2		T39	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	18	1			T7	1		T16	1		T40	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T7	2		T16	1		T17	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	13	1			T7	2		T37	1		T85	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T37	1		T40	1		T170	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T7	1		T40	1		T30	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T168	1		T84	1		T124	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	211	1			T1	1		T16	1		T17	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	228	1			T1	1		T7	1		T22	1