Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg
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Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 18 0 18 100.00
Crosses 128 4 124 96.88


Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_data 8 0 8 100.00 100 1 1 0
cp_mask 8 0 8 100.00 100 1 1 0
cp_payload_swap_en 2 0 2 100.00 100 1 1 2


Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_all 128 4 124 96.88 100 1 1 0


Summary for Variable cp_data

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for cp_data

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 2674 1 T3 14 T7 67 T16 64
values[1] 3152 1 T5 2 T7 40 T13 14
values[2] 3078 1 T36 8 T22 39 T16 30
values[3] 3152 1 T7 110 T22 34 T17 43
values[4] 2892 1 T7 20 T12 2 T14 16
values[5] 2676 1 T22 44 T37 128 T39 61
values[6] 2616 1 T1 8 T8 6 T16 54
values[7] 3026 1 T7 20 T16 108 T39 20



Summary for Variable cp_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for cp_mask

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
values[0] 3089 1 T7 67 T13 14 T36 8
values[1] 2523 1 T7 20 T12 2 T100 18
values[2] 2963 1 T1 8 T16 84 T37 161
values[3] 2503 1 T7 20 T8 6 T16 96
values[4] 3104 1 T5 2 T7 90 T22 39
values[5] 2918 1 T7 40 T22 34 T16 29
values[6] 3113 1 T3 14 T7 20 T14 16
values[7] 3053 1 T22 89 T16 55 T17 20



Summary for Variable cp_payload_swap_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_payload_swap_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 22938 1 T1 8 T3 14 T5 2
auto[1] 328 1 T7 4 T22 2 T16 11



Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 128 4 124 96.88 4


Automatically Generated Cross Bins for cr_all

Uncovered bins
cp_payload_swap_encp_datacp_maskCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [values[0]] [values[4]] 0 1 1
[auto[1]] [values[4]] [values[4]] 0 1 1
[auto[1]] [values[6]] [values[1]] 0 1 1
[auto[1]] [values[6]] [values[3]] 0 1 1


Covered bins
cp_payload_swap_encp_datacp_maskCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] values[0] values[0] 306 1 T7 47 T17 20 T166 22
auto[0] values[0] values[1] 360 1 T7 20 T167 16 T20 17
auto[0] values[0] values[2] 156 1 T40 35 T168 19 T169 10
auto[0] values[0] values[3] 381 1 T16 43 T40 74 T30 19
auto[0] values[0] values[4] 273 1 T16 20 T39 20 T170 20
auto[0] values[0] values[5] 438 1 T41 18 T171 24 T172 37
auto[0] values[0] values[6] 444 1 T3 14 T40 157 T30 20
auto[0] values[0] values[7] 276 1 T173 20 T174 20 T175 6
auto[0] values[1] values[0] 769 1 T13 14 T40 25 T30 32
auto[0] values[1] values[1] 347 1 T37 19 T84 20 T124 21
auto[0] values[1] values[2] 357 1 T16 19 T37 20 T40 20
auto[0] values[1] values[3] 208 1 T7 20 T60 18 T64 18
auto[0] values[1] values[4] 384 1 T5 2 T39 33 T173 20
auto[0] values[1] values[5] 383 1 T40 65 T43 43 T170 40
auto[0] values[1] values[6] 439 1 T7 20 T20 22 T168 46
auto[0] values[1] values[7] 207 1 T176 16 T177 52 T178 28
auto[0] values[2] values[0] 441 1 T36 8 T170 46 T179 12
auto[0] values[2] values[1] 522 1 T180 12 T181 18 T124 19
auto[0] values[2] values[2] 368 1 T16 28 T37 90 T39 20
auto[0] values[2] values[3] 331 1 T17 22 T171 22 T182 6
auto[0] values[2] values[4] 381 1 T22 39 T183 20 T184 6
auto[0] values[2] values[5] 376 1 T17 20 T85 19 T124 28
auto[0] values[2] values[6] 292 1 T185 20 T84 23 T186 53
auto[0] values[2] values[7] 322 1 T187 14 T188 20 T168 67
auto[0] values[3] values[0] 399 1 T7 17 T20 22 T188 58
auto[0] values[3] values[1] 421 1 T30 25 T168 39 T84 32
auto[0] values[3] values[2] 422 1 T173 20 T188 20 T189 8
auto[0] values[3] values[3] 500 1 T17 23 T37 65 T91 6
auto[0] values[3] values[4] 526 1 T7 89 T17 20 T39 19
auto[0] values[3] values[5] 339 1 T22 34 T190 16 T191 19
auto[0] values[3] values[6] 258 1 T168 60 T192 16 T193 8
auto[0] values[3] values[7] 246 1 T40 20 T194 14 T195 16
auto[0] values[4] values[0] 295 1 T40 23 T42 8 T196 4
auto[0] values[4] values[1] 152 1 T12 2 T100 18 T101 2
auto[0] values[4] values[2] 486 1 T168 19 T197 20 T132 124
auto[0] values[4] values[3] 182 1 T198 2 T199 4 T124 20
auto[0] values[4] values[4] 206 1 T39 106 T200 4 T34 20
auto[0] values[4] values[5] 283 1 T7 20 T39 99 T132 20
auto[0] values[4] values[6] 547 1 T14 16 T16 22 T17 20
auto[0] values[4] values[7] 695 1 T22 45 T16 31 T17 20
auto[0] values[5] values[0] 288 1 T201 8 T202 2 T168 20
auto[0] values[5] values[1] 247 1 T183 21 T170 20 T85 68
auto[0] values[5] values[2] 296 1 T37 24 T44 12 T203 8
auto[0] values[5] values[3] 333 1 T40 43 T168 20 T85 30
auto[0] values[5] values[4] 345 1 T20 40 T168 20 T204 20
auto[0] values[5] values[5] 328 1 T205 2 T84 31 T131 2
auto[0] values[5] values[6] 345 1 T40 23 T83 8 T34 47
auto[0] values[5] values[7] 453 1 T22 42 T37 101 T39 61
auto[0] values[6] values[0] 227 1 T146 8 T173 55 T183 18
auto[0] values[6] values[1] 199 1 T206 39 T174 23 T207 14
auto[0] values[6] values[2] 498 1 T1 8 T16 34 T37 23
auto[0] values[6] values[3] 343 1 T8 6 T20 20 T188 48
auto[0] values[6] values[4] 373 1 T38 18 T37 31 T132 20
auto[0] values[6] values[5] 337 1 T170 107 T177 20 T208 6
auto[0] values[6] values[6] 341 1 T37 18 T209 10 T84 20
auto[0] values[6] values[7] 275 1 T16 19 T183 21 T34 24
auto[0] values[7] values[0] 299 1 T173 20 T188 18 T85 20
auto[0] values[7] values[1] 249 1 T39 20 T188 26 T210 12
auto[0] values[7] values[2] 336 1 T173 23 T211 16 T177 25
auto[0] values[7] values[3] 187 1 T16 51 T129 20 T212 8
auto[0] values[7] values[4] 585 1 T16 27 T168 23 T132 71
auto[0] values[7] values[5] 391 1 T7 20 T16 28 T173 25
auto[0] values[7] values[6] 413 1 T213 16 T34 45 T129 20
auto[0] values[7] values[7] 532 1 T43 90 T30 21 T173 20
auto[1] values[0] values[0] 7 1 T178 2 T214 2 T215 1
auto[1] values[0] values[1] 3 1 T20 3 - - - -
auto[1] values[0] values[2] 2 1 T168 1 T216 1 - -
auto[1] values[0] values[3] 11 1 T16 1 T40 4 T30 1
auto[1] values[0] values[5] 6 1 T41 2 T217 1 T218 1
auto[1] values[0] values[6] 8 1 T40 2 T30 2 T219 1
auto[1] values[0] values[7] 3 1 T173 1 T220 2 - -
auto[1] values[1] values[0] 19 1 T30 1 T129 1 T206 2
auto[1] values[1] values[1] 3 1 T37 2 T221 1 - -
auto[1] values[1] values[2] 6 1 T16 1 T206 3 T222 1
auto[1] values[1] values[3] 8 1 T85 1 T223 2 T224 3
auto[1] values[1] values[4] 10 1 T39 1 T188 3 T218 2
auto[1] values[1] values[5] 7 1 T40 1 T34 1 T178 2
auto[1] values[1] values[6] 4 1 T225 4 - - - -
auto[1] values[1] values[7] 1 1 T226 1 - - - -
auto[1] values[2] values[0] 8 1 T227 1 T191 1 T220 1
auto[1] values[2] values[1] 6 1 T124 1 T186 1 T215 1
auto[1] values[2] values[2] 8 1 T16 2 T37 3 T228 2
auto[1] values[2] values[3] 9 1 T186 4 T229 1 T230 1
auto[1] values[2] values[4] 3 1 T129 1 T231 2 - -
auto[1] values[2] values[5] 6 1 T85 1 T124 1 T206 3
auto[1] values[2] values[6] 1 1 T174 1 - - - -
auto[1] values[2] values[7] 4 1 T168 1 T132 1 T215 2
auto[1] values[3] values[0] 8 1 T7 3 T188 1 T172 1
auto[1] values[3] values[1] 6 1 T168 2 T84 1 T129 2
auto[1] values[3] values[2] 11 1 T232 1 T233 1 T218 3
auto[1] values[3] values[3] 2 1 T234 2 - - - -
auto[1] values[3] values[4] 7 1 T7 1 T39 1 T129 1
auto[1] values[3] values[5] 3 1 T191 1 T157 2 - -
auto[1] values[3] values[6] 1 1 T168 1 - - - -
auto[1] values[3] values[7] 3 1 T85 3 - - - -
auto[1] values[4] values[0] 5 1 T42 4 T235 1 - -
auto[1] values[4] values[1] 4 1 T229 1 T227 2 T157 1
auto[1] values[4] values[2] 5 1 T168 1 T132 2 T236 1
auto[1] values[4] values[3] 4 1 T237 1 T133 3 - -
auto[1] values[4] values[5] 3 1 T229 2 T238 1 - -
auto[1] values[4] values[6] 7 1 T229 1 T227 1 T239 4
auto[1] values[4] values[7] 18 1 T16 4 T84 2 T85 1
auto[1] values[5] values[0] 9 1 T172 1 T222 2 T228 3
auto[1] values[5] values[1] 2 1 T183 1 T215 1 - -
auto[1] values[5] values[2] 6 1 T240 4 T241 2 - -
auto[1] values[5] values[3] 3 1 T40 1 T242 2 - -
auto[1] values[5] values[4] 4 1 T124 1 T132 2 T221 1
auto[1] values[5] values[5] 5 1 T84 2 T206 1 T229 1
auto[1] values[5] values[6] 3 1 T34 3 - - - -
auto[1] values[5] values[7] 9 1 T22 2 T37 3 T157 1
auto[1] values[6] values[0] 4 1 T183 4 - - - -
auto[1] values[6] values[2] 1 1 T37 1 - - - -
auto[1] values[6] values[4] 3 1 T38 2 T229 1 - -
auto[1] values[6] values[5] 4 1 T170 1 T237 1 T243 2
auto[1] values[6] values[6] 7 1 T37 2 T34 1 T178 1
auto[1] values[6] values[7] 4 1 T16 1 T229 1 T244 1
auto[1] values[7] values[0] 5 1 T188 2 T215 1 T241 2
auto[1] values[7] values[1] 2 1 T226 2 - - - -
auto[1] values[7] values[2] 5 1 T173 1 T177 1 T178 1
auto[1] values[7] values[3] 1 1 T16 1 - - - -
auto[1] values[7] values[4] 4 1 T132 1 T233 1 T245 2
auto[1] values[7] values[5] 9 1 T16 1 T173 2 T133 3
auto[1] values[7] values[6] 3 1 T238 3 - - - -
auto[1] values[7] values[7] 5 1 T43 1 T30 2 T244 2

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