Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1775

1

T2

15

T4

11

T6

3

auto[1]

1796

1

T2

10

T4

10

T6

1

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1766

1

T6

4

T16

2

T17

10

auto[1]

1805

1

T2

25

T4

21

T16

3

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2905

1

T2

25

T4

21

T6

3

auto[1]

666

1

T6

1

T16

2

T17

1

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	726	1			T2	3		T4	5		T16	3
valid[1]	676	1			T2	5		T4	3		T17	1
valid[2]	732	1			T2	3		T4	7		T6	2
valid[3]	686	1			T2	8		T4	1		T6	1
valid[4]	751	1			T2	6		T4	5		T6	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	96	1			T26	1		T28	1		T50	1
auto[0]	auto[0]	valid[0]	auto[1]	176	1			T2	2		T4	1		T16	2
auto[0]	auto[0]	valid[1]	auto[0]	99	1			T50	1		T19	1		T161	1
auto[0]	auto[0]	valid[1]	auto[1]	180	1			T2	3		T4	3		T28	1
auto[0]	auto[0]	valid[2]	auto[0]	117	1			T6	1		T26	1		T28	2
auto[0]	auto[0]	valid[2]	auto[1]	179	1			T2	1		T4	2		T25	2
auto[0]	auto[0]	valid[3]	auto[0]	117	1			T6	1		T17	1		T28	2
auto[0]	auto[0]	valid[3]	auto[1]	167	1			T2	5		T4	1		T16	1
auto[0]	auto[0]	valid[4]	auto[0]	113	1			T26	1		T28	1		T49	1
auto[0]	auto[0]	valid[4]	auto[1]	182	1			T2	4		T4	4		T28	1
auto[0]	auto[1]	valid[0]	auto[0]	125	1			T17	1		T26	2		T28	1
auto[0]	auto[1]	valid[0]	auto[1]	195	1			T2	1		T4	4		T25	3
auto[0]	auto[1]	valid[1]	auto[0]	118	1			T17	1		T28	4		T49	1
auto[0]	auto[1]	valid[1]	auto[1]	163	1			T2	2		T25	1		T26	1
auto[0]	auto[1]	valid[2]	auto[0]	126	1			T6	1		T17	5		T28	1
auto[0]	auto[1]	valid[2]	auto[1]	183	1			T2	2		T4	5		T26	1
auto[0]	auto[1]	valid[3]	auto[0]	92	1			T26	1		T19	2		T37	1
auto[0]	auto[1]	valid[3]	auto[1]	174	1			T2	3		T25	3		T26	1
auto[0]	auto[1]	valid[4]	auto[0]	97	1			T17	1		T26	1		T19	1
auto[0]	auto[1]	valid[4]	auto[1]	206	1			T2	2		T4	1		T25	1
auto[1]	auto[0]	valid[0]	auto[0]	67	1			T16	1		T24	1		T26	1
auto[1]	auto[0]	valid[1]	auto[0]	66	1			T28	2		T29	1		T48	1
auto[1]	auto[0]	valid[2]	auto[0]	64	1			T50	1		T37	1		T20	1
auto[1]	auto[0]	valid[3]	auto[0]	62	1			T16	1		T24	1		T26	1
auto[1]	auto[0]	valid[4]	auto[0]	90	1			T6	1		T26	1		T29	1
auto[1]	auto[1]	valid[0]	auto[0]	67	1			T28	2		T19	1		T321	2
auto[1]	auto[1]	valid[1]	auto[0]	50	1			T26	2		T40	1		T323	1
auto[1]	auto[1]	valid[2]	auto[0]	63	1			T49	2		T50	1		T321	1
auto[1]	auto[1]	valid[3]	auto[0]	74	1			T28	1		T49	1		T50	1
auto[1]	auto[1]	valid[4]	auto[0]	63	1			T17	1		T26	1		T28	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal