Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	858	1			T16	11		T17	10		T18	11
all_values[1]	858	1			T16	11		T17	10		T18	11
all_values[2]	858	1			T16	11		T17	10		T18	11
all_values[3]	858	1			T16	11		T17	10		T18	11
all_values[4]	858	1			T16	11		T17	10		T18	11
all_values[5]	858	1			T16	11		T17	10		T18	11
all_values[6]	858	1			T16	11		T17	10		T18	11
all_values[7]	858	1			T16	11		T17	10		T18	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3633

1

T16

52

T17

42

T18

51

auto[1]

3231

1

T16

36

T17

38

T18

37

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2807

1

T16

31

T17

36

T18

32

auto[1]

4057

1

T16

57

T17

44

T18

56

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3933

1

T16

48

T17

45

T18

48

auto[1]

2931

1

T16

40

T17

35

T18

40

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	178	1			T16	2		T18	2		T19	1
all_values[0]	auto[0]	auto[0]	auto[1]	94	1			T16	2		T18	2		T19	1
all_values[0]	auto[0]	auto[1]	auto[0]	149	1			T17	3		T18	4		T19	2
all_values[0]	auto[0]	auto[1]	auto[1]	82	1			T16	1		T17	2		T30	2
all_values[0]	auto[1]	auto[0]	auto[1]	207	1			T16	6		T17	2		T18	1
all_values[0]	auto[1]	auto[1]	auto[1]	148	1			T17	3		T18	2		T19	1
all_values[1]	auto[0]	auto[0]	auto[0]	151	1			T16	2		T17	1		T20	2
all_values[1]	auto[0]	auto[0]	auto[1]	81	1			T16	4		T17	2		T18	2
all_values[1]	auto[0]	auto[1]	auto[0]	154	1			T17	3		T18	1		T21	1
all_values[1]	auto[0]	auto[1]	auto[1]	87	1			T18	1		T19	2		T20	1
all_values[1]	auto[1]	auto[0]	auto[1]	202	1			T16	3		T17	4		T18	6
all_values[1]	auto[1]	auto[1]	auto[1]	183	1			T16	2		T18	1		T19	3
all_values[2]	auto[0]	auto[0]	auto[0]	149	1			T17	6		T18	3		T21	1
all_values[2]	auto[0]	auto[0]	auto[1]	92	1			T16	1		T18	3		T19	1
all_values[2]	auto[0]	auto[1]	auto[0]	166	1			T16	3		T17	1		T20	1
all_values[2]	auto[0]	auto[1]	auto[1]	84	1			T16	3		T17	1		T18	1
all_values[2]	auto[1]	auto[0]	auto[1]	183	1			T16	2		T17	1		T18	4
all_values[2]	auto[1]	auto[1]	auto[1]	184	1			T16	2		T17	1		T19	2
all_values[3]	auto[0]	auto[0]	auto[0]	196	1			T16	2		T17	2		T18	1
all_values[3]	auto[0]	auto[0]	auto[1]	56	1			T31	1		T165	1		T51	1
all_values[3]	auto[0]	auto[1]	auto[0]	168	1			T16	3		T17	1		T18	1
all_values[3]	auto[0]	auto[1]	auto[1]	95	1			T16	1		T18	3		T19	1
all_values[3]	auto[1]	auto[0]	auto[1]	175	1			T16	3		T17	5		T18	1
all_values[3]	auto[1]	auto[1]	auto[1]	168	1			T16	2		T17	2		T18	5
all_values[4]	auto[0]	auto[0]	auto[0]	170	1			T16	3		T17	2		T18	5
all_values[4]	auto[0]	auto[0]	auto[1]	86	1			T17	1		T18	2		T31	1
all_values[4]	auto[0]	auto[1]	auto[0]	151	1			T17	3		T18	1		T19	3
all_values[4]	auto[0]	auto[1]	auto[1]	76	1			T16	2		T31	2		T32	1
all_values[4]	auto[1]	auto[0]	auto[1]	221	1			T16	3		T17	3		T18	1
all_values[4]	auto[1]	auto[1]	auto[1]	154	1			T16	3		T17	1		T18	2
all_values[5]	auto[0]	auto[0]	auto[0]	259	1			T16	3		T17	2		T18	1
all_values[5]	auto[0]	auto[1]	auto[0]	227	1			T16	3		T17	4		T18	4
all_values[5]	auto[1]	auto[0]	auto[1]	213	1			T16	2		T17	1		T18	3
all_values[5]	auto[1]	auto[1]	auto[1]	159	1			T16	3		T17	3		T18	3
all_values[6]	auto[0]	auto[0]	auto[0]	203	1			T16	4		T17	3		T18	2
all_values[6]	auto[0]	auto[0]	auto[1]	79	1			T17	1		T18	1		T20	1
all_values[6]	auto[0]	auto[1]	auto[0]	130	1			T16	3		T17	2		T18	2
all_values[6]	auto[0]	auto[1]	auto[1]	70	1			T32	1		T165	2		T51	2
all_values[6]	auto[1]	auto[0]	auto[1]	223	1			T16	1		T17	2		T18	5
all_values[6]	auto[1]	auto[1]	auto[1]	153	1			T16	3		T17	2		T18	1
all_values[7]	auto[0]	auto[0]	auto[0]	172	1			T16	2		T17	1		T18	3
all_values[7]	auto[0]	auto[0]	auto[1]	68	1			T16	3		T17	1		T20	1
all_values[7]	auto[0]	auto[1]	auto[0]	184	1			T16	1		T17	2		T18	2
all_values[7]	auto[0]	auto[1]	auto[1]	76	1			T17	1		T18	1		T21	1
all_values[7]	auto[1]	auto[0]	auto[1]	175	1			T16	4		T17	2		T18	3
all_values[7]	auto[1]	auto[1]	auto[1]	183	1			T16	1		T17	3		T18	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal