Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

44397

1

T6

156

T16

190

T17

275

auto[1]

18707

1

T2

230

T4

214

T16

35

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46709

1

T2

230

T4

214

T6

108

auto[1]

16395

1

T6

48

T16

69

T17

95

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	32363	1			T2	116		T4	117		T6	88
others[1]	5233	1			T2	20		T4	14		T6	16
others[2]	5449	1			T2	18		T4	19		T6	9
others[3]	5941	1			T2	21		T4	17		T6	11
interest[1]	3554	1			T2	8		T4	13		T6	9
interest[4]	21062	1			T2	79		T4	72		T6	60
interest[64]	10564	1			T2	47		T4	34		T6	23

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	14220	1			T6	58		T16	78		T17	98
auto[0]	auto[0]	others[1]	2353	1			T6	10		T16	6		T17	7
auto[0]	auto[0]	others[2]	2471	1			T6	7		T16	12		T17	16
auto[0]	auto[0]	others[3]	2710	1			T6	8		T16	7		T17	20
auto[0]	auto[0]	interest[1]	1579	1			T6	9		T16	5		T17	9
auto[0]	auto[0]	interest[4]	9306	1			T6	38		T16	54		T17	60
auto[0]	auto[0]	interest[64]	4669	1			T6	16		T16	13		T17	30
auto[0]	auto[1]	others[0]	9814	1			T2	116		T4	117		T16	12
auto[0]	auto[1]	others[1]	1520	1			T2	20		T4	14		T16	1
auto[0]	auto[1]	others[2]	1606	1			T2	18		T4	19		T16	6
auto[0]	auto[1]	others[3]	1683	1			T2	21		T4	17		T16	6
auto[0]	auto[1]	interest[1]	1040	1			T2	8		T4	13		T16	2
auto[0]	auto[1]	interest[4]	6436	1			T2	79		T4	72		T16	7
auto[0]	auto[1]	interest[64]	3044	1			T2	47		T4	34		T16	8
auto[1]	auto[0]	others[0]	8329	1			T6	30		T16	36		T17	50
auto[1]	auto[0]	others[1]	1360	1			T6	6		T16	9		T17	8
auto[1]	auto[0]	others[2]	1372	1			T6	2		T16	6		T17	8
auto[1]	auto[0]	others[3]	1548	1			T6	3		T16	7		T17	9
auto[1]	auto[0]	interest[1]	935	1			T16	4		T17	8		T24	1
auto[1]	auto[0]	interest[4]	5320	1			T6	22		T16	27		T17	38
auto[1]	auto[0]	interest[64]	2851	1			T6	7		T16	7		T17	12

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal