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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.98 98.30 93.94 98.62 89.36 97.14 95.45 99.05


Total test records in report: 1081
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T1006 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.311630368 Jun 10 05:46:09 PM PDT 24 Jun 10 05:46:12 PM PDT 24 86406019 ps
T1007 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1484686746 Jun 10 05:46:32 PM PDT 24 Jun 10 05:46:33 PM PDT 24 12109404 ps
T1008 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1882507160 Jun 10 05:45:51 PM PDT 24 Jun 10 05:45:53 PM PDT 24 16139069 ps
T1009 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.900578941 Jun 10 05:46:31 PM PDT 24 Jun 10 05:46:32 PM PDT 24 75510863 ps
T1010 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2420464176 Jun 10 05:45:44 PM PDT 24 Jun 10 05:45:45 PM PDT 24 18145853 ps
T1011 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3796442251 Jun 10 05:45:55 PM PDT 24 Jun 10 05:45:58 PM PDT 24 93953273 ps
T1012 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3485841996 Jun 10 05:46:32 PM PDT 24 Jun 10 05:46:36 PM PDT 24 57055862 ps
T1013 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1550504800 Jun 10 05:45:56 PM PDT 24 Jun 10 05:45:58 PM PDT 24 41351625 ps
T247 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1150283488 Jun 10 05:45:49 PM PDT 24 Jun 10 05:45:54 PM PDT 24 1617778201 ps
T1014 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3148945927 Jun 10 05:46:33 PM PDT 24 Jun 10 05:46:34 PM PDT 24 21019197 ps
T1015 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2557971972 Jun 10 05:46:17 PM PDT 24 Jun 10 05:46:21 PM PDT 24 133175474 ps
T249 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.663347841 Jun 10 05:46:03 PM PDT 24 Jun 10 05:46:24 PM PDT 24 1228572456 ps
T1016 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3910663963 Jun 10 05:45:58 PM PDT 24 Jun 10 05:45:59 PM PDT 24 32854597 ps
T1017 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3081537112 Jun 10 05:46:06 PM PDT 24 Jun 10 05:46:11 PM PDT 24 692276958 ps
T1018 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2241582694 Jun 10 05:46:00 PM PDT 24 Jun 10 05:46:02 PM PDT 24 90018790 ps
T1019 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.118788374 Jun 10 05:45:47 PM PDT 24 Jun 10 05:45:49 PM PDT 24 28057595 ps
T1020 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2935586752 Jun 10 05:45:50 PM PDT 24 Jun 10 05:45:52 PM PDT 24 25081023 ps
T1021 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3217793421 Jun 10 05:46:16 PM PDT 24 Jun 10 05:46:20 PM PDT 24 54229460 ps
T1022 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1031694965 Jun 10 05:46:35 PM PDT 24 Jun 10 05:46:36 PM PDT 24 22397534 ps
T88 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2618669189 Jun 10 05:45:49 PM PDT 24 Jun 10 05:45:50 PM PDT 24 18514703 ps
T1023 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.529560121 Jun 10 05:46:16 PM PDT 24 Jun 10 05:46:19 PM PDT 24 688334500 ps
T1024 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.765351 Jun 10 05:45:44 PM PDT 24 Jun 10 05:45:59 PM PDT 24 4348438306 ps
T1025 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.288445167 Jun 10 05:46:30 PM PDT 24 Jun 10 05:46:32 PM PDT 24 22826661 ps
T1026 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3169565317 Jun 10 05:46:11 PM PDT 24 Jun 10 05:46:12 PM PDT 24 35447991 ps
T1027 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2214591924 Jun 10 05:45:48 PM PDT 24 Jun 10 05:46:27 PM PDT 24 24610986047 ps
T1028 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.80110652 Jun 10 05:46:11 PM PDT 24 Jun 10 05:46:15 PM PDT 24 125171852 ps
T1029 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2358874448 Jun 10 05:45:51 PM PDT 24 Jun 10 05:45:53 PM PDT 24 46392682 ps
T1030 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2521075774 Jun 10 05:46:14 PM PDT 24 Jun 10 05:46:18 PM PDT 24 155399156 ps
T1031 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.4220810874 Jun 10 05:46:15 PM PDT 24 Jun 10 05:46:17 PM PDT 24 199830617 ps
T1032 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.172785779 Jun 10 05:45:48 PM PDT 24 Jun 10 05:45:52 PM PDT 24 198637939 ps
T1033 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1744428219 Jun 10 05:46:02 PM PDT 24 Jun 10 05:46:03 PM PDT 24 10567828 ps
T1034 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2626387722 Jun 10 05:46:03 PM PDT 24 Jun 10 05:46:07 PM PDT 24 143077046 ps
T1035 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.727845618 Jun 10 05:46:07 PM PDT 24 Jun 10 05:46:12 PM PDT 24 631596890 ps
T1036 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.4183473291 Jun 10 05:46:31 PM PDT 24 Jun 10 05:46:33 PM PDT 24 40750459 ps
T1037 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3487276359 Jun 10 05:45:55 PM PDT 24 Jun 10 05:45:59 PM PDT 24 249580123 ps
T1038 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.207700774 Jun 10 05:46:04 PM PDT 24 Jun 10 05:46:07 PM PDT 24 106413038 ps
T1039 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3020926601 Jun 10 05:46:01 PM PDT 24 Jun 10 05:46:03 PM PDT 24 248798736 ps
T1040 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.4018754496 Jun 10 05:46:08 PM PDT 24 Jun 10 05:46:20 PM PDT 24 201452442 ps
T1041 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.457837358 Jun 10 05:45:57 PM PDT 24 Jun 10 05:45:59 PM PDT 24 394514917 ps
T1042 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3914624735 Jun 10 05:46:08 PM PDT 24 Jun 10 05:46:09 PM PDT 24 21991296 ps
T1043 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2163447932 Jun 10 05:46:07 PM PDT 24 Jun 10 05:46:09 PM PDT 24 89878415 ps
T1044 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.657099913 Jun 10 05:45:40 PM PDT 24 Jun 10 05:45:41 PM PDT 24 10714954 ps
T1045 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.93291608 Jun 10 05:45:48 PM PDT 24 Jun 10 05:45:50 PM PDT 24 91835255 ps
T1046 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2027409096 Jun 10 05:46:03 PM PDT 24 Jun 10 05:46:05 PM PDT 24 104443152 ps
T1047 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1510320182 Jun 10 05:45:56 PM PDT 24 Jun 10 05:46:20 PM PDT 24 3966039481 ps
T1048 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3569665427 Jun 10 05:46:10 PM PDT 24 Jun 10 05:46:14 PM PDT 24 62496601 ps
T1049 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1942027684 Jun 10 05:46:29 PM PDT 24 Jun 10 05:46:30 PM PDT 24 89657373 ps
T1050 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1366944644 Jun 10 05:45:44 PM PDT 24 Jun 10 05:45:54 PM PDT 24 315335795 ps
T1051 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.404429590 Jun 10 05:45:58 PM PDT 24 Jun 10 05:46:02 PM PDT 24 461839861 ps
T1052 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3652273531 Jun 10 05:46:16 PM PDT 24 Jun 10 05:46:18 PM PDT 24 43212466 ps
T1053 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3986218342 Jun 10 05:46:14 PM PDT 24 Jun 10 05:46:22 PM PDT 24 905252872 ps
T1054 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1193948024 Jun 10 05:46:02 PM PDT 24 Jun 10 05:46:11 PM PDT 24 337193001 ps
T1055 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2228842865 Jun 10 05:46:11 PM PDT 24 Jun 10 05:46:15 PM PDT 24 148836427 ps
T250 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2694191781 Jun 10 05:46:01 PM PDT 24 Jun 10 05:46:22 PM PDT 24 4208792842 ps
T1056 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1496783261 Jun 10 05:46:12 PM PDT 24 Jun 10 05:46:17 PM PDT 24 153785692 ps
T1057 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.4126671897 Jun 10 05:45:56 PM PDT 24 Jun 10 05:46:00 PM PDT 24 349393179 ps
T1058 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3675660394 Jun 10 05:46:31 PM PDT 24 Jun 10 05:46:32 PM PDT 24 39753421 ps
T1059 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3497060466 Jun 10 05:46:33 PM PDT 24 Jun 10 05:46:35 PM PDT 24 37496708 ps
T1060 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3466889654 Jun 10 05:45:38 PM PDT 24 Jun 10 05:45:53 PM PDT 24 208464773 ps
T1061 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1470509981 Jun 10 05:46:30 PM PDT 24 Jun 10 05:46:31 PM PDT 24 78333529 ps
T1062 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3187790030 Jun 10 05:46:30 PM PDT 24 Jun 10 05:46:32 PM PDT 24 41162556 ps
T1063 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1260575043 Jun 10 05:46:19 PM PDT 24 Jun 10 05:46:21 PM PDT 24 397229974 ps
T1064 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.100431917 Jun 10 05:45:39 PM PDT 24 Jun 10 05:45:42 PM PDT 24 188641339 ps
T1065 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.354379712 Jun 10 05:46:17 PM PDT 24 Jun 10 05:46:19 PM PDT 24 61108575 ps
T1066 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1238484834 Jun 10 05:45:48 PM PDT 24 Jun 10 05:45:51 PM PDT 24 224168291 ps
T1067 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3535100262 Jun 10 05:46:16 PM PDT 24 Jun 10 05:46:19 PM PDT 24 249593133 ps
T1068 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1798650068 Jun 10 05:45:44 PM PDT 24 Jun 10 05:45:45 PM PDT 24 25214763 ps
T1069 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3665244106 Jun 10 05:45:56 PM PDT 24 Jun 10 05:46:11 PM PDT 24 1419685872 ps
T1070 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2366464657 Jun 10 05:46:19 PM PDT 24 Jun 10 05:46:20 PM PDT 24 20608297 ps
T1071 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1267523962 Jun 10 05:45:56 PM PDT 24 Jun 10 05:45:59 PM PDT 24 46600823 ps
T1072 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.4262372702 Jun 10 05:46:13 PM PDT 24 Jun 10 05:46:20 PM PDT 24 420365999 ps
T1073 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3078211645 Jun 10 05:45:52 PM PDT 24 Jun 10 05:45:55 PM PDT 24 77006929 ps
T1074 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2092862611 Jun 10 05:46:15 PM PDT 24 Jun 10 05:46:20 PM PDT 24 210191628 ps
T1075 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3087561214 Jun 10 05:46:32 PM PDT 24 Jun 10 05:46:34 PM PDT 24 79141346 ps
T1076 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1491423195 Jun 10 05:45:46 PM PDT 24 Jun 10 05:45:47 PM PDT 24 29446278 ps
T1077 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3874718508 Jun 10 05:46:05 PM PDT 24 Jun 10 05:46:10 PM PDT 24 177520748 ps
T1078 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2271833330 Jun 10 05:46:16 PM PDT 24 Jun 10 05:46:25 PM PDT 24 739557844 ps
T1079 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2127132369 Jun 10 05:46:17 PM PDT 24 Jun 10 05:46:40 PM PDT 24 3410380998 ps
T1080 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3260367255 Jun 10 05:46:30 PM PDT 24 Jun 10 05:46:31 PM PDT 24 11823263 ps
T89 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1197666378 Jun 10 05:45:44 PM PDT 24 Jun 10 05:45:46 PM PDT 24 31374224 ps
T1081 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1775777882 Jun 10 05:45:51 PM PDT 24 Jun 10 05:46:10 PM PDT 24 306216099 ps

Test location /workspace/coverage/default/19.spi_device_flash_all.483940507
Short name T7
Test name
Test status
Simulation time 200656865388 ps
CPU time 348.96 seconds
Started Jun 10 05:51:48 PM PDT 24
Finished Jun 10 05:57:37 PM PDT 24
Peak memory 257660 kb
Host smart-0ef8c85a-dc03-4fda-a35a-e6e70fe49424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483940507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.483940507
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.4259324864
Short name T16
Test name
Test status
Simulation time 64296517038 ps
CPU time 503.73 seconds
Started Jun 10 05:51:20 PM PDT 24
Finished Jun 10 05:59:45 PM PDT 24
Peak memory 282376 kb
Host smart-43f9f1b4-c71d-4487-a217-310ea57d44a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259324864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.4259324864
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.666464886
Short name T22
Test name
Test status
Simulation time 256215338345 ps
CPU time 180.23 seconds
Started Jun 10 05:52:59 PM PDT 24
Finished Jun 10 05:55:59 PM PDT 24
Peak memory 233148 kb
Host smart-21335103-5c50-4f40-8d29-fbdc00d04999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666464886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.666464886
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.765255611
Short name T99
Test name
Test status
Simulation time 339051714 ps
CPU time 7.95 seconds
Started Jun 10 05:46:02 PM PDT 24
Finished Jun 10 05:46:10 PM PDT 24
Peak memory 215256 kb
Host smart-0d6f6bcf-4d80-4142-a882-da5d593aae3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765255611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device
_tl_intg_err.765255611
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.503210739
Short name T17
Test name
Test status
Simulation time 4745188378 ps
CPU time 66.18 seconds
Started Jun 10 05:52:57 PM PDT 24
Finished Jun 10 05:54:04 PM PDT 24
Peak memory 254548 kb
Host smart-9fc4a185-4e35-4968-816c-e52a3484d8a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503210739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stres
s_all.503210739
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.2318863107
Short name T49
Test name
Test status
Simulation time 2577520517 ps
CPU time 26.1 seconds
Started Jun 10 05:53:00 PM PDT 24
Finished Jun 10 05:53:26 PM PDT 24
Peak memory 217072 kb
Host smart-e72a3535-bd8c-4795-911f-7483719af0a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318863107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2318863107
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.2805802147
Short name T188
Test name
Test status
Simulation time 45576812893 ps
CPU time 376.86 seconds
Started Jun 10 05:50:47 PM PDT 24
Finished Jun 10 05:57:04 PM PDT 24
Peak memory 254192 kb
Host smart-e3f4de18-9258-4769-9662-b5faf58ad978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805802147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.2805802147
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.2954530675
Short name T72
Test name
Test status
Simulation time 20318378 ps
CPU time 0.76 seconds
Started Jun 10 05:50:50 PM PDT 24
Finished Jun 10 05:50:51 PM PDT 24
Peak memory 216388 kb
Host smart-684781a4-cd37-46fa-b869-7d94a606e677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954530675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.2954530675
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.275057072
Short name T40
Test name
Test status
Simulation time 171275834920 ps
CPU time 249.36 seconds
Started Jun 10 05:52:52 PM PDT 24
Finished Jun 10 05:57:02 PM PDT 24
Peak memory 271392 kb
Host smart-ddb6362a-3fb1-4f2f-8616-e5f6e5506af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275057072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle
.275057072
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.2742809094
Short name T37
Test name
Test status
Simulation time 43307671539 ps
CPU time 268.75 seconds
Started Jun 10 05:52:32 PM PDT 24
Finished Jun 10 05:57:02 PM PDT 24
Peak memory 260880 kb
Host smart-a2284aca-34e3-4660-879b-83eb7eff75a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2742809094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.2742809094
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.4023298665
Short name T229
Test name
Test status
Simulation time 52303285667 ps
CPU time 631.93 seconds
Started Jun 10 05:51:17 PM PDT 24
Finished Jun 10 06:01:50 PM PDT 24
Peak memory 287300 kb
Host smart-68c4aabf-fd5f-4bd0-b9a6-e3e3da063773
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023298665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.4023298665
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.3378546053
Short name T98
Test name
Test status
Simulation time 529086489 ps
CPU time 3.86 seconds
Started Jun 10 05:46:03 PM PDT 24
Finished Jun 10 05:46:07 PM PDT 24
Peak memory 215136 kb
Host smart-27d2ef28-cfd9-4c3a-a144-b63b088340f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3378546053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.3
378546053
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.1982521750
Short name T21
Test name
Test status
Simulation time 46879155084 ps
CPU time 249.9 seconds
Started Jun 10 05:52:52 PM PDT 24
Finished Jun 10 05:57:03 PM PDT 24
Peak memory 256156 kb
Host smart-99007a78-ad7b-48c9-9d21-63a06eba905a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982521750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.1982521750
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.2982771386
Short name T142
Test name
Test status
Simulation time 1362615417 ps
CPU time 9.31 seconds
Started Jun 10 05:51:52 PM PDT 24
Finished Jun 10 05:52:02 PM PDT 24
Peak memory 233004 kb
Host smart-a3556b47-a097-4a68-bca6-bf7627b61a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982771386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.2982771386
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.3695471023
Short name T68
Test name
Test status
Simulation time 14740333 ps
CPU time 0.74 seconds
Started Jun 10 05:51:35 PM PDT 24
Finished Jun 10 05:51:36 PM PDT 24
Peak memory 205200 kb
Host smart-93553961-7267-435d-9d08-2f67181a9909
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695471023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
3695471023
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.3572624927
Short name T34
Test name
Test status
Simulation time 545017574658 ps
CPU time 572.62 seconds
Started Jun 10 05:51:09 PM PDT 24
Finished Jun 10 06:00:42 PM PDT 24
Peak memory 251900 kb
Host smart-50b471d5-81ce-41cd-9fc5-045c2072d71e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572624927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.3572624927
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.2706057006
Short name T168
Test name
Test status
Simulation time 15975419156 ps
CPU time 103.43 seconds
Started Jun 10 05:52:43 PM PDT 24
Finished Jun 10 05:54:27 PM PDT 24
Peak memory 264472 kb
Host smart-c95851c5-ba79-4ce0-8613-53786c47634f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706057006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.2706057006
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.274767157
Short name T20
Test name
Test status
Simulation time 167310265751 ps
CPU time 422.53 seconds
Started Jun 10 05:51:51 PM PDT 24
Finished Jun 10 05:58:55 PM PDT 24
Peak memory 250624 kb
Host smart-b80dd39c-ad67-4385-ba74-dce89f6f8e6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274767157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stres
s_all.274767157
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.3846811108
Short name T115
Test name
Test status
Simulation time 113398664 ps
CPU time 8.27 seconds
Started Jun 10 05:45:49 PM PDT 24
Finished Jun 10 05:45:58 PM PDT 24
Peak memory 206884 kb
Host smart-37884a32-7fe2-4342-ab16-abf7148db2d5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846811108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.3846811108
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.2675845064
Short name T173
Test name
Test status
Simulation time 541066725824 ps
CPU time 304.32 seconds
Started Jun 10 05:52:19 PM PDT 24
Finished Jun 10 05:57:24 PM PDT 24
Peak memory 265164 kb
Host smart-0ea8fdec-eebe-48df-8d43-18e7865879da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675845064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.2675845064
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1038112553
Short name T251
Test name
Test status
Simulation time 300566760 ps
CPU time 18.71 seconds
Started Jun 10 05:45:48 PM PDT 24
Finished Jun 10 05:46:07 PM PDT 24
Peak memory 215244 kb
Host smart-bcbd1e04-e06b-4c4e-b98d-7f4c2a471373
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038112553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1038112553
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.2957641977
Short name T85
Test name
Test status
Simulation time 9512913608 ps
CPU time 138.3 seconds
Started Jun 10 05:51:02 PM PDT 24
Finished Jun 10 05:53:21 PM PDT 24
Peak memory 256704 kb
Host smart-0f0ac0ea-1a37-47bd-bb7d-c3bc7da21b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957641977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.2957641977
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.3268423275
Short name T286
Test name
Test status
Simulation time 25081033234 ps
CPU time 62.66 seconds
Started Jun 10 05:52:52 PM PDT 24
Finished Jun 10 05:53:55 PM PDT 24
Peak memory 248960 kb
Host smart-f8a88887-4468-4957-a12a-37309bbf3af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268423275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.3268423275
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.3572234994
Short name T30
Test name
Test status
Simulation time 100212501891 ps
CPU time 252.39 seconds
Started Jun 10 05:53:09 PM PDT 24
Finished Jun 10 05:57:21 PM PDT 24
Peak memory 241356 kb
Host smart-9ba6df29-1c70-4a67-a3b7-efc6b4b6a10b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3572234994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.3572234994
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.2249260199
Short name T73
Test name
Test status
Simulation time 60942009 ps
CPU time 1.12 seconds
Started Jun 10 05:50:49 PM PDT 24
Finished Jun 10 05:50:51 PM PDT 24
Peak memory 236096 kb
Host smart-51c7ee0a-e741-4468-9f3e-78ef99b3efd0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249260199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.2249260199
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.3550352212
Short name T178
Test name
Test status
Simulation time 22816343214 ps
CPU time 253.47 seconds
Started Jun 10 05:51:11 PM PDT 24
Finished Jun 10 05:55:25 PM PDT 24
Peak memory 269680 kb
Host smart-8d97c50f-f182-4603-8e74-24c22ca45624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550352212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.3550352212
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.664190696
Short name T237
Test name
Test status
Simulation time 69202958048 ps
CPU time 290.6 seconds
Started Jun 10 05:51:03 PM PDT 24
Finished Jun 10 05:55:54 PM PDT 24
Peak memory 254684 kb
Host smart-3824b4e4-5afd-486d-ac4f-0c0fb1a53613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664190696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.
664190696
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.2720648813
Short name T174
Test name
Test status
Simulation time 8925701714 ps
CPU time 58.31 seconds
Started Jun 10 05:51:39 PM PDT 24
Finished Jun 10 05:52:38 PM PDT 24
Peak memory 254580 kb
Host smart-5019a2a9-18ba-4118-aac5-e7146c48c73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720648813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.2720648813
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.3620062350
Short name T132
Test name
Test status
Simulation time 9525869918 ps
CPU time 121.47 seconds
Started Jun 10 05:51:22 PM PDT 24
Finished Jun 10 05:53:24 PM PDT 24
Peak memory 252636 kb
Host smart-62051dd8-e48f-45c4-9e8c-32ed09d74587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620062350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.3620062350
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.1981380509
Short name T6
Test name
Test status
Simulation time 3002786569 ps
CPU time 9.31 seconds
Started Jun 10 05:52:38 PM PDT 24
Finished Jun 10 05:52:47 PM PDT 24
Peak memory 217016 kb
Host smart-db6ee325-882a-41a0-8d2d-77858801ccc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981380509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.1981380509
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.3283560858
Short name T191
Test name
Test status
Simulation time 34994386142 ps
CPU time 228.72 seconds
Started Jun 10 05:51:41 PM PDT 24
Finished Jun 10 05:55:30 PM PDT 24
Peak memory 252484 kb
Host smart-7d82358c-3893-4319-a0e1-f0673aca3a86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283560858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.3283560858
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.2474654879
Short name T183
Test name
Test status
Simulation time 505817770718 ps
CPU time 463.76 seconds
Started Jun 10 05:52:52 PM PDT 24
Finished Jun 10 06:00:36 PM PDT 24
Peak memory 266044 kb
Host smart-15e0da48-b40e-4089-a8bd-d57eeecde675
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474654879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.2474654879
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.663347841
Short name T249
Test name
Test status
Simulation time 1228572456 ps
CPU time 20.9 seconds
Started Jun 10 05:46:03 PM PDT 24
Finished Jun 10 05:46:24 PM PDT 24
Peak memory 215060 kb
Host smart-bb8ed67e-a850-4c83-99b6-07f6b4f7e3db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663347841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_
tl_intg_err.663347841
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.3551691912
Short name T503
Test name
Test status
Simulation time 4680227920 ps
CPU time 19.56 seconds
Started Jun 10 05:50:52 PM PDT 24
Finished Jun 10 05:51:11 PM PDT 24
Peak memory 216756 kb
Host smart-73d54861-6564-4951-9b34-9675f6c4d694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551691912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3551691912
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.3178230650
Short name T283
Test name
Test status
Simulation time 32026487815 ps
CPU time 128.36 seconds
Started Jun 10 05:53:12 PM PDT 24
Finished Jun 10 05:55:21 PM PDT 24
Peak memory 251328 kb
Host smart-24e44b63-54eb-4f84-b9c2-5f820fe70185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178230650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.3178230650
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.1150283488
Short name T247
Test name
Test status
Simulation time 1617778201 ps
CPU time 4.76 seconds
Started Jun 10 05:45:49 PM PDT 24
Finished Jun 10 05:45:54 PM PDT 24
Peak memory 215296 kb
Host smart-13f3c30a-d956-47d1-b615-da850c895f07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150283488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.1
150283488
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/default/7.spi_device_intercept.1127214520
Short name T253
Test name
Test status
Simulation time 1469692499 ps
CPU time 16.57 seconds
Started Jun 10 05:51:13 PM PDT 24
Finished Jun 10 05:51:30 PM PDT 24
Peak memory 233028 kb
Host smart-a7b51145-81fa-485a-a99f-42f228ccdb96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127214520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1127214520
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.733457126
Short name T332
Test name
Test status
Simulation time 3792400368 ps
CPU time 8.67 seconds
Started Jun 10 05:50:49 PM PDT 24
Finished Jun 10 05:50:58 PM PDT 24
Peak memory 216752 kb
Host smart-42f22db1-64b2-48b5-aca0-5aaee2c28044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733457126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.733457126
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.182632877
Short name T226
Test name
Test status
Simulation time 12873268873 ps
CPU time 73.82 seconds
Started Jun 10 05:51:35 PM PDT 24
Finished Jun 10 05:52:49 PM PDT 24
Peak memory 250608 kb
Host smart-14b6f518-6393-42a3-81e5-9f22c2985996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182632877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.182632877
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.631267814
Short name T129
Test name
Test status
Simulation time 4387507978 ps
CPU time 90.88 seconds
Started Jun 10 05:51:32 PM PDT 24
Finished Jun 10 05:53:04 PM PDT 24
Peak memory 255704 kb
Host smart-73e13555-fda5-4e7e-a6b2-db46c82bc73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631267814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.631267814
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.2121578495
Short name T242
Test name
Test status
Simulation time 2254430547 ps
CPU time 44.94 seconds
Started Jun 10 05:51:33 PM PDT 24
Finished Jun 10 05:52:19 PM PDT 24
Peak memory 257184 kb
Host smart-b6800a92-05a7-41af-98ee-8eb1dfdca7e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121578495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.2121578495
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.1622497432
Short name T313
Test name
Test status
Simulation time 292683949 ps
CPU time 8.69 seconds
Started Jun 10 05:51:01 PM PDT 24
Finished Jun 10 05:51:10 PM PDT 24
Peak memory 232992 kb
Host smart-b4cc6b92-b6c0-4902-ae1c-22a96b1417aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622497432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.1622497432
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.1637631705
Short name T227
Test name
Test status
Simulation time 3108526861 ps
CPU time 66.11 seconds
Started Jun 10 05:52:32 PM PDT 24
Finished Jun 10 05:53:39 PM PDT 24
Peak memory 255844 kb
Host smart-b04410b9-54f7-46b5-b4cc-df5bbd9a34ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637631705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.1637631705
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.4014985885
Short name T218
Test name
Test status
Simulation time 16988564282 ps
CPU time 181.67 seconds
Started Jun 10 05:53:26 PM PDT 24
Finished Jun 10 05:56:28 PM PDT 24
Peak memory 254356 kb
Host smart-5ba7964b-2dcc-4a61-bb5c-9e20e5b3a3c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014985885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.4014985885
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.2960927511
Short name T3
Test name
Test status
Simulation time 276048177 ps
CPU time 2.85 seconds
Started Jun 10 05:51:38 PM PDT 24
Finished Jun 10 05:51:42 PM PDT 24
Peak memory 224808 kb
Host smart-9ab0b0f7-cda0-4ac5-99ba-d4f1bffb10e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960927511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.2960927511
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.2913650913
Short name T241
Test name
Test status
Simulation time 165455394772 ps
CPU time 219.71 seconds
Started Jun 10 05:51:27 PM PDT 24
Finished Jun 10 05:55:07 PM PDT 24
Peak memory 256192 kb
Host smart-ccb46690-016c-482a-8ad0-a62eafa073cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913650913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.2913650913
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.2097643573
Short name T319
Test name
Test status
Simulation time 2077879198 ps
CPU time 27.09 seconds
Started Jun 10 05:51:33 PM PDT 24
Finished Jun 10 05:52:01 PM PDT 24
Peak memory 216920 kb
Host smart-7e45c337-b2d7-40c3-b376-4451e1bc55c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2097643573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.2097643573
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.304673741
Short name T381
Test name
Test status
Simulation time 2515371515 ps
CPU time 14.41 seconds
Started Jun 10 05:51:32 PM PDT 24
Finished Jun 10 05:51:47 PM PDT 24
Peak memory 217904 kb
Host smart-a514ba68-56bf-4075-9ee5-69e7c69100cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304673741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.304673741
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.3104346846
Short name T238
Test name
Test status
Simulation time 146312777598 ps
CPU time 395.42 seconds
Started Jun 10 05:51:47 PM PDT 24
Finished Jun 10 05:58:23 PM PDT 24
Peak memory 265976 kb
Host smart-cda96a47-bac2-4d9c-8126-81408ebf4988
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3104346846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.3104346846
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.1619917077
Short name T42
Test name
Test status
Simulation time 2975308145 ps
CPU time 6.42 seconds
Started Jun 10 05:51:59 PM PDT 24
Finished Jun 10 05:52:06 PM PDT 24
Peak memory 224844 kb
Host smart-ef486ffa-2441-4e2b-9295-6cccce458cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619917077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.1619917077
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.3397319807
Short name T228
Test name
Test status
Simulation time 2980344995 ps
CPU time 55.36 seconds
Started Jun 10 05:52:06 PM PDT 24
Finished Jun 10 05:53:02 PM PDT 24
Peak memory 234592 kb
Host smart-5263796e-0f59-453d-ae90-8073e0dc597b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397319807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.3397319807
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.1967654451
Short name T638
Test name
Test status
Simulation time 163004012 ps
CPU time 2.48 seconds
Started Jun 10 05:51:59 PM PDT 24
Finished Jun 10 05:52:02 PM PDT 24
Peak memory 224696 kb
Host smart-d3ed78d8-72f9-4a2c-9c57-4de1f44034b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967654451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.1967654451
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.2837985516
Short name T225
Test name
Test status
Simulation time 277708611 ps
CPU time 5.7 seconds
Started Jun 10 05:52:22 PM PDT 24
Finished Jun 10 05:52:28 PM PDT 24
Peak memory 238544 kb
Host smart-86aa0e9e-7a2c-4ce1-a37f-e863256e282f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837985516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.2837985516
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.588200235
Short name T308
Test name
Test status
Simulation time 4029716318 ps
CPU time 22.36 seconds
Started Jun 10 05:53:09 PM PDT 24
Finished Jun 10 05:53:32 PM PDT 24
Peak memory 241324 kb
Host smart-21cf6021-20f0-4250-b47a-fc9351989ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588200235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.588200235
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.170381884
Short name T234
Test name
Test status
Simulation time 813236521 ps
CPU time 7.86 seconds
Started Jun 10 05:53:24 PM PDT 24
Finished Jun 10 05:53:32 PM PDT 24
Peak memory 241016 kb
Host smart-c27295c3-195a-414b-bc27-e48578d750c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170381884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap
.170381884
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.3112411131
Short name T64
Test name
Test status
Simulation time 203386626 ps
CPU time 3.71 seconds
Started Jun 10 05:51:47 PM PDT 24
Finished Jun 10 05:51:51 PM PDT 24
Peak memory 232920 kb
Host smart-c3d8f93f-26cb-4756-b043-6a36d7b8a1cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112411131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.3112411131
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2396364034
Short name T106
Test name
Test status
Simulation time 2224047281 ps
CPU time 5.96 seconds
Started Jun 10 05:45:38 PM PDT 24
Finished Jun 10 05:45:45 PM PDT 24
Peak memory 215364 kb
Host smart-a94057bf-488f-4f8b-90b2-3e53c2a330f4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396364034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2
396364034
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1197666378
Short name T89
Test name
Test status
Simulation time 31374224 ps
CPU time 1.22 seconds
Started Jun 10 05:45:44 PM PDT 24
Finished Jun 10 05:45:46 PM PDT 24
Peak memory 206844 kb
Host smart-6f245519-9f7a-4569-af7b-91fbeca25a12
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197666378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.1197666378
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1372712286
Short name T94
Test name
Test status
Simulation time 3032941325 ps
CPU time 16.47 seconds
Started Jun 10 05:46:01 PM PDT 24
Finished Jun 10 05:46:19 PM PDT 24
Peak memory 215280 kb
Host smart-79643dd1-b46f-4ee4-a714-43928268100a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372712286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1372712286
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1366944644
Short name T1050
Test name
Test status
Simulation time 315335795 ps
CPU time 9.31 seconds
Started Jun 10 05:45:44 PM PDT 24
Finished Jun 10 05:45:54 PM PDT 24
Peak memory 215032 kb
Host smart-53024717-c05f-4a53-8bf1-9fe483436444
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366944644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.1366944644
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.765351
Short name T1024
Test name
Test status
Simulation time 4348438306 ps
CPU time 14.6 seconds
Started Jun 10 05:45:44 PM PDT 24
Finished Jun 10 05:45:59 PM PDT 24
Peak memory 206952 kb
Host smart-85618c44-5830-44c1-a3d0-fd6d8f5e3f60
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_bi
t_bash.765351
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3236078985
Short name T70
Test name
Test status
Simulation time 75142436 ps
CPU time 2.83 seconds
Started Jun 10 05:45:48 PM PDT 24
Finished Jun 10 05:45:51 PM PDT 24
Peak memory 216500 kb
Host smart-313fe124-1db6-42c6-a3c1-24067e975922
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236078985 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.3236078985
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.100431917
Short name T1064
Test name
Test status
Simulation time 188641339 ps
CPU time 2.54 seconds
Started Jun 10 05:45:39 PM PDT 24
Finished Jun 10 05:45:42 PM PDT 24
Peak memory 214984 kb
Host smart-9b696d72-e74a-426c-b3c6-596df177c5a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100431917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.100431917
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1798650068
Short name T1068
Test name
Test status
Simulation time 25214763 ps
CPU time 0.7 seconds
Started Jun 10 05:45:44 PM PDT 24
Finished Jun 10 05:45:45 PM PDT 24
Peak memory 203564 kb
Host smart-c6d85364-18ee-4abe-aa9f-cd5ead5c1f4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798650068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.1
798650068
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.678152861
Short name T111
Test name
Test status
Simulation time 24944264 ps
CPU time 1.63 seconds
Started Jun 10 05:45:42 PM PDT 24
Finished Jun 10 05:45:44 PM PDT 24
Peak memory 215144 kb
Host smart-2fe5f666-9d13-4495-9c94-ef10ce47449c
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678152861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_
device_mem_partial_access.678152861
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.657099913
Short name T1044
Test name
Test status
Simulation time 10714954 ps
CPU time 0.66 seconds
Started Jun 10 05:45:40 PM PDT 24
Finished Jun 10 05:45:41 PM PDT 24
Peak memory 203480 kb
Host smart-e3544b4f-06b3-4894-ac1d-a9aa4ccc2679
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657099913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem
_walk.657099913
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.141774797
Short name T985
Test name
Test status
Simulation time 68190686 ps
CPU time 1.92 seconds
Started Jun 10 05:45:46 PM PDT 24
Finished Jun 10 05:45:48 PM PDT 24
Peak memory 215124 kb
Host smart-5468355d-e738-4049-8290-c93c02c332fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141774797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sp
i_device_same_csr_outstanding.141774797
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3466889654
Short name T1060
Test name
Test status
Simulation time 208464773 ps
CPU time 13.93 seconds
Started Jun 10 05:45:38 PM PDT 24
Finished Jun 10 05:45:53 PM PDT 24
Peak memory 215184 kb
Host smart-d4c96d0f-c102-4bdc-a3e8-89a5e07363d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466889654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3466889654
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2214591924
Short name T1027
Test name
Test status
Simulation time 24610986047 ps
CPU time 39.07 seconds
Started Jun 10 05:45:48 PM PDT 24
Finished Jun 10 05:46:27 PM PDT 24
Peak memory 206964 kb
Host smart-4a25fc56-a626-4c4d-a1db-f676f59a5afe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214591924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.2214591924
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2284082556
Short name T87
Test name
Test status
Simulation time 303529997 ps
CPU time 1.36 seconds
Started Jun 10 05:45:49 PM PDT 24
Finished Jun 10 05:45:50 PM PDT 24
Peak memory 207016 kb
Host smart-3e591587-df59-443e-93a8-358a3736a8b2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284082556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.2284082556
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1238484834
Short name T1066
Test name
Test status
Simulation time 224168291 ps
CPU time 2.87 seconds
Started Jun 10 05:45:48 PM PDT 24
Finished Jun 10 05:45:51 PM PDT 24
Peak memory 216544 kb
Host smart-43a6edc9-6d7a-4dfe-87d9-10b16a70f806
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238484834 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.1238484834
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1354257990
Short name T1002
Test name
Test status
Simulation time 76446350 ps
CPU time 1.22 seconds
Started Jun 10 05:45:47 PM PDT 24
Finished Jun 10 05:45:48 PM PDT 24
Peak memory 215184 kb
Host smart-b1222edd-f464-4a8e-860a-bad623d4332d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354257990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1
354257990
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2420464176
Short name T1010
Test name
Test status
Simulation time 18145853 ps
CPU time 0.73 seconds
Started Jun 10 05:45:44 PM PDT 24
Finished Jun 10 05:45:45 PM PDT 24
Peak memory 203560 kb
Host smart-1ddf2088-41cd-42c1-9411-141681f2e71b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420464176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.2
420464176
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.93291608
Short name T1045
Test name
Test status
Simulation time 91835255 ps
CPU time 1.43 seconds
Started Jun 10 05:45:48 PM PDT 24
Finished Jun 10 05:45:50 PM PDT 24
Peak memory 215188 kb
Host smart-ea5d996b-94ba-4ee3-8b3e-b428d3ae45a9
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93291608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi
_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_d
evice_mem_partial_access.93291608
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.118788374
Short name T1019
Test name
Test status
Simulation time 28057595 ps
CPU time 0.69 seconds
Started Jun 10 05:45:47 PM PDT 24
Finished Jun 10 05:45:49 PM PDT 24
Peak memory 203788 kb
Host smart-210487b4-8f0b-450c-bc44-7a3a056a68df
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118788374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem
_walk.118788374
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2500672970
Short name T134
Test name
Test status
Simulation time 103382246 ps
CPU time 2.71 seconds
Started Jun 10 05:45:48 PM PDT 24
Finished Jun 10 05:45:51 PM PDT 24
Peak memory 215240 kb
Host smart-3d5454ae-110b-4473-b67d-d54f248833b9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500672970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2500672970
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.1634116595
Short name T95
Test name
Test status
Simulation time 456197950 ps
CPU time 6.94 seconds
Started Jun 10 05:45:46 PM PDT 24
Finished Jun 10 05:45:53 PM PDT 24
Peak memory 215960 kb
Host smart-acdadb4b-03ce-4501-bd76-5e141f7e1960
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634116595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.1634116595
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1399620418
Short name T994
Test name
Test status
Simulation time 86871060 ps
CPU time 2.69 seconds
Started Jun 10 05:46:06 PM PDT 24
Finished Jun 10 05:46:09 PM PDT 24
Peak memory 217660 kb
Host smart-fa74f923-22f2-443a-a0dd-2f9680e8a4b4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399620418 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.1399620418
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3606140912
Short name T123
Test name
Test status
Simulation time 341990905 ps
CPU time 2.14 seconds
Started Jun 10 05:46:07 PM PDT 24
Finished Jun 10 05:46:09 PM PDT 24
Peak memory 206840 kb
Host smart-5d48e4ce-a420-45cf-b045-6d6d5e6f0e55
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606140912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
3606140912
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1502936884
Short name T990
Test name
Test status
Simulation time 15774136 ps
CPU time 0.79 seconds
Started Jun 10 05:46:03 PM PDT 24
Finished Jun 10 05:46:04 PM PDT 24
Peak memory 203468 kb
Host smart-2336cd12-d09f-4e7f-b5eb-6c09213d21bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502936884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
1502936884
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.3569665427
Short name T1048
Test name
Test status
Simulation time 62496601 ps
CPU time 3.79 seconds
Started Jun 10 05:46:10 PM PDT 24
Finished Jun 10 05:46:14 PM PDT 24
Peak memory 215184 kb
Host smart-717fd2c0-ece1-4999-b5ae-420d7b6003f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569665427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.3569665427
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.2660430198
Short name T103
Test name
Test status
Simulation time 234846389 ps
CPU time 3.3 seconds
Started Jun 10 05:46:04 PM PDT 24
Finished Jun 10 05:46:08 PM PDT 24
Peak memory 215452 kb
Host smart-e704cc64-7b1e-48be-bd77-0bf94c5618c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660430198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
2660430198
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2163447932
Short name T1043
Test name
Test status
Simulation time 89878415 ps
CPU time 1.56 seconds
Started Jun 10 05:46:07 PM PDT 24
Finished Jun 10 05:46:09 PM PDT 24
Peak memory 215444 kb
Host smart-397116ae-9a2e-437e-aeac-3e9768c4d7ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163447932 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.2163447932
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2370491240
Short name T117
Test name
Test status
Simulation time 494803776 ps
CPU time 2.73 seconds
Started Jun 10 05:46:08 PM PDT 24
Finished Jun 10 05:46:11 PM PDT 24
Peak memory 215180 kb
Host smart-80930f0e-3865-4f28-8b51-14f1b8381fd1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370491240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
2370491240
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.3352084758
Short name T1004
Test name
Test status
Simulation time 73609245 ps
CPU time 0.72 seconds
Started Jun 10 05:46:07 PM PDT 24
Finished Jun 10 05:46:08 PM PDT 24
Peak memory 203576 kb
Host smart-3dbf51a2-6a6b-4997-b8b5-07df9ac74d84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352084758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
3352084758
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.727845618
Short name T1035
Test name
Test status
Simulation time 631596890 ps
CPU time 4.76 seconds
Started Jun 10 05:46:07 PM PDT 24
Finished Jun 10 05:46:12 PM PDT 24
Peak memory 215220 kb
Host smart-b2ecd9c0-5a26-4991-9d1d-1dcdf4440953
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727845618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.s
pi_device_same_csr_outstanding.727845618
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3874718508
Short name T1077
Test name
Test status
Simulation time 177520748 ps
CPU time 4.46 seconds
Started Jun 10 05:46:05 PM PDT 24
Finished Jun 10 05:46:10 PM PDT 24
Peak memory 215308 kb
Host smart-7c1735fe-7e4c-423a-b0af-7a8c77afcbd0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874718508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3874718508
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.4018754496
Short name T1040
Test name
Test status
Simulation time 201452442 ps
CPU time 11.88 seconds
Started Jun 10 05:46:08 PM PDT 24
Finished Jun 10 05:46:20 PM PDT 24
Peak memory 215308 kb
Host smart-ff8d5a25-ab4f-40fe-b668-89609374a0a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018754496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.4018754496
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2228842865
Short name T1055
Test name
Test status
Simulation time 148836427 ps
CPU time 3.9 seconds
Started Jun 10 05:46:11 PM PDT 24
Finished Jun 10 05:46:15 PM PDT 24
Peak memory 217760 kb
Host smart-a52fcbf0-dfe4-41ce-b714-1777a3c16851
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228842865 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.2228842865
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.2718990279
Short name T112
Test name
Test status
Simulation time 310865683 ps
CPU time 1.96 seconds
Started Jun 10 05:46:08 PM PDT 24
Finished Jun 10 05:46:10 PM PDT 24
Peak memory 215072 kb
Host smart-1373e36e-9d6e-4a23-9824-188c407e02a1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718990279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
2718990279
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3914624735
Short name T1042
Test name
Test status
Simulation time 21991296 ps
CPU time 0.83 seconds
Started Jun 10 05:46:08 PM PDT 24
Finished Jun 10 05:46:09 PM PDT 24
Peak memory 203560 kb
Host smart-b4cb59c9-0086-4c88-b938-772287d9ccbc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914624735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
3914624735
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3081537112
Short name T1017
Test name
Test status
Simulation time 692276958 ps
CPU time 3.95 seconds
Started Jun 10 05:46:06 PM PDT 24
Finished Jun 10 05:46:11 PM PDT 24
Peak memory 215256 kb
Host smart-63bbea9b-5d05-48bf-99dd-93605cba290a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081537112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.3081537112
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.3261227233
Short name T96
Test name
Test status
Simulation time 162282823 ps
CPU time 3.18 seconds
Started Jun 10 05:46:08 PM PDT 24
Finished Jun 10 05:46:11 PM PDT 24
Peak memory 215300 kb
Host smart-9d8b7768-835f-4719-b1eb-814d5070f1f6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261227233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
3261227233
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.697658709
Short name T248
Test name
Test status
Simulation time 119539330 ps
CPU time 6.98 seconds
Started Jun 10 05:46:07 PM PDT 24
Finished Jun 10 05:46:15 PM PDT 24
Peak memory 215044 kb
Host smart-51c30476-78df-4c19-ae61-f13bfd07411c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697658709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device
_tl_intg_err.697658709
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3217793421
Short name T1021
Test name
Test status
Simulation time 54229460 ps
CPU time 3.94 seconds
Started Jun 10 05:46:16 PM PDT 24
Finished Jun 10 05:46:20 PM PDT 24
Peak memory 217340 kb
Host smart-2cd97d6f-7d94-4188-9c99-7aa830c4296a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217793421 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.3217793421
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2080983150
Short name T138
Test name
Test status
Simulation time 82187393 ps
CPU time 2.34 seconds
Started Jun 10 05:46:10 PM PDT 24
Finished Jun 10 05:46:13 PM PDT 24
Peak memory 215228 kb
Host smart-de0f1d3c-5d1f-492b-a9de-c84d7c5c9188
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080983150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
2080983150
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3169565317
Short name T1026
Test name
Test status
Simulation time 35447991 ps
CPU time 0.72 seconds
Started Jun 10 05:46:11 PM PDT 24
Finished Jun 10 05:46:12 PM PDT 24
Peak memory 203556 kb
Host smart-d6644069-8808-4144-bd33-b3f64abb5a0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169565317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3169565317
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.959824836
Short name T975
Test name
Test status
Simulation time 304002210 ps
CPU time 2.86 seconds
Started Jun 10 05:46:08 PM PDT 24
Finished Jun 10 05:46:11 PM PDT 24
Peak memory 215264 kb
Host smart-cfb74c3b-0501-4a1c-b896-ca3eeaec2d96
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959824836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.959824836
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.80110652
Short name T1028
Test name
Test status
Simulation time 125171852 ps
CPU time 3.21 seconds
Started Jun 10 05:46:11 PM PDT 24
Finished Jun 10 05:46:15 PM PDT 24
Peak memory 215316 kb
Host smart-6388ef79-9a8a-4ab0-98bc-fa87369f2cc5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80110652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.80110652
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3986218342
Short name T1053
Test name
Test status
Simulation time 905252872 ps
CPU time 7.26 seconds
Started Jun 10 05:46:14 PM PDT 24
Finished Jun 10 05:46:22 PM PDT 24
Peak memory 215468 kb
Host smart-be9f06f3-da43-43a2-ae09-c781ac00dd39
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986218342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.3986218342
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3254533222
Short name T982
Test name
Test status
Simulation time 210048804 ps
CPU time 1.87 seconds
Started Jun 10 05:46:09 PM PDT 24
Finished Jun 10 05:46:11 PM PDT 24
Peak memory 215256 kb
Host smart-2bf04f22-4751-4a89-9f9c-fb19380dba69
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254533222 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.3254533222
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.774247449
Short name T110
Test name
Test status
Simulation time 38314761 ps
CPU time 2.62 seconds
Started Jun 10 05:46:14 PM PDT 24
Finished Jun 10 05:46:17 PM PDT 24
Peak memory 215104 kb
Host smart-6faae724-f0b0-46ec-bd7c-be6d3cc1cebe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774247449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.774247449
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.395474420
Short name T966
Test name
Test status
Simulation time 13916080 ps
CPU time 0.7 seconds
Started Jun 10 05:46:13 PM PDT 24
Finished Jun 10 05:46:14 PM PDT 24
Peak memory 203844 kb
Host smart-2d379826-9db2-4424-bf33-08329e280a8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395474420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.395474420
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2644566572
Short name T972
Test name
Test status
Simulation time 106911901 ps
CPU time 1.86 seconds
Started Jun 10 05:46:13 PM PDT 24
Finished Jun 10 05:46:15 PM PDT 24
Peak memory 215292 kb
Host smart-bfab9da2-63ae-4308-aee9-cd14499c8adb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644566572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.2644566572
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1496783261
Short name T1056
Test name
Test status
Simulation time 153785692 ps
CPU time 4.64 seconds
Started Jun 10 05:46:12 PM PDT 24
Finished Jun 10 05:46:17 PM PDT 24
Peak memory 215260 kb
Host smart-7f566312-74ee-4716-a6df-a9e80d4b75d6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496783261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
1496783261
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.2271833330
Short name T1078
Test name
Test status
Simulation time 739557844 ps
CPU time 8.54 seconds
Started Jun 10 05:46:16 PM PDT 24
Finished Jun 10 05:46:25 PM PDT 24
Peak memory 215520 kb
Host smart-6b222d99-ea37-4ee1-acd3-af5c2e01ef94
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271833330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.2271833330
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1582339125
Short name T109
Test name
Test status
Simulation time 131841475 ps
CPU time 1.87 seconds
Started Jun 10 05:46:17 PM PDT 24
Finished Jun 10 05:46:19 PM PDT 24
Peak memory 216192 kb
Host smart-33b04bee-4087-4c3f-a6a5-b715553d8c09
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582339125 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.1582339125
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.952946906
Short name T116
Test name
Test status
Simulation time 72234953 ps
CPU time 1.26 seconds
Started Jun 10 05:46:09 PM PDT 24
Finished Jun 10 05:46:11 PM PDT 24
Peak memory 206864 kb
Host smart-92fa1752-a38f-49eb-b2c5-7e986809e803
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952946906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.952946906
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1607920662
Short name T1000
Test name
Test status
Simulation time 53895936 ps
CPU time 0.74 seconds
Started Jun 10 05:46:12 PM PDT 24
Finished Jun 10 05:46:13 PM PDT 24
Peak memory 203776 kb
Host smart-be90e179-2484-47a7-bbe3-41e46b32ff2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607920662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
1607920662
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2164918807
Short name T136
Test name
Test status
Simulation time 48154082 ps
CPU time 2.84 seconds
Started Jun 10 05:46:11 PM PDT 24
Finished Jun 10 05:46:14 PM PDT 24
Peak memory 215252 kb
Host smart-e83fdd38-fe40-4658-b469-1ee8e2223f71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164918807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.2164918807
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.311630368
Short name T1006
Test name
Test status
Simulation time 86406019 ps
CPU time 2.62 seconds
Started Jun 10 05:46:09 PM PDT 24
Finished Jun 10 05:46:12 PM PDT 24
Peak memory 215328 kb
Host smart-7c78ba57-563c-4352-886b-ef0a0ffc4d2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311630368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.311630368
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.4262372702
Short name T1072
Test name
Test status
Simulation time 420365999 ps
CPU time 6.56 seconds
Started Jun 10 05:46:13 PM PDT 24
Finished Jun 10 05:46:20 PM PDT 24
Peak memory 215292 kb
Host smart-499dcee7-cfe6-4b36-9ae9-d93419bb2f4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262372702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.4262372702
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2092862611
Short name T1074
Test name
Test status
Simulation time 210191628 ps
CPU time 3.79 seconds
Started Jun 10 05:46:15 PM PDT 24
Finished Jun 10 05:46:20 PM PDT 24
Peak memory 217776 kb
Host smart-3f41a32e-1499-4a2e-8fd0-5a9e6be425df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092862611 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.2092862611
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.354379712
Short name T1065
Test name
Test status
Simulation time 61108575 ps
CPU time 1.93 seconds
Started Jun 10 05:46:17 PM PDT 24
Finished Jun 10 05:46:19 PM PDT 24
Peak memory 215100 kb
Host smart-6ffa3c84-7f0c-451a-9ee2-19625d2ece48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354379712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.354379712
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3027871544
Short name T970
Test name
Test status
Simulation time 23195496 ps
CPU time 0.71 seconds
Started Jun 10 05:46:20 PM PDT 24
Finished Jun 10 05:46:21 PM PDT 24
Peak memory 203584 kb
Host smart-750a5ab4-a5ac-4a7f-a669-d285636ef175
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027871544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3027871544
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1844085253
Short name T991
Test name
Test status
Simulation time 168187954 ps
CPU time 4.63 seconds
Started Jun 10 05:46:16 PM PDT 24
Finished Jun 10 05:46:21 PM PDT 24
Peak memory 215244 kb
Host smart-00ab17b0-32c0-41fd-95cb-bd4af01cb512
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844085253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.1844085253
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3652273531
Short name T1052
Test name
Test status
Simulation time 43212466 ps
CPU time 1.42 seconds
Started Jun 10 05:46:16 PM PDT 24
Finished Jun 10 05:46:18 PM PDT 24
Peak memory 216372 kb
Host smart-16322e46-2fc9-48ce-8b3c-c601bbc61eda
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652273531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
3652273531
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.783091916
Short name T977
Test name
Test status
Simulation time 1222724203 ps
CPU time 8.72 seconds
Started Jun 10 05:46:16 PM PDT 24
Finished Jun 10 05:46:25 PM PDT 24
Peak memory 215600 kb
Host smart-703e180e-7700-4b97-a35c-f1bc8d617d2c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783091916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device
_tl_intg_err.783091916
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2557971972
Short name T1015
Test name
Test status
Simulation time 133175474 ps
CPU time 3.65 seconds
Started Jun 10 05:46:17 PM PDT 24
Finished Jun 10 05:46:21 PM PDT 24
Peak memory 217384 kb
Host smart-06885a4a-622b-47ea-91c0-3ce14647f91f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557971972 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.2557971972
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1260575043
Short name T1063
Test name
Test status
Simulation time 397229974 ps
CPU time 1.58 seconds
Started Jun 10 05:46:19 PM PDT 24
Finished Jun 10 05:46:21 PM PDT 24
Peak memory 206852 kb
Host smart-9d9f8319-1b95-4aa6-889d-c58bcc645d72
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260575043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
1260575043
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3738402706
Short name T964
Test name
Test status
Simulation time 31543273 ps
CPU time 0.72 seconds
Started Jun 10 05:46:20 PM PDT 24
Finished Jun 10 05:46:21 PM PDT 24
Peak memory 203552 kb
Host smart-606e8793-b6a2-4fcf-96da-8d55949373cd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738402706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
3738402706
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2521075774
Short name T1030
Test name
Test status
Simulation time 155399156 ps
CPU time 2.98 seconds
Started Jun 10 05:46:14 PM PDT 24
Finished Jun 10 05:46:18 PM PDT 24
Peak memory 215144 kb
Host smart-8eca4665-feae-4400-9aca-b7729410e2fa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521075774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.2521075774
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.10925395
Short name T104
Test name
Test status
Simulation time 64134961 ps
CPU time 4.01 seconds
Started Jun 10 05:46:16 PM PDT 24
Finished Jun 10 05:46:21 PM PDT 24
Peak memory 215312 kb
Host smart-e45e12b3-4a19-43ee-b28a-be9934980abf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10925395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.10925395
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.2276202211
Short name T149
Test name
Test status
Simulation time 1038327555 ps
CPU time 23.54 seconds
Started Jun 10 05:46:15 PM PDT 24
Finished Jun 10 05:46:39 PM PDT 24
Peak memory 215140 kb
Host smart-4ac3199b-e5c9-4ffa-92b7-9de2750fed32
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276202211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.2276202211
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.4220810874
Short name T1031
Test name
Test status
Simulation time 199830617 ps
CPU time 1.84 seconds
Started Jun 10 05:46:15 PM PDT 24
Finished Jun 10 05:46:17 PM PDT 24
Peak memory 215256 kb
Host smart-77f77b08-8215-4356-b93a-703760fcb43e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220810874 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.4220810874
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2459530598
Short name T119
Test name
Test status
Simulation time 454444372 ps
CPU time 2.96 seconds
Started Jun 10 05:46:16 PM PDT 24
Finished Jun 10 05:46:19 PM PDT 24
Peak memory 215048 kb
Host smart-e17202b0-a564-4332-b21c-5bc91347e2c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459530598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
2459530598
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.4285642201
Short name T971
Test name
Test status
Simulation time 16427989 ps
CPU time 0.86 seconds
Started Jun 10 05:46:16 PM PDT 24
Finished Jun 10 05:46:17 PM PDT 24
Peak memory 203988 kb
Host smart-7a2c7660-6d6b-4c1a-b285-892ca5a7dd45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285642201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
4285642201
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.529560121
Short name T1023
Test name
Test status
Simulation time 688334500 ps
CPU time 2.17 seconds
Started Jun 10 05:46:16 PM PDT 24
Finished Jun 10 05:46:19 PM PDT 24
Peak memory 215276 kb
Host smart-6e0d72e1-3d71-4fa8-aa7f-5189d897b57d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529560121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.s
pi_device_same_csr_outstanding.529560121
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3535100262
Short name T1067
Test name
Test status
Simulation time 249593133 ps
CPU time 3.07 seconds
Started Jun 10 05:46:16 PM PDT 24
Finished Jun 10 05:46:19 PM PDT 24
Peak memory 215352 kb
Host smart-ba0c367a-02ac-4a89-9c56-a28940dee82a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535100262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
3535100262
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.2127132369
Short name T1079
Test name
Test status
Simulation time 3410380998 ps
CPU time 22.36 seconds
Started Jun 10 05:46:17 PM PDT 24
Finished Jun 10 05:46:40 PM PDT 24
Peak memory 215316 kb
Host smart-d3e83007-4579-4ea4-bba8-f653f72e095b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127132369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.2127132369
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3485841996
Short name T1012
Test name
Test status
Simulation time 57055862 ps
CPU time 3.58 seconds
Started Jun 10 05:46:32 PM PDT 24
Finished Jun 10 05:46:36 PM PDT 24
Peak memory 217944 kb
Host smart-b4fc2994-4cce-417e-bd23-d9fb601d66ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485841996 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.3485841996
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1481589908
Short name T113
Test name
Test status
Simulation time 20701317 ps
CPU time 1.2 seconds
Started Jun 10 05:46:22 PM PDT 24
Finished Jun 10 05:46:24 PM PDT 24
Peak memory 206852 kb
Host smart-d06f090f-272c-4585-b8a6-304c0c25c7ca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481589908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
1481589908
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2366464657
Short name T1070
Test name
Test status
Simulation time 20608297 ps
CPU time 0.72 seconds
Started Jun 10 05:46:19 PM PDT 24
Finished Jun 10 05:46:20 PM PDT 24
Peak memory 203528 kb
Host smart-5aaefe85-e549-492a-9693-e9724e3bb113
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366464657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2366464657
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2777212219
Short name T164
Test name
Test status
Simulation time 430367834 ps
CPU time 4.66 seconds
Started Jun 10 05:46:29 PM PDT 24
Finished Jun 10 05:46:34 PM PDT 24
Peak memory 215256 kb
Host smart-9972f2e2-7004-4615-87f2-76af2bd891a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777212219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.2777212219
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.340237611
Short name T102
Test name
Test status
Simulation time 460381467 ps
CPU time 2.99 seconds
Started Jun 10 05:46:11 PM PDT 24
Finished Jun 10 05:46:14 PM PDT 24
Peak memory 215356 kb
Host smart-199962cd-27aa-4ff1-8657-23bbef0f5800
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340237611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.340237611
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1970014799
Short name T147
Test name
Test status
Simulation time 667647094 ps
CPU time 17.94 seconds
Started Jun 10 05:46:19 PM PDT 24
Finished Jun 10 05:46:38 PM PDT 24
Peak memory 215320 kb
Host smart-898bf3a1-5fde-47c6-8ce5-e9e28698243f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970014799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.1970014799
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2615851953
Short name T122
Test name
Test status
Simulation time 6559419135 ps
CPU time 24.16 seconds
Started Jun 10 05:45:53 PM PDT 24
Finished Jun 10 05:46:17 PM PDT 24
Peak memory 215164 kb
Host smart-487be2dd-01fd-4c47-9917-26ae6ea21b3a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615851953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2615851953
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2349955824
Short name T986
Test name
Test status
Simulation time 2774879341 ps
CPU time 15.36 seconds
Started Jun 10 05:45:52 PM PDT 24
Finished Jun 10 05:46:08 PM PDT 24
Peak memory 215148 kb
Host smart-30223a3a-ce8a-47a3-8915-98ed496866e3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349955824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.2349955824
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2618669189
Short name T88
Test name
Test status
Simulation time 18514703 ps
CPU time 1.13 seconds
Started Jun 10 05:45:49 PM PDT 24
Finished Jun 10 05:45:50 PM PDT 24
Peak memory 216132 kb
Host smart-943b43a2-7d06-41cd-9b10-3958806206ca
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618669189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.2618669189
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2935586752
Short name T1020
Test name
Test status
Simulation time 25081023 ps
CPU time 1.71 seconds
Started Jun 10 05:45:50 PM PDT 24
Finished Jun 10 05:45:52 PM PDT 24
Peak memory 215256 kb
Host smart-f3fcae0c-bb15-4d97-83e5-3d1380216dab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935586752 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.2935586752
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3280993735
Short name T114
Test name
Test status
Simulation time 303647955 ps
CPU time 2.1 seconds
Started Jun 10 05:45:49 PM PDT 24
Finished Jun 10 05:45:51 PM PDT 24
Peak memory 215144 kb
Host smart-bec78cdc-210f-4c82-a3e9-11977dff1045
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280993735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.3
280993735
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1199221400
Short name T1003
Test name
Test status
Simulation time 19667658 ps
CPU time 0.8 seconds
Started Jun 10 05:45:49 PM PDT 24
Finished Jun 10 05:45:50 PM PDT 24
Peak memory 203444 kb
Host smart-9ab63d5e-a196-4574-b9d0-083c96285d41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199221400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1
199221400
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2358874448
Short name T1029
Test name
Test status
Simulation time 46392682 ps
CPU time 1.73 seconds
Started Jun 10 05:45:51 PM PDT 24
Finished Jun 10 05:45:53 PM PDT 24
Peak memory 215148 kb
Host smart-bd8e118a-cdd0-4ede-b53a-dfcea8fc9a77
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358874448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.2358874448
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.1491423195
Short name T1076
Test name
Test status
Simulation time 29446278 ps
CPU time 0.7 seconds
Started Jun 10 05:45:46 PM PDT 24
Finished Jun 10 05:45:47 PM PDT 24
Peak memory 203808 kb
Host smart-c0213783-5adf-47e3-bc27-d59c07ef0742
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491423195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.1491423195
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3078211645
Short name T1073
Test name
Test status
Simulation time 77006929 ps
CPU time 2.91 seconds
Started Jun 10 05:45:52 PM PDT 24
Finished Jun 10 05:45:55 PM PDT 24
Peak memory 207028 kb
Host smart-32fc8000-ae03-48fe-9277-ad58273c798f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078211645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.3078211645
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.172785779
Short name T1032
Test name
Test status
Simulation time 198637939 ps
CPU time 3.89 seconds
Started Jun 10 05:45:48 PM PDT 24
Finished Jun 10 05:45:52 PM PDT 24
Peak memory 215380 kb
Host smart-2eadce81-846e-431d-b896-e74b8296927e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172785779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.172785779
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3260367255
Short name T1080
Test name
Test status
Simulation time 11823263 ps
CPU time 0.73 seconds
Started Jun 10 05:46:30 PM PDT 24
Finished Jun 10 05:46:31 PM PDT 24
Peak memory 203628 kb
Host smart-8d27f373-48d1-4ade-b9f2-b07d99ddb1ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260367255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
3260367255
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3675660394
Short name T1058
Test name
Test status
Simulation time 39753421 ps
CPU time 0.7 seconds
Started Jun 10 05:46:31 PM PDT 24
Finished Jun 10 05:46:32 PM PDT 24
Peak memory 203516 kb
Host smart-4dfc3f66-5448-487c-b935-e10666df0f10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675660394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
3675660394
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3032845690
Short name T962
Test name
Test status
Simulation time 28411701 ps
CPU time 0.76 seconds
Started Jun 10 05:46:23 PM PDT 24
Finished Jun 10 05:46:24 PM PDT 24
Peak memory 203884 kb
Host smart-624b9def-3bb4-4735-8d1e-55fc6490f64a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032845690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3032845690
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1942027684
Short name T1049
Test name
Test status
Simulation time 89657373 ps
CPU time 0.73 seconds
Started Jun 10 05:46:29 PM PDT 24
Finished Jun 10 05:46:30 PM PDT 24
Peak memory 203612 kb
Host smart-688b0222-e7a3-4994-b116-ffd0f5199674
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942027684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
1942027684
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2347108471
Short name T960
Test name
Test status
Simulation time 38665982 ps
CPU time 0.71 seconds
Started Jun 10 05:46:19 PM PDT 24
Finished Jun 10 05:46:20 PM PDT 24
Peak memory 203544 kb
Host smart-e0489eb5-c590-4d56-84eb-0eba947e2b14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347108471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
2347108471
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1969065272
Short name T993
Test name
Test status
Simulation time 21764915 ps
CPU time 0.75 seconds
Started Jun 10 05:46:17 PM PDT 24
Finished Jun 10 05:46:18 PM PDT 24
Peak memory 203876 kb
Host smart-c060eb39-e0bd-4835-833f-b6fe7f529826
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969065272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
1969065272
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2000842519
Short name T978
Test name
Test status
Simulation time 37957323 ps
CPU time 0.76 seconds
Started Jun 10 05:46:20 PM PDT 24
Finished Jun 10 05:46:21 PM PDT 24
Peak memory 203684 kb
Host smart-72bff4b8-a538-4de2-83e2-aa0b8429a274
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000842519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2000842519
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3148945927
Short name T1014
Test name
Test status
Simulation time 21019197 ps
CPU time 0.72 seconds
Started Jun 10 05:46:33 PM PDT 24
Finished Jun 10 05:46:34 PM PDT 24
Peak memory 203800 kb
Host smart-530972fb-1445-4bce-b6c2-ff31136a7171
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148945927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
3148945927
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1658751535
Short name T989
Test name
Test status
Simulation time 81123074 ps
CPU time 0.77 seconds
Started Jun 10 05:46:29 PM PDT 24
Finished Jun 10 05:46:30 PM PDT 24
Peak memory 203880 kb
Host smart-665d61a2-f138-4164-80a4-8a8d0b79d539
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658751535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
1658751535
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1660566772
Short name T999
Test name
Test status
Simulation time 30427987 ps
CPU time 0.73 seconds
Started Jun 10 05:46:28 PM PDT 24
Finished Jun 10 05:46:29 PM PDT 24
Peak memory 203888 kb
Host smart-02b8ee02-50fb-42e1-88b7-5e05640a9d77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660566772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
1660566772
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1510320182
Short name T1047
Test name
Test status
Simulation time 3966039481 ps
CPU time 24.22 seconds
Started Jun 10 05:45:56 PM PDT 24
Finished Jun 10 05:46:20 PM PDT 24
Peak memory 215224 kb
Host smart-8df8a15f-7fc6-4b48-a1a1-c9ae2c31ffda
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510320182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.1510320182
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.4181281816
Short name T120
Test name
Test status
Simulation time 7537041331 ps
CPU time 36.01 seconds
Started Jun 10 05:45:55 PM PDT 24
Finished Jun 10 05:46:31 PM PDT 24
Peak memory 207004 kb
Host smart-89092e9b-e6ef-4ead-a0be-b8096214ac26
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181281816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.4181281816
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1882507160
Short name T1008
Test name
Test status
Simulation time 16139069 ps
CPU time 0.97 seconds
Started Jun 10 05:45:51 PM PDT 24
Finished Jun 10 05:45:53 PM PDT 24
Peak memory 206612 kb
Host smart-05dce1d0-7385-44ea-b2e6-c05ff3fcbeb1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882507160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.1882507160
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.457837358
Short name T1041
Test name
Test status
Simulation time 394514917 ps
CPU time 1.71 seconds
Started Jun 10 05:45:57 PM PDT 24
Finished Jun 10 05:45:59 PM PDT 24
Peak memory 215256 kb
Host smart-5f9c2206-c3cd-4c38-b911-44d41987ec2f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457837358 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.457837358
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1127682195
Short name T1001
Test name
Test status
Simulation time 62522597 ps
CPU time 2.08 seconds
Started Jun 10 05:45:55 PM PDT 24
Finished Jun 10 05:45:58 PM PDT 24
Peak memory 206848 kb
Host smart-6900111b-645a-4d19-81b3-3656424e3e30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127682195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1
127682195
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.399904193
Short name T998
Test name
Test status
Simulation time 13336638 ps
CPU time 0.73 seconds
Started Jun 10 05:45:53 PM PDT 24
Finished Jun 10 05:45:55 PM PDT 24
Peak memory 203868 kb
Host smart-707c9009-11c2-4a24-9aae-7c38621480f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399904193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.399904193
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2365458890
Short name T118
Test name
Test status
Simulation time 131876534 ps
CPU time 2.15 seconds
Started Jun 10 05:45:48 PM PDT 24
Finished Jun 10 05:45:50 PM PDT 24
Peak memory 215128 kb
Host smart-c48975a1-044c-47f1-9b1a-4f1d7e6102f8
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365458890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.2365458890
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3991768688
Short name T984
Test name
Test status
Simulation time 10714572 ps
CPU time 0.65 seconds
Started Jun 10 05:45:50 PM PDT 24
Finished Jun 10 05:45:51 PM PDT 24
Peak memory 203476 kb
Host smart-8547bfe8-1256-4dbd-95c0-1fc7184f52a4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991768688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.3991768688
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2108357930
Short name T151
Test name
Test status
Simulation time 602112844 ps
CPU time 3 seconds
Started Jun 10 05:45:55 PM PDT 24
Finished Jun 10 05:45:58 PM PDT 24
Peak memory 215772 kb
Host smart-13ee0390-e577-4a7b-88bd-40a679d2653f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108357930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.2108357930
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2016917972
Short name T105
Test name
Test status
Simulation time 550809909 ps
CPU time 3.67 seconds
Started Jun 10 05:45:50 PM PDT 24
Finished Jun 10 05:45:54 PM PDT 24
Peak memory 215308 kb
Host smart-b28aef48-1da9-48ae-89dd-17cf67464f13
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016917972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2
016917972
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1775777882
Short name T1081
Test name
Test status
Simulation time 306216099 ps
CPU time 18.78 seconds
Started Jun 10 05:45:51 PM PDT 24
Finished Jun 10 05:46:10 PM PDT 24
Peak memory 215176 kb
Host smart-027ac2c5-1b90-4fab-9ca2-804dc197e971
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775777882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.1775777882
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3234448850
Short name T996
Test name
Test status
Simulation time 16569458 ps
CPU time 0.76 seconds
Started Jun 10 05:46:33 PM PDT 24
Finished Jun 10 05:46:34 PM PDT 24
Peak memory 203872 kb
Host smart-d1ada39b-ee0a-472a-a1e2-52a1db1fd944
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234448850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
3234448850
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2763769218
Short name T974
Test name
Test status
Simulation time 22698057 ps
CPU time 0.77 seconds
Started Jun 10 05:46:26 PM PDT 24
Finished Jun 10 05:46:27 PM PDT 24
Peak memory 203560 kb
Host smart-3a6d5973-234b-4043-816e-f65f17951a6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763769218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
2763769218
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1031694965
Short name T1022
Test name
Test status
Simulation time 22397534 ps
CPU time 0.77 seconds
Started Jun 10 05:46:35 PM PDT 24
Finished Jun 10 05:46:36 PM PDT 24
Peak memory 203612 kb
Host smart-2c5478b8-2971-484a-835f-c65a9dab2286
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031694965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
1031694965
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3497060466
Short name T1059
Test name
Test status
Simulation time 37496708 ps
CPU time 0.68 seconds
Started Jun 10 05:46:33 PM PDT 24
Finished Jun 10 05:46:35 PM PDT 24
Peak memory 203568 kb
Host smart-85dcfe6b-8ff1-43c1-b230-9c000b89a451
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497060466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
3497060466
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1436071713
Short name T968
Test name
Test status
Simulation time 70615854 ps
CPU time 0.76 seconds
Started Jun 10 05:46:30 PM PDT 24
Finished Jun 10 05:46:32 PM PDT 24
Peak memory 203864 kb
Host smart-87400cf7-e704-4de8-ae4f-928b7523813a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1436071713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1436071713
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.90132750
Short name T979
Test name
Test status
Simulation time 29120890 ps
CPU time 0.71 seconds
Started Jun 10 05:46:31 PM PDT 24
Finished Jun 10 05:46:32 PM PDT 24
Peak memory 203472 kb
Host smart-4939174c-557d-4fba-8ca4-ac03e095a64f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90132750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.90132750
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.288445167
Short name T1025
Test name
Test status
Simulation time 22826661 ps
CPU time 0.78 seconds
Started Jun 10 05:46:30 PM PDT 24
Finished Jun 10 05:46:32 PM PDT 24
Peak memory 203564 kb
Host smart-e2d45053-f199-4f10-ac29-ff7df3e1b966
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288445167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.288445167
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1484686746
Short name T1007
Test name
Test status
Simulation time 12109404 ps
CPU time 0.73 seconds
Started Jun 10 05:46:32 PM PDT 24
Finished Jun 10 05:46:33 PM PDT 24
Peak memory 203956 kb
Host smart-0727a18a-9da2-42cd-9262-3354efa05292
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484686746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
1484686746
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.3703674583
Short name T973
Test name
Test status
Simulation time 38696339 ps
CPU time 0.69 seconds
Started Jun 10 05:46:27 PM PDT 24
Finished Jun 10 05:46:28 PM PDT 24
Peak memory 203548 kb
Host smart-3c612a40-47c0-45fd-8d83-e5250953ece4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703674583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
3703674583
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1470509981
Short name T1061
Test name
Test status
Simulation time 78333529 ps
CPU time 0.72 seconds
Started Jun 10 05:46:30 PM PDT 24
Finished Jun 10 05:46:31 PM PDT 24
Peak memory 203616 kb
Host smart-95184b84-165c-4295-b264-b1d6112677ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470509981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1470509981
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3665244106
Short name T1069
Test name
Test status
Simulation time 1419685872 ps
CPU time 15.02 seconds
Started Jun 10 05:45:56 PM PDT 24
Finished Jun 10 05:46:11 PM PDT 24
Peak memory 215156 kb
Host smart-c4fb3277-e323-438f-9f1a-60d7c375aaff
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665244106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.3665244106
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3865693595
Short name T121
Test name
Test status
Simulation time 372225710 ps
CPU time 11.47 seconds
Started Jun 10 05:45:57 PM PDT 24
Finished Jun 10 05:46:09 PM PDT 24
Peak memory 206944 kb
Host smart-d2ab6a45-aa8e-4870-be1a-7f6e384b23e7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865693595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.3865693595
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3788141658
Short name T148
Test name
Test status
Simulation time 95574034 ps
CPU time 0.99 seconds
Started Jun 10 05:46:07 PM PDT 24
Finished Jun 10 05:46:09 PM PDT 24
Peak memory 206528 kb
Host smart-2cea8c15-f3aa-427d-b7ad-f8237d9a82f8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788141658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.3788141658
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3812202406
Short name T69
Test name
Test status
Simulation time 49548393 ps
CPU time 1.7 seconds
Started Jun 10 05:46:02 PM PDT 24
Finished Jun 10 05:46:04 PM PDT 24
Peak memory 215008 kb
Host smart-f1bde820-7919-4277-9bbd-450a2602320d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812202406 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.3812202406
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.1550504800
Short name T1013
Test name
Test status
Simulation time 41351625 ps
CPU time 1.91 seconds
Started Jun 10 05:45:56 PM PDT 24
Finished Jun 10 05:45:58 PM PDT 24
Peak memory 206804 kb
Host smart-7518cb75-9735-4631-90b1-fb16e2af8ba3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550504800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1
550504800
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2767804335
Short name T967
Test name
Test status
Simulation time 10453171 ps
CPU time 0.71 seconds
Started Jun 10 05:45:58 PM PDT 24
Finished Jun 10 05:45:59 PM PDT 24
Peak memory 203568 kb
Host smart-08c8d5be-ade5-4745-8430-36b8d59f5439
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767804335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.2
767804335
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.1267523962
Short name T1071
Test name
Test status
Simulation time 46600823 ps
CPU time 1.83 seconds
Started Jun 10 05:45:56 PM PDT 24
Finished Jun 10 05:45:59 PM PDT 24
Peak memory 215204 kb
Host smart-9167bd22-065b-45e6-9a7e-128b78d3af88
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267523962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.1267523962
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1744428219
Short name T1033
Test name
Test status
Simulation time 10567828 ps
CPU time 0.66 seconds
Started Jun 10 05:46:02 PM PDT 24
Finished Jun 10 05:46:03 PM PDT 24
Peak memory 203592 kb
Host smart-2dc80244-d772-4384-a262-8ee90fdd39bb
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744428219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1744428219
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2337058399
Short name T976
Test name
Test status
Simulation time 94535937 ps
CPU time 3.73 seconds
Started Jun 10 05:46:02 PM PDT 24
Finished Jun 10 05:46:07 PM PDT 24
Peak memory 215040 kb
Host smart-88e4fe4e-fb46-4122-ad49-f06ea9d78ba5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337058399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2337058399
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3487276359
Short name T1037
Test name
Test status
Simulation time 249580123 ps
CPU time 3.98 seconds
Started Jun 10 05:45:55 PM PDT 24
Finished Jun 10 05:45:59 PM PDT 24
Peak memory 215360 kb
Host smart-664c9d25-f910-4d09-be37-3a92bff3e57d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487276359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3
487276359
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.785622656
Short name T152
Test name
Test status
Simulation time 1129371190 ps
CPU time 24.82 seconds
Started Jun 10 05:45:54 PM PDT 24
Finished Jun 10 05:46:20 PM PDT 24
Peak memory 215280 kb
Host smart-7f12f951-26c6-4d1c-92a7-71279fc19a64
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785622656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_
tl_intg_err.785622656
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3187790030
Short name T1062
Test name
Test status
Simulation time 41162556 ps
CPU time 0.75 seconds
Started Jun 10 05:46:30 PM PDT 24
Finished Jun 10 05:46:32 PM PDT 24
Peak memory 203868 kb
Host smart-bd7a07f4-23d2-46c0-9f64-1c3de474bee9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187790030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
3187790030
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.4183473291
Short name T1036
Test name
Test status
Simulation time 40750459 ps
CPU time 0.78 seconds
Started Jun 10 05:46:31 PM PDT 24
Finished Jun 10 05:46:33 PM PDT 24
Peak memory 203880 kb
Host smart-32ccfd4b-adf1-4661-840f-542624a6942a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183473291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
4183473291
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.4002714094
Short name T965
Test name
Test status
Simulation time 14317951 ps
CPU time 0.73 seconds
Started Jun 10 05:46:32 PM PDT 24
Finished Jun 10 05:46:33 PM PDT 24
Peak memory 203852 kb
Host smart-df978b41-8ee4-433b-b7e2-c0a4613cb0c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002714094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
4002714094
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1694719886
Short name T997
Test name
Test status
Simulation time 14103078 ps
CPU time 0.73 seconds
Started Jun 10 05:46:33 PM PDT 24
Finished Jun 10 05:46:34 PM PDT 24
Peak memory 203544 kb
Host smart-4878f179-14e2-44cb-a1e1-fcdd62e6049f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694719886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
1694719886
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1768213373
Short name T983
Test name
Test status
Simulation time 22079260 ps
CPU time 0.74 seconds
Started Jun 10 05:46:32 PM PDT 24
Finished Jun 10 05:46:33 PM PDT 24
Peak memory 203784 kb
Host smart-9f1fb81b-12fb-4aba-9b72-64ae6cb2e171
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768213373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1768213373
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.32205104
Short name T980
Test name
Test status
Simulation time 21152332 ps
CPU time 0.72 seconds
Started Jun 10 05:46:35 PM PDT 24
Finished Jun 10 05:46:36 PM PDT 24
Peak memory 203588 kb
Host smart-abafeecb-9af3-4389-aa1a-ccceb01ee351
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32205104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.32205104
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.728569817
Short name T988
Test name
Test status
Simulation time 41424785 ps
CPU time 0.73 seconds
Started Jun 10 05:46:31 PM PDT 24
Finished Jun 10 05:46:32 PM PDT 24
Peak memory 203824 kb
Host smart-8a0cda79-d602-4092-981f-8c8083ff2111
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728569817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.728569817
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.3087561214
Short name T1075
Test name
Test status
Simulation time 79141346 ps
CPU time 0.73 seconds
Started Jun 10 05:46:32 PM PDT 24
Finished Jun 10 05:46:34 PM PDT 24
Peak memory 203984 kb
Host smart-fa534c3f-43bc-4bcd-8f81-845d8ea0d48c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087561214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
3087561214
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.900578941
Short name T1009
Test name
Test status
Simulation time 75510863 ps
CPU time 0.77 seconds
Started Jun 10 05:46:31 PM PDT 24
Finished Jun 10 05:46:32 PM PDT 24
Peak memory 203560 kb
Host smart-637a1378-fe6c-4a51-b70c-fb3a07b112ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900578941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.900578941
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1246784673
Short name T969
Test name
Test status
Simulation time 42154347 ps
CPU time 0.68 seconds
Started Jun 10 05:46:34 PM PDT 24
Finished Jun 10 05:46:35 PM PDT 24
Peak memory 203804 kb
Host smart-0ebcb731-4157-4c54-ab84-e07bf7ac237a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246784673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
1246784673
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3036602619
Short name T992
Test name
Test status
Simulation time 44566703 ps
CPU time 1.81 seconds
Started Jun 10 05:46:05 PM PDT 24
Finished Jun 10 05:46:07 PM PDT 24
Peak memory 215216 kb
Host smart-1b8a330b-6a64-4e09-8239-c4692f696dd8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036602619 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.3036602619
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3796442251
Short name T1011
Test name
Test status
Simulation time 93953273 ps
CPU time 1.8 seconds
Started Jun 10 05:45:55 PM PDT 24
Finished Jun 10 05:45:58 PM PDT 24
Peak memory 215124 kb
Host smart-08cfdffd-6085-4d18-bc41-71b8b24def1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796442251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3
796442251
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3496058351
Short name T987
Test name
Test status
Simulation time 62667588 ps
CPU time 0.83 seconds
Started Jun 10 05:46:01 PM PDT 24
Finished Jun 10 05:46:03 PM PDT 24
Peak memory 203528 kb
Host smart-e4422e52-3360-4f75-80a2-6f1253cc4f36
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496058351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
496058351
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.4196106594
Short name T135
Test name
Test status
Simulation time 440535544 ps
CPU time 2.92 seconds
Started Jun 10 05:45:58 PM PDT 24
Finished Jun 10 05:46:01 PM PDT 24
Peak memory 215256 kb
Host smart-bdfa5832-c14e-493a-b011-e1bf62474b75
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196106594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.4196106594
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.4126671897
Short name T1057
Test name
Test status
Simulation time 349393179 ps
CPU time 4.11 seconds
Started Jun 10 05:45:56 PM PDT 24
Finished Jun 10 05:46:00 PM PDT 24
Peak memory 215292 kb
Host smart-81eebbac-c540-47be-9e28-3b08f7acfc68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126671897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.4
126671897
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3878221844
Short name T108
Test name
Test status
Simulation time 134188372 ps
CPU time 1.64 seconds
Started Jun 10 05:46:00 PM PDT 24
Finished Jun 10 05:46:01 PM PDT 24
Peak memory 215040 kb
Host smart-27900a74-2ed7-492d-b74a-2f1f609bc7c9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878221844 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3878221844
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2487702702
Short name T139
Test name
Test status
Simulation time 22784818 ps
CPU time 1.32 seconds
Started Jun 10 05:46:02 PM PDT 24
Finished Jun 10 05:46:03 PM PDT 24
Peak memory 206888 kb
Host smart-f329513f-1a21-43cf-901f-34e399bb3cf3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487702702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2
487702702
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.813225014
Short name T961
Test name
Test status
Simulation time 19758914 ps
CPU time 0.79 seconds
Started Jun 10 05:46:00 PM PDT 24
Finished Jun 10 05:46:01 PM PDT 24
Peak memory 203600 kb
Host smart-5232b8d2-1a76-43f7-8041-6bdc3881ab4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813225014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.813225014
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.833450074
Short name T981
Test name
Test status
Simulation time 232498375 ps
CPU time 1.9 seconds
Started Jun 10 05:46:00 PM PDT 24
Finished Jun 10 05:46:02 PM PDT 24
Peak memory 215268 kb
Host smart-5f5f05d0-f6c3-4210-9c01-0e27e67e5df7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833450074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sp
i_device_same_csr_outstanding.833450074
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2694191781
Short name T250
Test name
Test status
Simulation time 4208792842 ps
CPU time 20.74 seconds
Started Jun 10 05:46:01 PM PDT 24
Finished Jun 10 05:46:22 PM PDT 24
Peak memory 215228 kb
Host smart-8bb96d1f-7bb8-4787-b523-ddadd3b9ebaa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694191781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.2694191781
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.404429590
Short name T1051
Test name
Test status
Simulation time 461839861 ps
CPU time 3.49 seconds
Started Jun 10 05:45:58 PM PDT 24
Finished Jun 10 05:46:02 PM PDT 24
Peak memory 217588 kb
Host smart-4647103f-7a90-4b9d-b9b0-aae0dc0d536c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404429590 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.404429590
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1246521939
Short name T995
Test name
Test status
Simulation time 85776487 ps
CPU time 2.54 seconds
Started Jun 10 05:45:57 PM PDT 24
Finished Jun 10 05:46:00 PM PDT 24
Peak memory 215100 kb
Host smart-868278fd-a1b1-4a8c-b0fc-d45774082557
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246521939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
246521939
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3910663963
Short name T1016
Test name
Test status
Simulation time 32854597 ps
CPU time 0.71 seconds
Started Jun 10 05:45:58 PM PDT 24
Finished Jun 10 05:45:59 PM PDT 24
Peak memory 203520 kb
Host smart-0ca3f17b-7686-4924-970c-55f274424e22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910663963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.3
910663963
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1476239494
Short name T137
Test name
Test status
Simulation time 146415937 ps
CPU time 2.71 seconds
Started Jun 10 05:46:00 PM PDT 24
Finished Jun 10 05:46:03 PM PDT 24
Peak memory 215224 kb
Host smart-555356c0-85f2-4e4c-9281-8ac3056b0414
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476239494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1476239494
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2443478505
Short name T107
Test name
Test status
Simulation time 34609612 ps
CPU time 2.29 seconds
Started Jun 10 05:46:01 PM PDT 24
Finished Jun 10 05:46:04 PM PDT 24
Peak memory 215336 kb
Host smart-a3cc801f-72c8-49c5-aeae-34a906cd7313
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443478505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2
443478505
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2702133044
Short name T150
Test name
Test status
Simulation time 976986614 ps
CPU time 21.16 seconds
Started Jun 10 05:45:59 PM PDT 24
Finished Jun 10 05:46:20 PM PDT 24
Peak memory 215200 kb
Host smart-d7e50fdf-496d-4dc5-b762-9288921a1d49
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702133044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.2702133044
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3020926601
Short name T1039
Test name
Test status
Simulation time 248798736 ps
CPU time 1.84 seconds
Started Jun 10 05:46:01 PM PDT 24
Finished Jun 10 05:46:03 PM PDT 24
Peak memory 215272 kb
Host smart-0fb9589f-9202-4db6-9f67-8c5716f7c83e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020926601 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.3020926601
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.296286375
Short name T1005
Test name
Test status
Simulation time 227304909 ps
CPU time 1.98 seconds
Started Jun 10 05:46:07 PM PDT 24
Finished Jun 10 05:46:09 PM PDT 24
Peak memory 207020 kb
Host smart-4ec1311a-5925-454b-aa6d-758c377d5072
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296286375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.296286375
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2688450679
Short name T959
Test name
Test status
Simulation time 37327257 ps
CPU time 0.73 seconds
Started Jun 10 05:46:01 PM PDT 24
Finished Jun 10 05:46:02 PM PDT 24
Peak memory 203904 kb
Host smart-5c922523-7e33-4ee7-b31a-4191a936c515
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688450679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2
688450679
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2027409096
Short name T1046
Test name
Test status
Simulation time 104443152 ps
CPU time 1.84 seconds
Started Jun 10 05:46:03 PM PDT 24
Finished Jun 10 05:46:05 PM PDT 24
Peak memory 215308 kb
Host smart-e2af14d4-9581-490d-9937-6d93d00b2441
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027409096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2027409096
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2704000906
Short name T97
Test name
Test status
Simulation time 314799137 ps
CPU time 2.79 seconds
Started Jun 10 05:46:00 PM PDT 24
Finished Jun 10 05:46:03 PM PDT 24
Peak memory 215312 kb
Host smart-7edc98e4-a821-415d-a315-eb0da941a34b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704000906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2
704000906
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2241582694
Short name T1018
Test name
Test status
Simulation time 90018790 ps
CPU time 1.95 seconds
Started Jun 10 05:46:00 PM PDT 24
Finished Jun 10 05:46:02 PM PDT 24
Peak memory 215240 kb
Host smart-943dfa9d-c149-4a13-a1f1-9325e3fe9e88
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241582694 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.2241582694
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.207700774
Short name T1038
Test name
Test status
Simulation time 106413038 ps
CPU time 2.71 seconds
Started Jun 10 05:46:04 PM PDT 24
Finished Jun 10 05:46:07 PM PDT 24
Peak memory 215180 kb
Host smart-8b0cab7f-decb-4c1a-b9db-5f28a1e05c4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207700774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.207700774
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2086044635
Short name T963
Test name
Test status
Simulation time 36020968 ps
CPU time 0.71 seconds
Started Jun 10 05:46:06 PM PDT 24
Finished Jun 10 05:46:07 PM PDT 24
Peak memory 203560 kb
Host smart-787b06eb-050f-4f99-b1f9-7f0f1461bbd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086044635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
086044635
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2626387722
Short name T1034
Test name
Test status
Simulation time 143077046 ps
CPU time 3.21 seconds
Started Jun 10 05:46:03 PM PDT 24
Finished Jun 10 05:46:07 PM PDT 24
Peak memory 215248 kb
Host smart-d11fdc25-5c53-4970-91dc-cf9980d87c0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626387722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2626387722
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3979040224
Short name T71
Test name
Test status
Simulation time 72788120 ps
CPU time 1.6 seconds
Started Jun 10 05:46:01 PM PDT 24
Finished Jun 10 05:46:03 PM PDT 24
Peak memory 215296 kb
Host smart-0a333e58-b455-4afe-b3f0-03b7be659046
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979040224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.3
979040224
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1193948024
Short name T1054
Test name
Test status
Simulation time 337193001 ps
CPU time 8.46 seconds
Started Jun 10 05:46:02 PM PDT 24
Finished Jun 10 05:46:11 PM PDT 24
Peak memory 215200 kb
Host smart-b909706a-75a3-4d3f-9595-89d09402a44b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193948024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.1193948024
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.1103134399
Short name T654
Test name
Test status
Simulation time 13419827 ps
CPU time 0.72 seconds
Started Jun 10 05:50:48 PM PDT 24
Finished Jun 10 05:50:49 PM PDT 24
Peak memory 205804 kb
Host smart-b562338c-7411-4538-88ef-16dcde504559
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103134399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.1
103134399
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.682803358
Short name T423
Test name
Test status
Simulation time 66014722 ps
CPU time 2.72 seconds
Started Jun 10 05:50:51 PM PDT 24
Finished Jun 10 05:50:54 PM PDT 24
Peak memory 232860 kb
Host smart-838c28c1-5876-41a5-93c3-9c8723c75ac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682803358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.682803358
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.1175258085
Short name T9
Test name
Test status
Simulation time 22016374 ps
CPU time 0.89 seconds
Started Jun 10 05:50:49 PM PDT 24
Finished Jun 10 05:50:50 PM PDT 24
Peak memory 206920 kb
Host smart-c93a5d2b-06a7-4762-a384-6cc3b8c48e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175258085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.1175258085
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.2327565738
Short name T43
Test name
Test status
Simulation time 9666061511 ps
CPU time 80.25 seconds
Started Jun 10 05:50:48 PM PDT 24
Finished Jun 10 05:52:09 PM PDT 24
Peak memory 241320 kb
Host smart-b050f822-d7bb-43ae-8514-257550b82ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327565738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.2327565738
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.636694758
Short name T262
Test name
Test status
Simulation time 24303512845 ps
CPU time 95.09 seconds
Started Jun 10 05:50:50 PM PDT 24
Finished Jun 10 05:52:25 PM PDT 24
Peak memory 239496 kb
Host smart-17cee211-802a-4406-afe2-128b4549044b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636694758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.636694758
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.632034618
Short name T635
Test name
Test status
Simulation time 197374763 ps
CPU time 5.53 seconds
Started Jun 10 05:50:47 PM PDT 24
Finished Jun 10 05:50:52 PM PDT 24
Peak memory 234368 kb
Host smart-84acfe84-3bde-46ba-a9ae-fd53fbf38433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632034618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.632034618
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.114027834
Short name T954
Test name
Test status
Simulation time 38491920 ps
CPU time 2.29 seconds
Started Jun 10 05:50:54 PM PDT 24
Finished Jun 10 05:50:56 PM PDT 24
Peak memory 224760 kb
Host smart-3276d6e0-b84f-45f5-9798-50f6c5a6a476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114027834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.114027834
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.2263556836
Short name T812
Test name
Test status
Simulation time 20169772724 ps
CPU time 46.15 seconds
Started Jun 10 05:50:54 PM PDT 24
Finished Jun 10 05:51:40 PM PDT 24
Peak memory 230772 kb
Host smart-5f9361b9-c033-4261-bb3f-ee9ff93e1f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263556836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2263556836
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.2992923221
Short name T473
Test name
Test status
Simulation time 4624928207 ps
CPU time 13.32 seconds
Started Jun 10 05:50:48 PM PDT 24
Finished Jun 10 05:51:01 PM PDT 24
Peak memory 233040 kb
Host smart-b53bb38e-3bbb-4b33-a6b7-9a5c8ea7b4eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992923221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.2992923221
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3664494045
Short name T443
Test name
Test status
Simulation time 788631400 ps
CPU time 4.27 seconds
Started Jun 10 05:51:07 PM PDT 24
Finished Jun 10 05:51:11 PM PDT 24
Peak memory 224780 kb
Host smart-f381c21b-f080-4d40-b16f-df8780eda40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664494045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3664494045
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3876713288
Short name T745
Test name
Test status
Simulation time 376810369 ps
CPU time 5.62 seconds
Started Jun 10 05:50:51 PM PDT 24
Finished Jun 10 05:50:57 PM PDT 24
Peak memory 219864 kb
Host smart-c8e6bb14-0fd9-4711-9f28-9ef9d2722f88
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3876713288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3876713288
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.584155289
Short name T460
Test name
Test status
Simulation time 47918645 ps
CPU time 1.02 seconds
Started Jun 10 05:50:48 PM PDT 24
Finished Jun 10 05:50:49 PM PDT 24
Peak memory 207428 kb
Host smart-1482fc6f-a0ee-4753-870d-039395ece0d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=584155289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress
_all.584155289
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.3354025229
Short name T482
Test name
Test status
Simulation time 778086224 ps
CPU time 12.69 seconds
Started Jun 10 05:50:56 PM PDT 24
Finished Jun 10 05:51:09 PM PDT 24
Peak memory 216620 kb
Host smart-cb975185-9fd2-4fee-ba0d-81e6188dd0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354025229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.3354025229
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.3447609396
Short name T411
Test name
Test status
Simulation time 17070616 ps
CPU time 0.73 seconds
Started Jun 10 05:50:59 PM PDT 24
Finished Jun 10 05:51:00 PM PDT 24
Peak memory 205920 kb
Host smart-a7c9d56b-1236-4192-a5cb-2c14f87cb2d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447609396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3447609396
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1709228680
Short name T902
Test name
Test status
Simulation time 40481618 ps
CPU time 0.73 seconds
Started Jun 10 05:50:48 PM PDT 24
Finished Jun 10 05:50:49 PM PDT 24
Peak memory 206188 kb
Host smart-7c987565-0424-43a7-9a6a-289c68aad5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709228680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1709228680
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.3270240340
Short name T844
Test name
Test status
Simulation time 401829097 ps
CPU time 3.5 seconds
Started Jun 10 05:50:51 PM PDT 24
Finished Jun 10 05:50:55 PM PDT 24
Peak memory 233024 kb
Host smart-0238fd60-a5a1-4050-a237-6f82895be283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270240340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3270240340
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.3176596141
Short name T457
Test name
Test status
Simulation time 13872327 ps
CPU time 0.72 seconds
Started Jun 10 05:50:55 PM PDT 24
Finished Jun 10 05:50:56 PM PDT 24
Peak memory 205184 kb
Host smart-c88ac6eb-8dc2-4bd3-951d-1a4d61222f71
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176596141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3
176596141
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.1309030867
Short name T550
Test name
Test status
Simulation time 42645499 ps
CPU time 2.55 seconds
Started Jun 10 05:51:00 PM PDT 24
Finished Jun 10 05:51:02 PM PDT 24
Peak memory 232996 kb
Host smart-714931b9-2e90-443f-94a0-587e25bb04ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309030867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1309030867
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.1459353620
Short name T383
Test name
Test status
Simulation time 57336521 ps
CPU time 0.76 seconds
Started Jun 10 05:50:50 PM PDT 24
Finished Jun 10 05:50:51 PM PDT 24
Peak memory 205880 kb
Host smart-81c185c3-7849-4e4f-8562-9d0183d98ae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1459353620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.1459353620
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.2903745508
Short name T82
Test name
Test status
Simulation time 955827310 ps
CPU time 12.27 seconds
Started Jun 10 05:51:02 PM PDT 24
Finished Jun 10 05:51:15 PM PDT 24
Peak memory 238336 kb
Host smart-348737c7-6319-4cad-96d8-7410fee2e501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903745508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.2903745508
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.1663036020
Short name T814
Test name
Test status
Simulation time 7848277003 ps
CPU time 81.77 seconds
Started Jun 10 05:51:10 PM PDT 24
Finished Jun 10 05:52:32 PM PDT 24
Peak memory 254780 kb
Host smart-6e1864c0-95bb-4f4b-9eaa-da59c112c032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663036020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.1663036020
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.2250004191
Short name T729
Test name
Test status
Simulation time 35897048073 ps
CPU time 83.47 seconds
Started Jun 10 05:50:58 PM PDT 24
Finished Jun 10 05:52:21 PM PDT 24
Peak memory 249560 kb
Host smart-e9792922-2087-4bcb-965f-6babe60fa93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250004191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.2250004191
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3151004033
Short name T310
Test name
Test status
Simulation time 1474766820 ps
CPU time 10.12 seconds
Started Jun 10 05:50:53 PM PDT 24
Finished Jun 10 05:51:03 PM PDT 24
Peak memory 241104 kb
Host smart-381ac03c-c751-4d6c-87c9-ade4790747e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151004033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3151004033
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.107159385
Short name T524
Test name
Test status
Simulation time 145653211 ps
CPU time 3.86 seconds
Started Jun 10 05:51:05 PM PDT 24
Finished Jun 10 05:51:09 PM PDT 24
Peak memory 233020 kb
Host smart-bf51ee76-59d1-4e64-87c0-5685d78103d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107159385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.107159385
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.1547687859
Short name T782
Test name
Test status
Simulation time 11026792138 ps
CPU time 12.05 seconds
Started Jun 10 05:51:10 PM PDT 24
Finished Jun 10 05:51:23 PM PDT 24
Peak memory 233148 kb
Host smart-c8caf477-1307-4a3e-a69a-9e4a3f7c1e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547687859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.1547687859
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2733710159
Short name T126
Test name
Test status
Simulation time 874307278 ps
CPU time 3.58 seconds
Started Jun 10 05:50:49 PM PDT 24
Finished Jun 10 05:50:53 PM PDT 24
Peak memory 224800 kb
Host smart-7859ffa2-2180-4d75-a83e-2c97a4f61f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733710159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.2733710159
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.390159306
Short name T917
Test name
Test status
Simulation time 936666267 ps
CPU time 11.09 seconds
Started Jun 10 05:50:54 PM PDT 24
Finished Jun 10 05:51:05 PM PDT 24
Peak memory 224832 kb
Host smart-1bad0973-75d3-46b9-b452-63488faed65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390159306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.390159306
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.3032418113
Short name T367
Test name
Test status
Simulation time 931309593 ps
CPU time 6.58 seconds
Started Jun 10 05:50:50 PM PDT 24
Finished Jun 10 05:50:57 PM PDT 24
Peak memory 222212 kb
Host smart-4ea3504d-4373-46a8-a6c4-452a0147b37f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3032418113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.3032418113
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.2683347334
Short name T74
Test name
Test status
Simulation time 85493261 ps
CPU time 1.22 seconds
Started Jun 10 05:51:02 PM PDT 24
Finished Jun 10 05:51:04 PM PDT 24
Peak memory 236808 kb
Host smart-5f3133d2-7345-4734-bef8-ec539ef558c8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683347334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2683347334
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.939943838
Short name T506
Test name
Test status
Simulation time 40302305 ps
CPU time 1.04 seconds
Started Jun 10 05:50:54 PM PDT 24
Finished Jun 10 05:50:55 PM PDT 24
Peak memory 207288 kb
Host smart-43d4fe92-39d4-4fa7-ae0f-e6b220f6f097
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939943838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress
_all.939943838
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2075464214
Short name T695
Test name
Test status
Simulation time 1889794458 ps
CPU time 5.95 seconds
Started Jun 10 05:50:58 PM PDT 24
Finished Jun 10 05:51:04 PM PDT 24
Peak memory 216612 kb
Host smart-3400657b-191e-4caa-859e-c5332ac7d643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075464214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.2075464214
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.825989603
Short name T791
Test name
Test status
Simulation time 87104889 ps
CPU time 1.24 seconds
Started Jun 10 05:51:00 PM PDT 24
Finished Jun 10 05:51:01 PM PDT 24
Peak memory 216396 kb
Host smart-6d165940-fd00-4262-929c-c4d6b5c9fe63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825989603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.825989603
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.692031238
Short name T397
Test name
Test status
Simulation time 18254464 ps
CPU time 0.77 seconds
Started Jun 10 05:50:53 PM PDT 24
Finished Jun 10 05:50:54 PM PDT 24
Peak memory 206200 kb
Host smart-d8470a41-3b74-4eac-a1ff-65be4b7d8d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692031238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.692031238
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.200952859
Short name T869
Test name
Test status
Simulation time 58863184655 ps
CPU time 24.68 seconds
Started Jun 10 05:50:52 PM PDT 24
Finished Jun 10 05:51:17 PM PDT 24
Peak memory 233140 kb
Host smart-55f40142-f86c-4676-b061-57d4f5c3e157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200952859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.200952859
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.3214033360
Short name T502
Test name
Test status
Simulation time 42494437 ps
CPU time 0.73 seconds
Started Jun 10 05:51:21 PM PDT 24
Finished Jun 10 05:51:22 PM PDT 24
Peak memory 205732 kb
Host smart-e02253e8-c7fd-47d1-9755-4660a3dd1f95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214033360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
3214033360
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.2944037811
Short name T538
Test name
Test status
Simulation time 357679589 ps
CPU time 5.74 seconds
Started Jun 10 05:51:21 PM PDT 24
Finished Jun 10 05:51:27 PM PDT 24
Peak memory 232984 kb
Host smart-eaa8d0a4-d901-4238-8e8d-6954736320bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944037811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.2944037811
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.663808252
Short name T330
Test name
Test status
Simulation time 26856226 ps
CPU time 0.8 seconds
Started Jun 10 05:51:20 PM PDT 24
Finished Jun 10 05:51:21 PM PDT 24
Peak memory 206964 kb
Host smart-98850de6-a536-4b99-8f5a-2943378a2f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663808252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.663808252
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.1673182689
Short name T726
Test name
Test status
Simulation time 18190043051 ps
CPU time 31.94 seconds
Started Jun 10 05:51:22 PM PDT 24
Finished Jun 10 05:51:55 PM PDT 24
Peak memory 224952 kb
Host smart-fafc4dce-95c9-4711-90b3-7d9810630d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673182689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1673182689
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.3973269330
Short name T376
Test name
Test status
Simulation time 62298683202 ps
CPU time 172.22 seconds
Started Jun 10 05:51:18 PM PDT 24
Finished Jun 10 05:54:11 PM PDT 24
Peak memory 251912 kb
Host smart-f59953ef-eefe-425c-82fd-ccb706d1621b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973269330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3973269330
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.1473161377
Short name T817
Test name
Test status
Simulation time 2501050717 ps
CPU time 58.69 seconds
Started Jun 10 05:51:38 PM PDT 24
Finished Jun 10 05:52:38 PM PDT 24
Peak memory 251840 kb
Host smart-315d4c2d-0bfd-4e20-b985-4b934412da46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473161377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.1473161377
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.1307105673
Short name T144
Test name
Test status
Simulation time 2212002750 ps
CPU time 29.36 seconds
Started Jun 10 05:51:21 PM PDT 24
Finished Jun 10 05:51:51 PM PDT 24
Peak memory 252200 kb
Host smart-0d2dd3f2-b825-4482-a412-2fc86d399afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307105673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1307105673
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.4223796283
Short name T647
Test name
Test status
Simulation time 154335818 ps
CPU time 2.45 seconds
Started Jun 10 05:51:28 PM PDT 24
Finished Jun 10 05:51:31 PM PDT 24
Peak memory 224384 kb
Host smart-08b1e1a7-0272-495b-b145-9b477061578e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4223796283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.4223796283
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.867380039
Short name T616
Test name
Test status
Simulation time 38799435848 ps
CPU time 54.84 seconds
Started Jun 10 05:51:31 PM PDT 24
Finished Jun 10 05:52:26 PM PDT 24
Peak memory 241312 kb
Host smart-9ca0d572-c8b1-4a63-bc07-a10ecf6e8bd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867380039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.867380039
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.1220879087
Short name T672
Test name
Test status
Simulation time 15193429815 ps
CPU time 13.88 seconds
Started Jun 10 05:51:26 PM PDT 24
Finished Jun 10 05:51:40 PM PDT 24
Peak memory 233040 kb
Host smart-5674f522-884a-474e-a542-d07006f8e1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220879087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.1220879087
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.1229377193
Short name T613
Test name
Test status
Simulation time 845682986 ps
CPU time 7.74 seconds
Started Jun 10 05:51:21 PM PDT 24
Finished Jun 10 05:51:29 PM PDT 24
Peak memory 241108 kb
Host smart-b322c57f-aa13-4f73-a06c-58d621d2fb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229377193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.1229377193
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.1562248193
Short name T855
Test name
Test status
Simulation time 1167429628 ps
CPU time 11.05 seconds
Started Jun 10 05:51:37 PM PDT 24
Finished Jun 10 05:51:49 PM PDT 24
Peak memory 219540 kb
Host smart-70781d06-e409-467b-b770-f3d3eaf8be38
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1562248193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.1562248193
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.1630594251
Short name T377
Test name
Test status
Simulation time 163368784 ps
CPU time 0.98 seconds
Started Jun 10 05:51:30 PM PDT 24
Finished Jun 10 05:51:32 PM PDT 24
Peak memory 207236 kb
Host smart-f6b899e8-c543-41f4-8177-fe9215eb7a9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630594251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.1630594251
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.2414125025
Short name T924
Test name
Test status
Simulation time 23418987198 ps
CPU time 32.11 seconds
Started Jun 10 05:51:23 PM PDT 24
Finished Jun 10 05:51:56 PM PDT 24
Peak memory 216752 kb
Host smart-0e23bb00-e4e2-4594-a80f-db4a78e9259f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414125025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.2414125025
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.469679329
Short name T753
Test name
Test status
Simulation time 7332451340 ps
CPU time 20.33 seconds
Started Jun 10 05:51:22 PM PDT 24
Finished Jun 10 05:51:43 PM PDT 24
Peak memory 216672 kb
Host smart-b0c4c263-cfe9-4094-be3a-c49978b22ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469679329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.469679329
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.2227366847
Short name T401
Test name
Test status
Simulation time 463370192 ps
CPU time 7.56 seconds
Started Jun 10 05:51:19 PM PDT 24
Finished Jun 10 05:51:26 PM PDT 24
Peak memory 216620 kb
Host smart-c4dd63ec-b13d-478c-bd5c-680e4083dae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227366847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2227366847
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.2543675811
Short name T90
Test name
Test status
Simulation time 111587230 ps
CPU time 0.89 seconds
Started Jun 10 05:51:19 PM PDT 24
Finished Jun 10 05:51:20 PM PDT 24
Peak memory 206196 kb
Host smart-23600d02-d29f-4102-9b5e-9c68708aa051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543675811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2543675811
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.2033466782
Short name T341
Test name
Test status
Simulation time 302963517 ps
CPU time 2.32 seconds
Started Jun 10 05:51:32 PM PDT 24
Finished Jun 10 05:51:35 PM PDT 24
Peak memory 223904 kb
Host smart-770613d7-5e55-4470-8a70-1afd6c1b392c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033466782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2033466782
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.2711999189
Short name T645
Test name
Test status
Simulation time 906861763 ps
CPU time 8.56 seconds
Started Jun 10 05:51:25 PM PDT 24
Finished Jun 10 05:51:34 PM PDT 24
Peak memory 224752 kb
Host smart-8477ab7e-4b9e-4285-91be-ec10884f7a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711999189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.2711999189
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.2207052834
Short name T835
Test name
Test status
Simulation time 47286071 ps
CPU time 0.83 seconds
Started Jun 10 05:51:25 PM PDT 24
Finished Jun 10 05:51:26 PM PDT 24
Peak memory 207208 kb
Host smart-ef08230c-b9c2-4aa0-890c-88b50a698dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207052834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.2207052834
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.155352944
Short name T334
Test name
Test status
Simulation time 115565706 ps
CPU time 0.99 seconds
Started Jun 10 05:51:26 PM PDT 24
Finished Jun 10 05:51:27 PM PDT 24
Peak memory 216432 kb
Host smart-5e80268f-8baa-4427-b5ac-1d6505846181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155352944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.155352944
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.3527673050
Short name T767
Test name
Test status
Simulation time 148602237756 ps
CPU time 374.7 seconds
Started Jun 10 05:51:29 PM PDT 24
Finished Jun 10 05:57:44 PM PDT 24
Peak memory 257684 kb
Host smart-a8822fb0-034b-43e4-8786-440e9dd7028e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527673050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.3527673050
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.513127657
Short name T143
Test name
Test status
Simulation time 10262848685 ps
CPU time 27.01 seconds
Started Jun 10 05:51:24 PM PDT 24
Finished Jun 10 05:51:51 PM PDT 24
Peak memory 233068 kb
Host smart-b1ae3936-ff45-47e7-88a3-affd9b5ee36a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513127657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.513127657
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.3226705660
Short name T406
Test name
Test status
Simulation time 1029527972 ps
CPU time 14.66 seconds
Started Jun 10 05:51:25 PM PDT 24
Finished Jun 10 05:51:40 PM PDT 24
Peak memory 224752 kb
Host smart-34ef629f-4682-443f-ba18-982fcb1f4a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226705660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3226705660
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.3855749827
Short name T919
Test name
Test status
Simulation time 2830931954 ps
CPU time 26.73 seconds
Started Jun 10 05:51:23 PM PDT 24
Finished Jun 10 05:51:50 PM PDT 24
Peak memory 240744 kb
Host smart-80355609-5cf5-4297-8d1d-14b3773e3a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855749827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3855749827
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2835332148
Short name T941
Test name
Test status
Simulation time 1586486969 ps
CPU time 6.07 seconds
Started Jun 10 05:51:27 PM PDT 24
Finished Jun 10 05:51:33 PM PDT 24
Peak memory 224772 kb
Host smart-54ce5cf3-5fc9-4854-8a8e-9ba509e53053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835332148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2835332148
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.2986388142
Short name T708
Test name
Test status
Simulation time 963776747 ps
CPU time 2.91 seconds
Started Jun 10 05:51:31 PM PDT 24
Finished Jun 10 05:51:35 PM PDT 24
Peak memory 224832 kb
Host smart-fcfab14c-1a5e-4e62-8a12-ac709a0a3dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986388142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2986388142
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.2527293628
Short name T877
Test name
Test status
Simulation time 2876420540 ps
CPU time 8.86 seconds
Started Jun 10 05:51:29 PM PDT 24
Finished Jun 10 05:51:38 PM PDT 24
Peak memory 223448 kb
Host smart-20732b9b-2fb7-47d7-baae-598f5d9990f4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2527293628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.2527293628
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.2725955844
Short name T662
Test name
Test status
Simulation time 37965097668 ps
CPU time 51.35 seconds
Started Jun 10 05:51:30 PM PDT 24
Finished Jun 10 05:52:21 PM PDT 24
Peak memory 252400 kb
Host smart-684e2288-d3fd-45ff-b412-0b0d523032c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2725955844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.2725955844
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.128505913
Short name T825
Test name
Test status
Simulation time 18096330391 ps
CPU time 24.45 seconds
Started Jun 10 05:51:25 PM PDT 24
Finished Jun 10 05:51:50 PM PDT 24
Peak memory 216876 kb
Host smart-704e7a1b-d81e-4885-9289-99d638585a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128505913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.128505913
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.996288007
Short name T394
Test name
Test status
Simulation time 12471050 ps
CPU time 0.72 seconds
Started Jun 10 05:51:32 PM PDT 24
Finished Jun 10 05:51:33 PM PDT 24
Peak memory 205972 kb
Host smart-b2ecd549-d955-4a9f-9e77-1c0fcaf1081f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996288007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.996288007
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.2873540461
Short name T631
Test name
Test status
Simulation time 27288345 ps
CPU time 0.71 seconds
Started Jun 10 05:51:27 PM PDT 24
Finished Jun 10 05:51:28 PM PDT 24
Peak memory 205940 kb
Host smart-e18f00b5-e15d-4c53-b67d-6ba164252028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873540461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.2873540461
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.2493673375
Short name T822
Test name
Test status
Simulation time 112553483 ps
CPU time 0.85 seconds
Started Jun 10 05:51:29 PM PDT 24
Finished Jun 10 05:51:30 PM PDT 24
Peak memory 207252 kb
Host smart-a297c650-2b0b-41dc-9d3b-9d59f688a00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493673375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.2493673375
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.1123797775
Short name T531
Test name
Test status
Simulation time 12612126329 ps
CPU time 7.48 seconds
Started Jun 10 05:51:35 PM PDT 24
Finished Jun 10 05:51:43 PM PDT 24
Peak memory 233048 kb
Host smart-c77b8b54-45c0-4570-9b38-3cb6f4e5a187
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123797775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.1123797775
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2916182363
Short name T362
Test name
Test status
Simulation time 14155245 ps
CPU time 0.74 seconds
Started Jun 10 05:51:30 PM PDT 24
Finished Jun 10 05:51:31 PM PDT 24
Peak memory 206084 kb
Host smart-0e9de823-581a-4333-bbf6-479850d96fb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2916182363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2916182363
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.122443627
Short name T404
Test name
Test status
Simulation time 1904512479 ps
CPU time 6.3 seconds
Started Jun 10 05:51:26 PM PDT 24
Finished Jun 10 05:51:33 PM PDT 24
Peak memory 224856 kb
Host smart-e3abc760-feaf-4e2b-bed6-c2c607e48894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122443627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.122443627
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.1585453163
Short name T719
Test name
Test status
Simulation time 20759193 ps
CPU time 0.79 seconds
Started Jun 10 05:51:35 PM PDT 24
Finished Jun 10 05:51:36 PM PDT 24
Peak memory 206884 kb
Host smart-2e0f5c57-c602-4618-ab61-61e18b6d2777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585453163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1585453163
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.732261912
Short name T623
Test name
Test status
Simulation time 11918307800 ps
CPU time 98.66 seconds
Started Jun 10 05:51:34 PM PDT 24
Finished Jun 10 05:53:13 PM PDT 24
Peak memory 238252 kb
Host smart-26ef8226-4ae7-48e9-a0c6-afb748241bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732261912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.732261912
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.1089112693
Short name T58
Test name
Test status
Simulation time 15468911303 ps
CPU time 38.4 seconds
Started Jun 10 05:51:36 PM PDT 24
Finished Jun 10 05:52:15 PM PDT 24
Peak memory 224820 kb
Host smart-b364e149-8396-42c3-ac79-c75214676991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089112693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.1089112693
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.4216252258
Short name T425
Test name
Test status
Simulation time 307798080 ps
CPU time 6.77 seconds
Started Jun 10 05:51:27 PM PDT 24
Finished Jun 10 05:51:35 PM PDT 24
Peak memory 238712 kb
Host smart-ed653df1-c29f-4103-be73-6366c3d69a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216252258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.4216252258
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.947542876
Short name T952
Test name
Test status
Simulation time 3382269470 ps
CPU time 4.58 seconds
Started Jun 10 05:51:34 PM PDT 24
Finished Jun 10 05:51:39 PM PDT 24
Peak memory 224860 kb
Host smart-31650554-174c-4362-abcc-2d5a2fa1cb9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947542876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.947542876
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.4089495662
Short name T449
Test name
Test status
Simulation time 4826134139 ps
CPU time 45.96 seconds
Started Jun 10 05:51:32 PM PDT 24
Finished Jun 10 05:52:18 PM PDT 24
Peak memory 237332 kb
Host smart-8079da1c-42db-445a-bdc2-3724100544d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089495662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.4089495662
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.3516107927
Short name T785
Test name
Test status
Simulation time 1352108796 ps
CPU time 4.86 seconds
Started Jun 10 05:51:31 PM PDT 24
Finished Jun 10 05:51:37 PM PDT 24
Peak memory 224748 kb
Host smart-77e345f4-1cfc-4e44-bef7-36e7e02e317f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516107927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.3516107927
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.3418932143
Short name T749
Test name
Test status
Simulation time 3568034300 ps
CPU time 13.28 seconds
Started Jun 10 05:51:36 PM PDT 24
Finished Jun 10 05:51:50 PM PDT 24
Peak memory 228412 kb
Host smart-be767f9f-7c38-4c44-9314-a675f6b25d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418932143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.3418932143
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.4245896968
Short name T601
Test name
Test status
Simulation time 2398418691 ps
CPU time 15.21 seconds
Started Jun 10 05:51:32 PM PDT 24
Finished Jun 10 05:51:48 PM PDT 24
Peak memory 223456 kb
Host smart-2ed17a77-2931-43d6-b08f-4519ae6825bd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4245896968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.4245896968
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.1536731468
Short name T156
Test name
Test status
Simulation time 36072305703 ps
CPU time 149.23 seconds
Started Jun 10 05:51:29 PM PDT 24
Finished Jun 10 05:53:59 PM PDT 24
Peak memory 235424 kb
Host smart-9ffb9886-b909-4f9d-941c-872c52c948fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536731468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.1536731468
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3328622966
Short name T163
Test name
Test status
Simulation time 1263848382 ps
CPU time 4.34 seconds
Started Jun 10 05:51:27 PM PDT 24
Finished Jun 10 05:51:32 PM PDT 24
Peak memory 216572 kb
Host smart-53e9d12b-acff-4443-a5c0-5deb215f8e4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328622966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3328622966
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.3013630120
Short name T821
Test name
Test status
Simulation time 40274128 ps
CPU time 0.69 seconds
Started Jun 10 05:51:29 PM PDT 24
Finished Jun 10 05:51:30 PM PDT 24
Peak memory 205932 kb
Host smart-0841a7aa-4294-4092-891d-57f1c9784eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013630120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3013630120
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.3198834892
Short name T356
Test name
Test status
Simulation time 44939663 ps
CPU time 0.93 seconds
Started Jun 10 05:51:27 PM PDT 24
Finished Jun 10 05:51:28 PM PDT 24
Peak memory 206188 kb
Host smart-3b6ce780-0430-49b3-b3f1-836ab7b7e990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198834892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3198834892
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.1343413367
Short name T945
Test name
Test status
Simulation time 1488303453 ps
CPU time 4.89 seconds
Started Jun 10 05:51:23 PM PDT 24
Finished Jun 10 05:51:28 PM PDT 24
Peak memory 233004 kb
Host smart-55fa5977-c54c-4347-9a2a-fdcee3e7e19f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343413367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.1343413367
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.2091480386
Short name T867
Test name
Test status
Simulation time 46608387 ps
CPU time 0.69 seconds
Started Jun 10 05:51:39 PM PDT 24
Finished Jun 10 05:51:40 PM PDT 24
Peak memory 205072 kb
Host smart-c8d946ef-b989-46fb-b0fa-8736d8bffebc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091480386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
2091480386
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.4273831257
Short name T292
Test name
Test status
Simulation time 1061565369 ps
CPU time 11.88 seconds
Started Jun 10 05:51:30 PM PDT 24
Finished Jun 10 05:51:42 PM PDT 24
Peak memory 232988 kb
Host smart-8ba958d6-2b17-4461-960c-a84795b3cfb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273831257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.4273831257
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.25183079
Short name T727
Test name
Test status
Simulation time 20515177 ps
CPU time 0.75 seconds
Started Jun 10 05:51:29 PM PDT 24
Finished Jun 10 05:51:30 PM PDT 24
Peak memory 205888 kb
Host smart-f0c4ae8c-43d1-4484-b4a8-415b5efe937d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25183079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.25183079
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.2698669597
Short name T816
Test name
Test status
Simulation time 11920083831 ps
CPU time 92.82 seconds
Started Jun 10 05:51:36 PM PDT 24
Finished Jun 10 05:53:10 PM PDT 24
Peak memory 249520 kb
Host smart-3904ef24-8529-43c8-8f6d-2c2444508352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698669597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.2698669597
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.807210911
Short name T736
Test name
Test status
Simulation time 210721740 ps
CPU time 7.19 seconds
Started Jun 10 05:51:31 PM PDT 24
Finished Jun 10 05:51:39 PM PDT 24
Peak memory 236436 kb
Host smart-f0f49f25-2b02-40f5-8df6-7e579e543002
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807210911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.807210911
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.545790600
Short name T290
Test name
Test status
Simulation time 234238824 ps
CPU time 4.99 seconds
Started Jun 10 05:51:31 PM PDT 24
Finished Jun 10 05:51:37 PM PDT 24
Peak memory 233008 kb
Host smart-a124ed42-05b0-4977-819f-65e830bee73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545790600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.545790600
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.71400311
Short name T182
Test name
Test status
Simulation time 1589580772 ps
CPU time 8.81 seconds
Started Jun 10 05:51:36 PM PDT 24
Finished Jun 10 05:51:45 PM PDT 24
Peak memory 235676 kb
Host smart-cd525bf7-4b6b-4a7b-8749-0761bf8fe36f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71400311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.71400311
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.2621892088
Short name T166
Test name
Test status
Simulation time 322530918 ps
CPU time 4.04 seconds
Started Jun 10 05:51:33 PM PDT 24
Finished Jun 10 05:51:37 PM PDT 24
Peak memory 233016 kb
Host smart-b50f700e-d8cf-4c28-a66f-0811c5ee9d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621892088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.2621892088
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.1416768495
Short name T807
Test name
Test status
Simulation time 3553650392 ps
CPU time 13.6 seconds
Started Jun 10 05:51:34 PM PDT 24
Finished Jun 10 05:51:48 PM PDT 24
Peak memory 240720 kb
Host smart-0857aea6-390f-4cd5-a2ff-4b4ae351d943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416768495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.1416768495
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.2646149272
Short name T804
Test name
Test status
Simulation time 1498847814 ps
CPU time 6.6 seconds
Started Jun 10 05:51:35 PM PDT 24
Finished Jun 10 05:51:42 PM PDT 24
Peak memory 223448 kb
Host smart-f6a3cc12-cb0f-4dba-b5dd-abcfbcc51ed8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2646149272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.2646149272
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.2629004691
Short name T571
Test name
Test status
Simulation time 8709058343 ps
CPU time 48.37 seconds
Started Jun 10 05:51:33 PM PDT 24
Finished Jun 10 05:52:22 PM PDT 24
Peak memory 216748 kb
Host smart-ca16fea5-001a-4e96-8221-2fcdb6069a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629004691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.2629004691
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.3396801119
Short name T608
Test name
Test status
Simulation time 78492602 ps
CPU time 1 seconds
Started Jun 10 05:51:31 PM PDT 24
Finished Jun 10 05:51:33 PM PDT 24
Peak memory 206272 kb
Host smart-9b914aea-7408-478a-b0d1-9deb45024f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396801119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.3396801119
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.3692069138
Short name T688
Test name
Test status
Simulation time 218344801 ps
CPU time 1.4 seconds
Started Jun 10 05:51:35 PM PDT 24
Finished Jun 10 05:51:37 PM PDT 24
Peak memory 216588 kb
Host smart-3d82423f-3a2d-4003-ab33-85d388225bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692069138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.3692069138
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.31992562
Short name T650
Test name
Test status
Simulation time 39618658 ps
CPU time 0.78 seconds
Started Jun 10 05:51:32 PM PDT 24
Finished Jun 10 05:51:33 PM PDT 24
Peak memory 206196 kb
Host smart-3e74d6b0-45b2-45a0-a286-432947c55d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31992562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.31992562
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.1651136489
Short name T689
Test name
Test status
Simulation time 2511969762 ps
CPU time 9.87 seconds
Started Jun 10 05:51:34 PM PDT 24
Finished Jun 10 05:51:45 PM PDT 24
Peak memory 224924 kb
Host smart-fa709c22-e83a-46af-b976-18a65ff12909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651136489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.1651136489
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.3324994325
Short name T848
Test name
Test status
Simulation time 81376241 ps
CPU time 0.74 seconds
Started Jun 10 05:51:36 PM PDT 24
Finished Jun 10 05:51:38 PM PDT 24
Peak memory 206024 kb
Host smart-f7d3dc9b-703e-4dbc-b170-a39559e4f6ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324994325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
3324994325
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.270628188
Short name T212
Test name
Test status
Simulation time 504348717 ps
CPU time 9.18 seconds
Started Jun 10 05:51:40 PM PDT 24
Finished Jun 10 05:51:49 PM PDT 24
Peak memory 232996 kb
Host smart-3cca7a39-d256-4a76-b4e9-92a9d4118eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270628188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.270628188
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.324260735
Short name T725
Test name
Test status
Simulation time 32740159 ps
CPU time 0.8 seconds
Started Jun 10 05:51:32 PM PDT 24
Finished Jun 10 05:51:34 PM PDT 24
Peak memory 206140 kb
Host smart-125ed39a-715b-44f7-8670-f71cbe9a58f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324260735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.324260735
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.4081265429
Short name T612
Test name
Test status
Simulation time 41627778 ps
CPU time 0.76 seconds
Started Jun 10 05:51:30 PM PDT 24
Finished Jun 10 05:51:31 PM PDT 24
Peak memory 216120 kb
Host smart-39a6cf67-937d-4cdc-a813-b8e9ec7d4e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081265429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.4081265429
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.1283661255
Short name T802
Test name
Test status
Simulation time 13424551261 ps
CPU time 52.85 seconds
Started Jun 10 05:51:34 PM PDT 24
Finished Jun 10 05:52:28 PM PDT 24
Peak memory 224924 kb
Host smart-311e29ba-bb32-486f-a5f4-3a37509f2e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283661255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.1283661255
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.1168599691
Short name T230
Test name
Test status
Simulation time 27711778706 ps
CPU time 95.54 seconds
Started Jun 10 05:51:39 PM PDT 24
Finished Jun 10 05:53:15 PM PDT 24
Peak memory 262428 kb
Host smart-c736f1a8-a80f-49e2-9267-b04fabf90b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168599691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.1168599691
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.1874934458
Short name T145
Test name
Test status
Simulation time 429976631 ps
CPU time 9.54 seconds
Started Jun 10 05:51:36 PM PDT 24
Finished Jun 10 05:51:46 PM PDT 24
Peak memory 235796 kb
Host smart-61c9848a-1343-4c3b-816d-3a715859de42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874934458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1874934458
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.67334809
Short name T278
Test name
Test status
Simulation time 1105182148 ps
CPU time 4.22 seconds
Started Jun 10 05:51:35 PM PDT 24
Finished Jun 10 05:51:40 PM PDT 24
Peak memory 224780 kb
Host smart-c8cd78ce-2b56-47ec-8f3f-b081eec41754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67334809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.67334809
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.3510791292
Short name T199
Test name
Test status
Simulation time 17636381470 ps
CPU time 46.83 seconds
Started Jun 10 05:51:35 PM PDT 24
Finished Jun 10 05:52:23 PM PDT 24
Peak memory 224900 kb
Host smart-9c896923-172d-4a95-9d1a-af91e407e131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510791292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3510791292
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.1262873134
Short name T272
Test name
Test status
Simulation time 2186687204 ps
CPU time 5.53 seconds
Started Jun 10 05:51:36 PM PDT 24
Finished Jun 10 05:51:42 PM PDT 24
Peak memory 241200 kb
Host smart-98bb8846-fedc-4500-9d63-dbf84cbd21e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262873134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.1262873134
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.3769068154
Short name T181
Test name
Test status
Simulation time 8188150687 ps
CPU time 24.55 seconds
Started Jun 10 05:51:34 PM PDT 24
Finished Jun 10 05:51:59 PM PDT 24
Peak memory 241212 kb
Host smart-20281bcc-1daa-44f0-9159-2aa885011832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769068154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3769068154
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.937666846
Short name T936
Test name
Test status
Simulation time 2592124556 ps
CPU time 6.5 seconds
Started Jun 10 05:51:41 PM PDT 24
Finished Jun 10 05:51:48 PM PDT 24
Peak memory 219744 kb
Host smart-fefc958d-1b54-4348-bf9c-a79421fa0707
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=937666846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dire
ct.937666846
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.4175040418
Short name T165
Test name
Test status
Simulation time 48951710800 ps
CPU time 39.35 seconds
Started Jun 10 05:51:34 PM PDT 24
Finished Jun 10 05:52:14 PM PDT 24
Peak memory 249608 kb
Host smart-492060dd-cea4-4415-9e27-824c29471d11
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175040418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.4175040418
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.290854975
Short name T128
Test name
Test status
Simulation time 7679366411 ps
CPU time 29.17 seconds
Started Jun 10 05:51:33 PM PDT 24
Finished Jun 10 05:52:03 PM PDT 24
Peak memory 217052 kb
Host smart-fa9b1564-1e74-4462-947b-dab875156fd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290854975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.290854975
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.3696721585
Short name T684
Test name
Test status
Simulation time 1211236729 ps
CPU time 6.82 seconds
Started Jun 10 05:51:36 PM PDT 24
Finished Jun 10 05:51:44 PM PDT 24
Peak memory 216492 kb
Host smart-7316fbb2-cb16-46d1-b3b0-393d950c5d4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696721585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3696721585
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.3699813374
Short name T331
Test name
Test status
Simulation time 26483726 ps
CPU time 0.69 seconds
Started Jun 10 05:51:32 PM PDT 24
Finished Jun 10 05:51:34 PM PDT 24
Peak memory 205920 kb
Host smart-987374ff-f9e9-4980-a1f0-e4c5afcef830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699813374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3699813374
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.1511405730
Short name T510
Test name
Test status
Simulation time 28274342 ps
CPU time 0.85 seconds
Started Jun 10 05:51:36 PM PDT 24
Finished Jun 10 05:51:38 PM PDT 24
Peak memory 206208 kb
Host smart-e9582c1f-de3c-4e36-a887-84a27bbc91f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511405730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.1511405730
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.1778029611
Short name T599
Test name
Test status
Simulation time 239934874 ps
CPU time 6.35 seconds
Started Jun 10 05:51:38 PM PDT 24
Finished Jun 10 05:51:45 PM PDT 24
Peak memory 241120 kb
Host smart-e476a372-c07a-4774-a17b-6b480f1d88b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778029611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1778029611
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.2872883626
Short name T637
Test name
Test status
Simulation time 38066434 ps
CPU time 0.73 seconds
Started Jun 10 05:51:36 PM PDT 24
Finished Jun 10 05:51:38 PM PDT 24
Peak memory 205780 kb
Host smart-e297400f-4015-4651-bc0e-877f04656061
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872883626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
2872883626
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.1732142017
Short name T543
Test name
Test status
Simulation time 472675299 ps
CPU time 2.49 seconds
Started Jun 10 05:51:48 PM PDT 24
Finished Jun 10 05:51:51 PM PDT 24
Peak memory 232724 kb
Host smart-30d8a54f-5837-4334-8a27-7f7944a77ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732142017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.1732142017
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.790500778
Short name T883
Test name
Test status
Simulation time 56381085 ps
CPU time 0.78 seconds
Started Jun 10 05:51:39 PM PDT 24
Finished Jun 10 05:51:41 PM PDT 24
Peak memory 205952 kb
Host smart-bc645275-a014-4fa5-97a9-f958e8e31586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790500778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.790500778
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.4026743118
Short name T61
Test name
Test status
Simulation time 138738837344 ps
CPU time 130.99 seconds
Started Jun 10 05:51:39 PM PDT 24
Finished Jun 10 05:53:51 PM PDT 24
Peak memory 241320 kb
Host smart-1ff2b2c4-fda4-40a2-a60d-df47ad4bf844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026743118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.4026743118
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.161167206
Short name T953
Test name
Test status
Simulation time 28422439185 ps
CPU time 79.84 seconds
Started Jun 10 05:51:40 PM PDT 24
Finished Jun 10 05:53:00 PM PDT 24
Peak memory 235244 kb
Host smart-3e700b83-1758-4bc1-beb6-cee0bc7e79fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161167206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.161167206
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.1421657115
Short name T46
Test name
Test status
Simulation time 4511035943 ps
CPU time 36.58 seconds
Started Jun 10 05:51:39 PM PDT 24
Finished Jun 10 05:52:16 PM PDT 24
Peak memory 233120 kb
Host smart-a7878875-489c-403a-b7e9-bad76fc5bbcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421657115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1421657115
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.73101983
Short name T285
Test name
Test status
Simulation time 995659627 ps
CPU time 9.77 seconds
Started Jun 10 05:51:47 PM PDT 24
Finished Jun 10 05:51:58 PM PDT 24
Peak memory 233024 kb
Host smart-779927da-d6d6-43eb-9ff3-4a31548d83ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=73101983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.73101983
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.866131505
Short name T607
Test name
Test status
Simulation time 7084750372 ps
CPU time 11.94 seconds
Started Jun 10 05:51:46 PM PDT 24
Finished Jun 10 05:51:58 PM PDT 24
Peak memory 241276 kb
Host smart-94cfcf8e-5d29-45ce-a454-7128d1f9e15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866131505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.866131505
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.4291398435
Short name T624
Test name
Test status
Simulation time 210069834 ps
CPU time 2.66 seconds
Started Jun 10 05:51:35 PM PDT 24
Finished Jun 10 05:51:39 PM PDT 24
Peak memory 224712 kb
Host smart-e27d98f2-eebe-4cbb-842c-77747a9f428b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291398435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.4291398435
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.3370888318
Short name T589
Test name
Test status
Simulation time 820396269 ps
CPU time 12.98 seconds
Started Jun 10 05:51:53 PM PDT 24
Finished Jun 10 05:52:07 PM PDT 24
Peak memory 223352 kb
Host smart-6fc723cb-7290-4159-88b4-b37bbeb2ba5c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3370888318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.3370888318
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.3953009892
Short name T378
Test name
Test status
Simulation time 20583308834 ps
CPU time 27.19 seconds
Started Jun 10 05:51:49 PM PDT 24
Finished Jun 10 05:52:17 PM PDT 24
Peak memory 218220 kb
Host smart-6e67c43b-1ec3-4282-93c1-797068c460f8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953009892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.3953009892
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.594031190
Short name T317
Test name
Test status
Simulation time 8868248574 ps
CPU time 13.2 seconds
Started Jun 10 05:51:50 PM PDT 24
Finished Jun 10 05:52:04 PM PDT 24
Peak memory 216680 kb
Host smart-1938af28-a795-419d-ae12-98e28622d8e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594031190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.594031190
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.3829881024
Short name T865
Test name
Test status
Simulation time 23856238907 ps
CPU time 11.04 seconds
Started Jun 10 05:51:42 PM PDT 24
Finished Jun 10 05:51:53 PM PDT 24
Peak memory 216844 kb
Host smart-926d28da-a251-434b-8865-f66b6c03bc40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829881024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3829881024
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.1736235960
Short name T540
Test name
Test status
Simulation time 56695936 ps
CPU time 1.2 seconds
Started Jun 10 05:51:38 PM PDT 24
Finished Jun 10 05:51:40 PM PDT 24
Peak memory 208140 kb
Host smart-96dd0e39-042a-43a9-a0db-427407a6c138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736235960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1736235960
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.851957207
Short name T508
Test name
Test status
Simulation time 72397039 ps
CPU time 0.99 seconds
Started Jun 10 05:51:48 PM PDT 24
Finished Jun 10 05:51:49 PM PDT 24
Peak memory 207212 kb
Host smart-f012e103-4d68-4eb9-a1e7-3bc02a7e571a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851957207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.851957207
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.275175661
Short name T180
Test name
Test status
Simulation time 7530626520 ps
CPU time 8.99 seconds
Started Jun 10 05:51:37 PM PDT 24
Finished Jun 10 05:51:46 PM PDT 24
Peak memory 233152 kb
Host smart-2a87cf89-a001-47e3-a244-a8819763152e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275175661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.275175661
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.1742933376
Short name T728
Test name
Test status
Simulation time 39118117 ps
CPU time 0.7 seconds
Started Jun 10 05:51:43 PM PDT 24
Finished Jun 10 05:51:44 PM PDT 24
Peak memory 206112 kb
Host smart-2c1a5ca2-456a-4787-9ba7-49d2bd03cf07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742933376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
1742933376
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.3910376050
Short name T873
Test name
Test status
Simulation time 2131303714 ps
CPU time 5.15 seconds
Started Jun 10 05:51:56 PM PDT 24
Finished Jun 10 05:52:02 PM PDT 24
Peak memory 224804 kb
Host smart-57e42923-c41b-4fa8-b849-26f4454c1975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910376050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.3910376050
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.3950085622
Short name T774
Test name
Test status
Simulation time 50251872 ps
CPU time 0.77 seconds
Started Jun 10 05:51:55 PM PDT 24
Finished Jun 10 05:51:57 PM PDT 24
Peak memory 206840 kb
Host smart-02e2ae85-c9e3-4092-a0a9-600d961ef3e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950085622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.3950085622
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.440453116
Short name T24
Test name
Test status
Simulation time 4831953569 ps
CPU time 29.73 seconds
Started Jun 10 05:51:59 PM PDT 24
Finished Jun 10 05:52:29 PM PDT 24
Peak memory 240828 kb
Host smart-8d1b09e8-1874-4449-aeec-b30881497e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440453116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.440453116
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.1925393396
Short name T588
Test name
Test status
Simulation time 8800482732 ps
CPU time 53.12 seconds
Started Jun 10 05:51:44 PM PDT 24
Finished Jun 10 05:52:37 PM PDT 24
Peak memory 253688 kb
Host smart-904793f2-339a-4e38-915f-61bdb1f390ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925393396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.1925393396
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.2351048094
Short name T679
Test name
Test status
Simulation time 647762253 ps
CPU time 8.49 seconds
Started Jun 10 05:51:50 PM PDT 24
Finished Jun 10 05:51:59 PM PDT 24
Peak memory 233004 kb
Host smart-2b1456df-ec36-4f96-9a90-53386f02319d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351048094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.2351048094
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.3612443713
Short name T481
Test name
Test status
Simulation time 1174594724 ps
CPU time 4.52 seconds
Started Jun 10 05:51:51 PM PDT 24
Finished Jun 10 05:51:56 PM PDT 24
Peak memory 233004 kb
Host smart-e0c0b053-2c0b-4c3d-816b-6bf552fa6625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612443713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.3612443713
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.2375898846
Short name T329
Test name
Test status
Simulation time 114230201 ps
CPU time 2.32 seconds
Started Jun 10 05:51:52 PM PDT 24
Finished Jun 10 05:51:55 PM PDT 24
Peak memory 233048 kb
Host smart-5fd51d2b-1f6d-4136-b886-ddd168006d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375898846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.2375898846
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.770584961
Short name T403
Test name
Test status
Simulation time 14022531545 ps
CPU time 13.51 seconds
Started Jun 10 05:51:49 PM PDT 24
Finished Jun 10 05:52:03 PM PDT 24
Peak memory 224856 kb
Host smart-e67ebf7a-54b3-4342-be93-0053c8fd1b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770584961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap
.770584961
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.19350008
Short name T640
Test name
Test status
Simulation time 1895202185 ps
CPU time 6.97 seconds
Started Jun 10 05:51:50 PM PDT 24
Finished Jun 10 05:51:58 PM PDT 24
Peak memory 233000 kb
Host smart-5ad22c67-9f09-4e85-b1f4-93da0fdc0cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19350008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.19350008
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.2141815596
Short name T651
Test name
Test status
Simulation time 4940375359 ps
CPU time 4.21 seconds
Started Jun 10 05:51:48 PM PDT 24
Finished Jun 10 05:51:53 PM PDT 24
Peak memory 221076 kb
Host smart-49acda92-cdc2-4dbb-b33b-bf911b45915f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2141815596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.2141815596
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.1272707230
Short name T559
Test name
Test status
Simulation time 1631205730 ps
CPU time 16.39 seconds
Started Jun 10 05:51:49 PM PDT 24
Finished Jun 10 05:52:06 PM PDT 24
Peak memory 216628 kb
Host smart-c95a1136-5c02-4ecf-ac5e-f008923739ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272707230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.1272707230
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.1852841574
Short name T839
Test name
Test status
Simulation time 8741715298 ps
CPU time 21.96 seconds
Started Jun 10 05:51:54 PM PDT 24
Finished Jun 10 05:52:16 PM PDT 24
Peak memory 216684 kb
Host smart-1c3d84cd-39bc-4b16-8290-d846a4d970cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852841574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1852841574
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.3136350918
Short name T478
Test name
Test status
Simulation time 348557283 ps
CPU time 2.51 seconds
Started Jun 10 05:51:41 PM PDT 24
Finished Jun 10 05:51:43 PM PDT 24
Peak memory 216616 kb
Host smart-5cf100ad-ddf4-4f0a-8788-64f2fbd45947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136350918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.3136350918
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.165016522
Short name T479
Test name
Test status
Simulation time 18203369 ps
CPU time 0.74 seconds
Started Jun 10 05:51:38 PM PDT 24
Finished Jun 10 05:51:39 PM PDT 24
Peak memory 206128 kb
Host smart-fc91855c-760d-4318-8c2b-bca6b6add1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165016522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.165016522
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1230163826
Short name T866
Test name
Test status
Simulation time 20651551348 ps
CPU time 9.8 seconds
Started Jun 10 05:51:39 PM PDT 24
Finished Jun 10 05:51:50 PM PDT 24
Peak memory 224836 kb
Host smart-f74ff147-a49a-4328-a20f-7a6e59912c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230163826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1230163826
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.241446845
Short name T442
Test name
Test status
Simulation time 23949368 ps
CPU time 0.72 seconds
Started Jun 10 05:52:03 PM PDT 24
Finished Jun 10 05:52:04 PM PDT 24
Peak memory 205776 kb
Host smart-7ae38c19-b123-497e-8f08-5a6712048f0c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241446845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.241446845
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.2279473855
Short name T405
Test name
Test status
Simulation time 54444962 ps
CPU time 0.81 seconds
Started Jun 10 05:51:42 PM PDT 24
Finished Jun 10 05:51:43 PM PDT 24
Peak memory 205880 kb
Host smart-f8e4eeb6-d3a5-4324-b88b-7b3aff4f90b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279473855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.2279473855
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.164072119
Short name T773
Test name
Test status
Simulation time 107775251536 ps
CPU time 187.71 seconds
Started Jun 10 05:52:00 PM PDT 24
Finished Jun 10 05:55:08 PM PDT 24
Peak memory 253544 kb
Host smart-44c3e9d0-8ba5-4ad1-b243-e852b70c83d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164072119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.164072119
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.4110091881
Short name T427
Test name
Test status
Simulation time 7768668917 ps
CPU time 84.07 seconds
Started Jun 10 05:52:00 PM PDT 24
Finished Jun 10 05:53:25 PM PDT 24
Peak memory 249356 kb
Host smart-0bf2eea1-7e63-4cda-be30-92537682a3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110091881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.4110091881
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.2489565744
Short name T54
Test name
Test status
Simulation time 77120829848 ps
CPU time 185.87 seconds
Started Jun 10 05:51:52 PM PDT 24
Finished Jun 10 05:54:59 PM PDT 24
Peak memory 256396 kb
Host smart-540ab702-9309-4b80-80b6-9b14bc1e04fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489565744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.2489565744
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.1666573206
Short name T314
Test name
Test status
Simulation time 633217144 ps
CPU time 10.67 seconds
Started Jun 10 05:52:01 PM PDT 24
Finished Jun 10 05:52:12 PM PDT 24
Peak memory 224684 kb
Host smart-bc75ac2c-4907-4429-a90b-e094f1a9bdff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666573206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1666573206
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.1410294280
Short name T399
Test name
Test status
Simulation time 353821868 ps
CPU time 2.61 seconds
Started Jun 10 05:51:50 PM PDT 24
Finished Jun 10 05:51:53 PM PDT 24
Peak memory 233000 kb
Host smart-8bda6c75-6aa0-4f5b-a95e-44274ee222d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410294280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.1410294280
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.541988172
Short name T464
Test name
Test status
Simulation time 25182401298 ps
CPU time 66.5 seconds
Started Jun 10 05:51:55 PM PDT 24
Finished Jun 10 05:53:02 PM PDT 24
Peak memory 233044 kb
Host smart-f38f3be9-8e2c-40aa-99fc-44c9c8e1e9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541988172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.541988172
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2423576362
Short name T500
Test name
Test status
Simulation time 2367103836 ps
CPU time 8.97 seconds
Started Jun 10 05:51:46 PM PDT 24
Finished Jun 10 05:51:55 PM PDT 24
Peak memory 233140 kb
Host smart-4f7f37f0-bcab-4e39-91fe-04004ba932e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423576362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2423576362
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.4074384160
Short name T517
Test name
Test status
Simulation time 1206623258 ps
CPU time 13.48 seconds
Started Jun 10 05:51:57 PM PDT 24
Finished Jun 10 05:52:11 PM PDT 24
Peak memory 222524 kb
Host smart-68b0ed93-1dcc-40af-88a6-c747e889085f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4074384160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.4074384160
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.2398323263
Short name T19
Test name
Test status
Simulation time 34276050647 ps
CPU time 57.54 seconds
Started Jun 10 05:51:47 PM PDT 24
Finished Jun 10 05:52:45 PM PDT 24
Peak memory 250664 kb
Host smart-82d7b5f2-8154-4985-a4fd-959960a7d524
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398323263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.2398323263
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.1920799320
Short name T326
Test name
Test status
Simulation time 5583436633 ps
CPU time 29.9 seconds
Started Jun 10 05:51:53 PM PDT 24
Finished Jun 10 05:52:24 PM PDT 24
Peak memory 220312 kb
Host smart-ecaa29ba-c3b8-4425-961a-9396fc02f3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920799320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1920799320
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.541875376
Short name T373
Test name
Test status
Simulation time 2389644698 ps
CPU time 7.3 seconds
Started Jun 10 05:52:00 PM PDT 24
Finished Jun 10 05:52:08 PM PDT 24
Peak memory 216700 kb
Host smart-ba0603e0-ef42-4df0-833b-b6f840af7207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541875376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.541875376
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.213568412
Short name T27
Test name
Test status
Simulation time 50720406 ps
CPU time 0.88 seconds
Started Jun 10 05:51:45 PM PDT 24
Finished Jun 10 05:51:47 PM PDT 24
Peak memory 206928 kb
Host smart-1d9681a8-74f3-46c1-b565-23bd2a9ba8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213568412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.213568412
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.4174804445
Short name T932
Test name
Test status
Simulation time 182286219 ps
CPU time 1.03 seconds
Started Jun 10 05:51:49 PM PDT 24
Finished Jun 10 05:51:51 PM PDT 24
Peak memory 206556 kb
Host smart-8c0f834d-889d-4fe8-b382-3144020ad606
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4174804445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.4174804445
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.2131840803
Short name T557
Test name
Test status
Simulation time 4768476759 ps
CPU time 7.29 seconds
Started Jun 10 05:51:47 PM PDT 24
Finished Jun 10 05:51:55 PM PDT 24
Peak memory 224868 kb
Host smart-872ecc19-898e-436d-811a-88025d28f27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131840803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.2131840803
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.1976378141
Short name T930
Test name
Test status
Simulation time 50422005 ps
CPU time 0.72 seconds
Started Jun 10 05:52:02 PM PDT 24
Finished Jun 10 05:52:04 PM PDT 24
Peak memory 206096 kb
Host smart-9ca0f7c3-b9b7-47ff-8520-35c90e2c1734
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1976378141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
1976378141
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.875640853
Short name T852
Test name
Test status
Simulation time 30333627 ps
CPU time 2.14 seconds
Started Jun 10 05:51:52 PM PDT 24
Finished Jun 10 05:51:54 PM PDT 24
Peak memory 224188 kb
Host smart-f3f11eca-3ab7-4be2-829e-2995fdbcad3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875640853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.875640853
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.390555736
Short name T815
Test name
Test status
Simulation time 22795728 ps
CPU time 0.78 seconds
Started Jun 10 05:51:55 PM PDT 24
Finished Jun 10 05:51:57 PM PDT 24
Peak memory 206836 kb
Host smart-6cd54efa-fbad-4931-8f0c-77dddee92455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390555736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.390555736
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.3134548747
Short name T219
Test name
Test status
Simulation time 441976692712 ps
CPU time 389.91 seconds
Started Jun 10 05:52:06 PM PDT 24
Finished Jun 10 05:58:37 PM PDT 24
Peak memory 252848 kb
Host smart-28fdf69e-dd02-46d2-8cf0-32a97d3faefc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134548747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.3134548747
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.1195476537
Short name T756
Test name
Test status
Simulation time 34045912367 ps
CPU time 32.15 seconds
Started Jun 10 05:52:01 PM PDT 24
Finished Jun 10 05:52:34 PM PDT 24
Peak memory 250032 kb
Host smart-34fdacd6-73bc-4923-bf70-cb61e6dff738
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195476537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.1195476537
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.989384344
Short name T764
Test name
Test status
Simulation time 44738551281 ps
CPU time 411.52 seconds
Started Jun 10 05:52:01 PM PDT 24
Finished Jun 10 05:58:55 PM PDT 24
Peak memory 257600 kb
Host smart-b2ef3b81-b333-474c-b277-d3d8a7765c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989384344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle
.989384344
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_intercept.4212493221
Short name T928
Test name
Test status
Simulation time 4997669551 ps
CPU time 14.54 seconds
Started Jun 10 05:51:51 PM PDT 24
Finished Jun 10 05:52:06 PM PDT 24
Peak memory 233116 kb
Host smart-587f6fa3-8792-4063-afc5-b3392fd90cb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212493221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.4212493221
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.4231896233
Short name T368
Test name
Test status
Simulation time 6955076478 ps
CPU time 55.83 seconds
Started Jun 10 05:51:49 PM PDT 24
Finished Jun 10 05:52:46 PM PDT 24
Peak memory 233048 kb
Host smart-4071c185-9722-42ba-9b2a-044750c72d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231896233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.4231896233
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.477298331
Short name T41
Test name
Test status
Simulation time 36173379925 ps
CPU time 25.31 seconds
Started Jun 10 05:51:55 PM PDT 24
Finished Jun 10 05:52:21 PM PDT 24
Peak memory 233056 kb
Host smart-ef2970b1-26e4-4a24-9120-9e5ddc6a5b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477298331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap
.477298331
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.2765217310
Short name T700
Test name
Test status
Simulation time 13665465853 ps
CPU time 12.71 seconds
Started Jun 10 05:52:02 PM PDT 24
Finished Jun 10 05:52:15 PM PDT 24
Peak memory 239948 kb
Host smart-c4a60133-7c50-4d22-afe4-8c6154bc4ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765217310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2765217310
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.1092585882
Short name T415
Test name
Test status
Simulation time 488442181 ps
CPU time 9.27 seconds
Started Jun 10 05:51:56 PM PDT 24
Finished Jun 10 05:52:06 PM PDT 24
Peak memory 220460 kb
Host smart-6622c438-baea-4ffb-8bea-718e472d04ea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1092585882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.1092585882
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1220859354
Short name T133
Test name
Test status
Simulation time 113394214619 ps
CPU time 269.94 seconds
Started Jun 10 05:52:05 PM PDT 24
Finished Jun 10 05:56:36 PM PDT 24
Peak memory 255212 kb
Host smart-10608511-7a7d-4e83-bf71-6d7594c14e6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220859354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1220859354
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.443647508
Short name T628
Test name
Test status
Simulation time 272417223 ps
CPU time 2.45 seconds
Started Jun 10 05:51:55 PM PDT 24
Finished Jun 10 05:51:59 PM PDT 24
Peak memory 216552 kb
Host smart-c0e8ebb3-1eff-429e-b8b9-f7be164c38ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=443647508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.443647508
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.711359313
Short name T422
Test name
Test status
Simulation time 1923834346 ps
CPU time 4.85 seconds
Started Jun 10 05:52:02 PM PDT 24
Finished Jun 10 05:52:07 PM PDT 24
Peak memory 216588 kb
Host smart-ea47b07c-767c-4193-9dc5-0d90e905117a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711359313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.711359313
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.3650322427
Short name T750
Test name
Test status
Simulation time 73792969 ps
CPU time 1.25 seconds
Started Jun 10 05:51:55 PM PDT 24
Finished Jun 10 05:51:57 PM PDT 24
Peak memory 216444 kb
Host smart-ff493e9b-b030-4a35-86e3-3b66807befda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650322427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.3650322427
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.485818636
Short name T521
Test name
Test status
Simulation time 20031875 ps
CPU time 0.78 seconds
Started Jun 10 05:51:55 PM PDT 24
Finished Jun 10 05:51:57 PM PDT 24
Peak memory 206108 kb
Host smart-bfcffb07-3677-40d1-a2cb-5c043fa4cae5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485818636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.485818636
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.1074080069
Short name T765
Test name
Test status
Simulation time 60977519 ps
CPU time 2.61 seconds
Started Jun 10 05:51:57 PM PDT 24
Finished Jun 10 05:52:00 PM PDT 24
Peak memory 232684 kb
Host smart-e062c0d7-30d3-4112-b816-b2d7f6d523c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074080069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.1074080069
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.4081198487
Short name T641
Test name
Test status
Simulation time 14703184 ps
CPU time 0.73 seconds
Started Jun 10 05:51:55 PM PDT 24
Finished Jun 10 05:51:57 PM PDT 24
Peak memory 205764 kb
Host smart-ce2d1fc2-4885-478f-9f61-35afe188a480
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081198487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
4081198487
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.695044360
Short name T414
Test name
Test status
Simulation time 598829582 ps
CPU time 8.6 seconds
Started Jun 10 05:51:54 PM PDT 24
Finished Jun 10 05:52:04 PM PDT 24
Peak memory 233024 kb
Host smart-ff8b6bb1-f458-444b-84f7-2657f883f6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695044360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.695044360
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.3447616591
Short name T738
Test name
Test status
Simulation time 63514937 ps
CPU time 0.81 seconds
Started Jun 10 05:52:02 PM PDT 24
Finished Jun 10 05:52:04 PM PDT 24
Peak memory 206888 kb
Host smart-d4c8f524-b711-4d80-b3f2-0e5e5f58de71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447616591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.3447616591
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.2650789906
Short name T795
Test name
Test status
Simulation time 29736942180 ps
CPU time 127.45 seconds
Started Jun 10 05:51:52 PM PDT 24
Finished Jun 10 05:54:00 PM PDT 24
Peak memory 249972 kb
Host smart-c7cce25e-72b7-4eef-a55b-f70462e75c92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650789906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.2650789906
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.2766782286
Short name T276
Test name
Test status
Simulation time 3729254466 ps
CPU time 71.64 seconds
Started Jun 10 05:51:55 PM PDT 24
Finished Jun 10 05:53:08 PM PDT 24
Peak memory 249616 kb
Host smart-00f625ce-67ca-4ad2-a26a-f809e621f780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766782286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.2766782286
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.3104395316
Short name T621
Test name
Test status
Simulation time 51101429 ps
CPU time 3 seconds
Started Jun 10 05:51:55 PM PDT 24
Finished Jun 10 05:51:59 PM PDT 24
Peak memory 232948 kb
Host smart-c805a587-26e1-445f-944d-6e072d86ee3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104395316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.3104395316
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.1838939340
Short name T410
Test name
Test status
Simulation time 622081286 ps
CPU time 6.36 seconds
Started Jun 10 05:51:58 PM PDT 24
Finished Jun 10 05:52:04 PM PDT 24
Peak memory 232920 kb
Host smart-3618be02-823a-4f8a-a8fc-d18177deb264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838939340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.1838939340
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.3920977023
Short name T494
Test name
Test status
Simulation time 44741381709 ps
CPU time 52.2 seconds
Started Jun 10 05:51:56 PM PDT 24
Finished Jun 10 05:52:50 PM PDT 24
Peak memory 224876 kb
Host smart-b02cf676-6aed-4d50-9c41-0f09608fec7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920977023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.3920977023
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.2526510206
Short name T685
Test name
Test status
Simulation time 6423056706 ps
CPU time 18.27 seconds
Started Jun 10 05:52:00 PM PDT 24
Finished Jun 10 05:52:18 PM PDT 24
Peak memory 234172 kb
Host smart-4a137428-1ce0-484c-8f02-a2f11f07bee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526510206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.2526510206
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.998423382
Short name T60
Test name
Test status
Simulation time 19770489150 ps
CPU time 9.46 seconds
Started Jun 10 05:52:02 PM PDT 24
Finished Jun 10 05:52:12 PM PDT 24
Peak memory 233088 kb
Host smart-8f151eb7-75c1-4372-b5a7-1ef8957a4d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=998423382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.998423382
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.2815280453
Short name T438
Test name
Test status
Simulation time 122753403 ps
CPU time 4.16 seconds
Started Jun 10 05:51:47 PM PDT 24
Finished Jun 10 05:51:51 PM PDT 24
Peak memory 223268 kb
Host smart-c6d4800e-b531-4ff3-86b3-1439a5f5b387
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2815280453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.2815280453
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.1407388120
Short name T849
Test name
Test status
Simulation time 14146334 ps
CPU time 0.77 seconds
Started Jun 10 05:52:01 PM PDT 24
Finished Jun 10 05:52:02 PM PDT 24
Peak memory 206004 kb
Host smart-4dbb060e-b2aa-46b7-bfe3-31e10931d327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407388120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.1407388120
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.2915608458
Short name T357
Test name
Test status
Simulation time 2220449312 ps
CPU time 6.83 seconds
Started Jun 10 05:51:48 PM PDT 24
Finished Jun 10 05:51:55 PM PDT 24
Peak memory 216764 kb
Host smart-75ef8fb5-f4a5-4c87-b7f5-2facd08e06fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915608458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.2915608458
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.86916069
Short name T340
Test name
Test status
Simulation time 126542885 ps
CPU time 5.95 seconds
Started Jun 10 05:51:57 PM PDT 24
Finished Jun 10 05:52:03 PM PDT 24
Peak memory 216484 kb
Host smart-3ced9b04-fab1-4fd5-af12-5b91496937c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86916069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.86916069
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.1609680878
Short name T568
Test name
Test status
Simulation time 28317500 ps
CPU time 0.73 seconds
Started Jun 10 05:52:02 PM PDT 24
Finished Jun 10 05:52:03 PM PDT 24
Peak memory 206200 kb
Host smart-736fd0b3-40db-42e0-b6bc-f0effcc05496
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609680878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.1609680878
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.3282945869
Short name T596
Test name
Test status
Simulation time 424868852 ps
CPU time 2.93 seconds
Started Jun 10 05:52:01 PM PDT 24
Finished Jun 10 05:52:05 PM PDT 24
Peak memory 232976 kb
Host smart-112434ad-a62e-4535-ba75-a25623a631f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282945869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.3282945869
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.3089776956
Short name T693
Test name
Test status
Simulation time 12322750 ps
CPU time 0.76 seconds
Started Jun 10 05:50:57 PM PDT 24
Finished Jun 10 05:50:58 PM PDT 24
Peak memory 205176 kb
Host smart-6da3c0cd-504e-4279-8253-0b7a6839ee06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089776956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.3
089776956
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.427069245
Short name T391
Test name
Test status
Simulation time 74901405 ps
CPU time 2.07 seconds
Started Jun 10 05:50:56 PM PDT 24
Finished Jun 10 05:50:58 PM PDT 24
Peak memory 223620 kb
Host smart-7a0a9678-4870-47dc-9eb3-893746a89957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427069245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.427069245
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.2096650926
Short name T125
Test name
Test status
Simulation time 14273181 ps
CPU time 0.74 seconds
Started Jun 10 05:51:07 PM PDT 24
Finished Jun 10 05:51:08 PM PDT 24
Peak memory 206172 kb
Host smart-fe5b6837-9ed4-4c08-8a2b-0d9273f96d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096650926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2096650926
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.3940454766
Short name T768
Test name
Test status
Simulation time 10224480602 ps
CPU time 34.55 seconds
Started Jun 10 05:50:57 PM PDT 24
Finished Jun 10 05:51:32 PM PDT 24
Peak memory 252708 kb
Host smart-45934950-9e84-4937-86cd-32c5eddfd471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940454766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.3940454766
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.2695163488
Short name T35
Test name
Test status
Simulation time 18399833237 ps
CPU time 190.75 seconds
Started Jun 10 05:51:04 PM PDT 24
Finished Jun 10 05:54:16 PM PDT 24
Peak memory 249980 kb
Host smart-b0198155-1787-4872-b394-2c877d043041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695163488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2695163488
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.427230608
Short name T829
Test name
Test status
Simulation time 13405370580 ps
CPU time 69.59 seconds
Started Jun 10 05:51:13 PM PDT 24
Finished Jun 10 05:52:23 PM PDT 24
Peak memory 251092 kb
Host smart-665993ef-af46-4e68-8b58-2aa96c330f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427230608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.
427230608
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.3881797754
Short name T379
Test name
Test status
Simulation time 1960780639 ps
CPU time 25.83 seconds
Started Jun 10 05:50:57 PM PDT 24
Finished Jun 10 05:51:23 PM PDT 24
Peak memory 250908 kb
Host smart-110a3571-c68b-43eb-84fa-64d959c571d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881797754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.3881797754
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.2648910741
Short name T567
Test name
Test status
Simulation time 34909424 ps
CPU time 2.48 seconds
Started Jun 10 05:51:11 PM PDT 24
Finished Jun 10 05:51:13 PM PDT 24
Peak memory 232960 kb
Host smart-69fa5f10-7bd1-46cc-a38d-67bf443247e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648910741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.2648910741
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.53709976
Short name T744
Test name
Test status
Simulation time 962320889 ps
CPU time 15.07 seconds
Started Jun 10 05:50:55 PM PDT 24
Finished Jun 10 05:51:10 PM PDT 24
Peak memory 233064 kb
Host smart-1dba3510-357d-450f-9cff-5c40ec1f44cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53709976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.53709976
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.3317554741
Short name T680
Test name
Test status
Simulation time 4155870314 ps
CPU time 8.38 seconds
Started Jun 10 05:51:03 PM PDT 24
Finished Jun 10 05:51:11 PM PDT 24
Peak memory 233092 kb
Host smart-d3d43b84-45c8-4387-b0f0-b19401227a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3317554741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.3317554741
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.367782464
Short name T776
Test name
Test status
Simulation time 120029322851 ps
CPU time 22.26 seconds
Started Jun 10 05:50:53 PM PDT 24
Finished Jun 10 05:51:16 PM PDT 24
Peak memory 241148 kb
Host smart-5b1a1a39-a084-445b-86ea-a74f755e8d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367782464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.367782464
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.749008257
Short name T92
Test name
Test status
Simulation time 1073973950 ps
CPU time 8.72 seconds
Started Jun 10 05:51:09 PM PDT 24
Finished Jun 10 05:51:18 PM PDT 24
Peak memory 222756 kb
Host smart-76302a88-3552-41b8-b0eb-b4baac9491ab
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=749008257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direc
t.749008257
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.2063930157
Short name T77
Test name
Test status
Simulation time 92807950 ps
CPU time 1.18 seconds
Started Jun 10 05:51:04 PM PDT 24
Finished Jun 10 05:51:06 PM PDT 24
Peak memory 237836 kb
Host smart-ec6f7b3e-a35b-415c-b449-b49a4a243a7e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063930157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2063930157
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.1071855295
Short name T888
Test name
Test status
Simulation time 182362716 ps
CPU time 1.01 seconds
Started Jun 10 05:51:01 PM PDT 24
Finished Jun 10 05:51:02 PM PDT 24
Peak memory 207292 kb
Host smart-b9f1e711-ae79-4cb1-bff3-c7574a33c5af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071855295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.1071855295
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.2675054630
Short name T402
Test name
Test status
Simulation time 4126348179 ps
CPU time 28.32 seconds
Started Jun 10 05:50:53 PM PDT 24
Finished Jun 10 05:51:22 PM PDT 24
Peak memory 216624 kb
Host smart-c3886a2d-2131-43ad-a857-49f1e5c60737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675054630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.2675054630
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.4190571670
Short name T459
Test name
Test status
Simulation time 2690545718 ps
CPU time 6.14 seconds
Started Jun 10 05:51:05 PM PDT 24
Finished Jun 10 05:51:12 PM PDT 24
Peak memory 216696 kb
Host smart-3085a674-4fe2-4c34-9adc-754737d991f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190571670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.4190571670
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2320615994
Short name T772
Test name
Test status
Simulation time 51506319 ps
CPU time 1.62 seconds
Started Jun 10 05:50:53 PM PDT 24
Finished Jun 10 05:50:55 PM PDT 24
Peak memory 216632 kb
Host smart-5027bdd1-6a2c-4b8e-b5ee-83797eb87980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320615994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2320615994
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.4063773069
Short name T520
Test name
Test status
Simulation time 62252122 ps
CPU time 0.74 seconds
Started Jun 10 05:51:12 PM PDT 24
Finished Jun 10 05:51:13 PM PDT 24
Peak memory 206192 kb
Host smart-158e8cfe-ed1d-4b54-afb1-c39d2eef646d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063773069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.4063773069
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.3947311876
Short name T294
Test name
Test status
Simulation time 27258840508 ps
CPU time 12.67 seconds
Started Jun 10 05:50:55 PM PDT 24
Finished Jun 10 05:51:08 PM PDT 24
Peak memory 240320 kb
Host smart-dd0e4abe-120a-4cc9-8b7f-28b712c9be66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947311876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.3947311876
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.549729762
Short name T652
Test name
Test status
Simulation time 21018210 ps
CPU time 0.76 seconds
Started Jun 10 05:51:55 PM PDT 24
Finished Jun 10 05:51:56 PM PDT 24
Peak memory 205760 kb
Host smart-6ba68956-5097-4c5d-9fa4-2ee697970f67
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=549729762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.549729762
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.2192356343
Short name T210
Test name
Test status
Simulation time 1027943631 ps
CPU time 3.82 seconds
Started Jun 10 05:52:06 PM PDT 24
Finished Jun 10 05:52:10 PM PDT 24
Peak memory 232988 kb
Host smart-a062598b-125f-47e8-8d36-9f7212430179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192356343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.2192356343
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.1664557633
Short name T819
Test name
Test status
Simulation time 77288862 ps
CPU time 0.8 seconds
Started Jun 10 05:51:55 PM PDT 24
Finished Jun 10 05:51:57 PM PDT 24
Peak memory 206924 kb
Host smart-2cb065cf-7dac-4c57-9ed1-d7ffe760726d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664557633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1664557633
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.2863964114
Short name T271
Test name
Test status
Simulation time 6351278090 ps
CPU time 58 seconds
Started Jun 10 05:52:00 PM PDT 24
Finished Jun 10 05:52:58 PM PDT 24
Peak memory 253068 kb
Host smart-786b5ae6-6fd0-47ec-97fe-e0a616058209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863964114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.2863964114
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.3386131438
Short name T923
Test name
Test status
Simulation time 190909049690 ps
CPU time 439.68 seconds
Started Jun 10 05:51:57 PM PDT 24
Finished Jun 10 05:59:17 PM PDT 24
Peak memory 251660 kb
Host smart-1ba9f66b-584b-42f8-906e-e2cc7e18f760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386131438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.3386131438
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.2655229007
Short name T345
Test name
Test status
Simulation time 39048567799 ps
CPU time 77.12 seconds
Started Jun 10 05:51:55 PM PDT 24
Finished Jun 10 05:53:13 PM PDT 24
Peak memory 234216 kb
Host smart-24c70bb3-ee4d-4232-97f1-35a76702d4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655229007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2655229007
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.778746839
Short name T820
Test name
Test status
Simulation time 7309712077 ps
CPU time 24.18 seconds
Started Jun 10 05:51:57 PM PDT 24
Finished Jun 10 05:52:22 PM PDT 24
Peak memory 224892 kb
Host smart-0a8edff6-8297-48f7-a0ab-ef7f43520c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778746839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.778746839
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.1864028260
Short name T880
Test name
Test status
Simulation time 5421426046 ps
CPU time 51.92 seconds
Started Jun 10 05:52:03 PM PDT 24
Finished Jun 10 05:52:56 PM PDT 24
Peak memory 241280 kb
Host smart-e686d180-ee5a-45c0-90ce-04b445436bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864028260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.1864028260
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1999321934
Short name T79
Test name
Test status
Simulation time 2769957664 ps
CPU time 4.43 seconds
Started Jun 10 05:51:53 PM PDT 24
Finished Jun 10 05:51:58 PM PDT 24
Peak memory 233168 kb
Host smart-060f6a95-647f-4fa7-9772-6f047fc97475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999321934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1999321934
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.47732148
Short name T469
Test name
Test status
Simulation time 304085843 ps
CPU time 4.84 seconds
Started Jun 10 05:51:54 PM PDT 24
Finished Jun 10 05:52:00 PM PDT 24
Peak memory 239968 kb
Host smart-9263bc4b-370f-4bef-8c39-014dc760a4ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47732148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.47732148
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.3165513999
Short name T642
Test name
Test status
Simulation time 170843971 ps
CPU time 3.82 seconds
Started Jun 10 05:52:00 PM PDT 24
Finished Jun 10 05:52:04 PM PDT 24
Peak memory 220668 kb
Host smart-93d541b7-63d4-4d7d-9d2a-2e1febd3667a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3165513999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.3165513999
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.3569233394
Short name T154
Test name
Test status
Simulation time 16660542989 ps
CPU time 41.63 seconds
Started Jun 10 05:52:06 PM PDT 24
Finished Jun 10 05:52:49 PM PDT 24
Peak memory 218144 kb
Host smart-b6aa78f3-7bc8-418c-8d11-621159b7c32f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569233394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.3569233394
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.3221807574
Short name T321
Test name
Test status
Simulation time 41637664436 ps
CPU time 54 seconds
Started Jun 10 05:51:56 PM PDT 24
Finished Jun 10 05:52:51 PM PDT 24
Peak memory 216684 kb
Host smart-b695e2f7-594f-452b-9310-cf92fdd9adfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221807574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3221807574
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.168068089
Short name T497
Test name
Test status
Simulation time 21412162320 ps
CPU time 9.16 seconds
Started Jun 10 05:51:55 PM PDT 24
Finished Jun 10 05:52:05 PM PDT 24
Peak memory 216672 kb
Host smart-e0e2491f-7edb-45a0-a92d-40ccc160ac00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168068089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.168068089
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.1782359543
Short name T446
Test name
Test status
Simulation time 36517089 ps
CPU time 1.43 seconds
Started Jun 10 05:51:55 PM PDT 24
Finished Jun 10 05:51:58 PM PDT 24
Peak memory 216640 kb
Host smart-6f8f5d14-8940-40ac-8d8c-e901a6c02375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782359543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1782359543
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.1364814393
Short name T435
Test name
Test status
Simulation time 88688860 ps
CPU time 1.02 seconds
Started Jun 10 05:51:55 PM PDT 24
Finished Jun 10 05:51:56 PM PDT 24
Peak memory 206200 kb
Host smart-20848f11-80d4-4b9f-9296-fce531f874ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364814393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.1364814393
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.362534725
Short name T418
Test name
Test status
Simulation time 565544353 ps
CPU time 5.2 seconds
Started Jun 10 05:51:57 PM PDT 24
Finished Jun 10 05:52:03 PM PDT 24
Peak memory 232076 kb
Host smart-a8223e5a-ffbf-43d3-880f-13ad6901b4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362534725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.362534725
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3231758365
Short name T453
Test name
Test status
Simulation time 46121987 ps
CPU time 0.75 seconds
Started Jun 10 05:52:04 PM PDT 24
Finished Jun 10 05:52:05 PM PDT 24
Peak memory 206008 kb
Host smart-18ee4f5f-4525-416d-b4ed-3a0dce3e5954
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231758365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3231758365
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.1832616749
Short name T560
Test name
Test status
Simulation time 62622779 ps
CPU time 0.76 seconds
Started Jun 10 05:51:54 PM PDT 24
Finished Jun 10 05:51:56 PM PDT 24
Peak memory 205876 kb
Host smart-cb181311-ca1c-4a6a-8551-59a6b1cc3203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832616749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.1832616749
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.2580420237
Short name T735
Test name
Test status
Simulation time 4180226135 ps
CPU time 19.03 seconds
Started Jun 10 05:51:59 PM PDT 24
Finished Jun 10 05:52:19 PM PDT 24
Peak memory 224860 kb
Host smart-d20d50fb-f5e5-4a36-9c6d-b66e893d39e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580420237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.2580420237
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.2319435324
Short name T57
Test name
Test status
Simulation time 47805116628 ps
CPU time 259.46 seconds
Started Jun 10 05:52:05 PM PDT 24
Finished Jun 10 05:56:24 PM PDT 24
Peak memory 266656 kb
Host smart-56a62aa9-8936-47c5-9309-eb3027e9ca25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319435324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.2319435324
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.4139669653
Short name T186
Test name
Test status
Simulation time 90077458285 ps
CPU time 465.51 seconds
Started Jun 10 05:52:01 PM PDT 24
Finished Jun 10 05:59:47 PM PDT 24
Peak memory 256804 kb
Host smart-79ab10df-9758-420a-9c97-99de0a8e55d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139669653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.4139669653
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.1380328100
Short name T526
Test name
Test status
Simulation time 1603260362 ps
CPU time 24.9 seconds
Started Jun 10 05:52:03 PM PDT 24
Finished Jun 10 05:52:28 PM PDT 24
Peak memory 232992 kb
Host smart-3e46e995-0883-4a2f-9713-b22d4ac96bd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380328100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.1380328100
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.1076496558
Short name T860
Test name
Test status
Simulation time 975802672 ps
CPU time 7.38 seconds
Started Jun 10 05:52:04 PM PDT 24
Finished Jun 10 05:52:11 PM PDT 24
Peak memory 224728 kb
Host smart-1da1dc52-cc03-4163-a549-ef2d5ef51ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076496558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1076496558
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.2244213717
Short name T633
Test name
Test status
Simulation time 7051528349 ps
CPU time 11.72 seconds
Started Jun 10 05:51:57 PM PDT 24
Finished Jun 10 05:52:09 PM PDT 24
Peak memory 224884 kb
Host smart-73d51b59-4894-44de-87db-ff75e87a86be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244213717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2244213717
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2883479386
Short name T847
Test name
Test status
Simulation time 1996399012 ps
CPU time 8.52 seconds
Started Jun 10 05:52:01 PM PDT 24
Finished Jun 10 05:52:10 PM PDT 24
Peak memory 218980 kb
Host smart-5c50033c-14e2-4509-89cf-3bf1bf312eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883479386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2883479386
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.2016397305
Short name T856
Test name
Test status
Simulation time 9163617643 ps
CPU time 11.65 seconds
Started Jun 10 05:52:06 PM PDT 24
Finished Jun 10 05:52:18 PM PDT 24
Peak memory 224876 kb
Host smart-5a47f22d-6670-43d6-85f4-1a1dd0cb39f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016397305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.2016397305
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.611806936
Short name T723
Test name
Test status
Simulation time 237100005 ps
CPU time 4.94 seconds
Started Jun 10 05:52:05 PM PDT 24
Finished Jun 10 05:52:10 PM PDT 24
Peak memory 223344 kb
Host smart-4eaa91bd-6a18-4902-bc78-9f36c0900d47
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=611806936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dire
ct.611806936
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.3541788068
Short name T31
Test name
Test status
Simulation time 1116065017 ps
CPU time 11.81 seconds
Started Jun 10 05:52:10 PM PDT 24
Finished Jun 10 05:52:22 PM PDT 24
Peak memory 224752 kb
Host smart-8ff1534e-d3b9-45a6-96cd-62c077bd2c55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541788068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.3541788068
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.1958785660
Short name T48
Test name
Test status
Simulation time 827220959 ps
CPU time 5.35 seconds
Started Jun 10 05:52:06 PM PDT 24
Finished Jun 10 05:52:12 PM PDT 24
Peak memory 216868 kb
Host smart-828bd275-1393-462d-909e-dc3dcb8c2f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958785660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.1958785660
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3733796270
Short name T913
Test name
Test status
Simulation time 3652238409 ps
CPU time 3.24 seconds
Started Jun 10 05:52:06 PM PDT 24
Finished Jun 10 05:52:10 PM PDT 24
Peak memory 216688 kb
Host smart-79bc5ac5-c42e-4b86-b70b-730069fc5358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733796270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3733796270
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.2253801812
Short name T841
Test name
Test status
Simulation time 56620267 ps
CPU time 1.24 seconds
Started Jun 10 05:52:01 PM PDT 24
Finished Jun 10 05:52:04 PM PDT 24
Peak memory 208100 kb
Host smart-f139abad-c6ef-4074-b167-946e577b6795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253801812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2253801812
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.912468682
Short name T823
Test name
Test status
Simulation time 178116889 ps
CPU time 0.8 seconds
Started Jun 10 05:51:56 PM PDT 24
Finished Jun 10 05:51:57 PM PDT 24
Peak memory 206216 kb
Host smart-13194754-cfd0-4813-8559-e4fe4427d299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912468682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.912468682
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.2353434309
Short name T914
Test name
Test status
Simulation time 1304071097 ps
CPU time 6.5 seconds
Started Jun 10 05:52:04 PM PDT 24
Finished Jun 10 05:52:11 PM PDT 24
Peak memory 224672 kb
Host smart-8547caf5-6e6a-4979-bc8d-b7ad7560293b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353434309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.2353434309
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.663962252
Short name T67
Test name
Test status
Simulation time 21926081 ps
CPU time 0.7 seconds
Started Jun 10 05:52:05 PM PDT 24
Finished Jun 10 05:52:06 PM PDT 24
Peak memory 205756 kb
Host smart-87905ab2-dbfe-46c3-a8ba-d3328b8e7591
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=663962252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.663962252
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.2365322495
Short name T93
Test name
Test status
Simulation time 905468973 ps
CPU time 9.21 seconds
Started Jun 10 05:51:56 PM PDT 24
Finished Jun 10 05:52:06 PM PDT 24
Peak memory 233048 kb
Host smart-c04b678e-bcb9-482e-b5fb-a6b2b58b638a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365322495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2365322495
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.1153940026
Short name T758
Test name
Test status
Simulation time 62904931 ps
CPU time 0.74 seconds
Started Jun 10 05:52:03 PM PDT 24
Finished Jun 10 05:52:05 PM PDT 24
Peak memory 205856 kb
Host smart-03df21cf-a321-4758-b158-53c0c6af039d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153940026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1153940026
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.1521118772
Short name T301
Test name
Test status
Simulation time 566177623 ps
CPU time 6.03 seconds
Started Jun 10 05:52:00 PM PDT 24
Finished Jun 10 05:52:06 PM PDT 24
Peak memory 224784 kb
Host smart-7dd57ee4-125e-4f95-a4a9-7b0f9867e0db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521118772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.1521118772
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.1324423062
Short name T806
Test name
Test status
Simulation time 1650276077 ps
CPU time 41.55 seconds
Started Jun 10 05:51:58 PM PDT 24
Finished Jun 10 05:52:40 PM PDT 24
Peak memory 249448 kb
Host smart-2028c63b-7d99-45c4-9f51-d12367998c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324423062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.1324423062
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.917379517
Short name T244
Test name
Test status
Simulation time 17608133565 ps
CPU time 93.5 seconds
Started Jun 10 05:52:05 PM PDT 24
Finished Jun 10 05:53:39 PM PDT 24
Peak memory 249584 kb
Host smart-f9dc840b-8c9f-451e-9d0a-3706ef6fbfca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917379517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle
.917379517
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.3494211871
Short name T140
Test name
Test status
Simulation time 1116737994 ps
CPU time 7.58 seconds
Started Jun 10 05:51:59 PM PDT 24
Finished Jun 10 05:52:07 PM PDT 24
Peak memory 237416 kb
Host smart-d9a6dd33-ea94-4890-82a5-d3e63c61e0cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494211871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.3494211871
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.1229993536
Short name T255
Test name
Test status
Simulation time 273481205 ps
CPU time 3.01 seconds
Started Jun 10 05:52:01 PM PDT 24
Finished Jun 10 05:52:04 PM PDT 24
Peak memory 224756 kb
Host smart-7d9266d5-4df7-4bbd-9649-7cb3c9bca015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229993536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.1229993536
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.2506568392
Short name T747
Test name
Test status
Simulation time 12962600450 ps
CPU time 31.22 seconds
Started Jun 10 05:52:01 PM PDT 24
Finished Jun 10 05:52:33 PM PDT 24
Peak memory 233016 kb
Host smart-0e8af91b-fa55-4703-8ee5-1afb5bcaa148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506568392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.2506568392
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.4218076347
Short name T223
Test name
Test status
Simulation time 5183138887 ps
CPU time 8.3 seconds
Started Jun 10 05:52:06 PM PDT 24
Finished Jun 10 05:52:15 PM PDT 24
Peak memory 233108 kb
Host smart-f4c9185e-07ba-4d75-9294-7103d5d64114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218076347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.4218076347
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.550627191
Short name T908
Test name
Test status
Simulation time 115660963 ps
CPU time 4 seconds
Started Jun 10 05:52:23 PM PDT 24
Finished Jun 10 05:52:28 PM PDT 24
Peak memory 241192 kb
Host smart-a30b89c8-b02f-405b-abe4-daab4c1cd245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550627191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.550627191
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.982900732
Short name T561
Test name
Test status
Simulation time 863246979 ps
CPU time 3.77 seconds
Started Jun 10 05:52:05 PM PDT 24
Finished Jun 10 05:52:09 PM PDT 24
Peak memory 222876 kb
Host smart-35c67d46-2a4b-4e9d-9d7a-a68c2353e48c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=982900732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dire
ct.982900732
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.456862400
Short name T270
Test name
Test status
Simulation time 4826589067 ps
CPU time 76.55 seconds
Started Jun 10 05:52:06 PM PDT 24
Finished Jun 10 05:53:23 PM PDT 24
Peak memory 251788 kb
Host smart-b40cc004-224c-41f0-986e-0daab1b6792c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456862400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stres
s_all.456862400
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.188417297
Short name T444
Test name
Test status
Simulation time 2636849309 ps
CPU time 17.79 seconds
Started Jun 10 05:52:01 PM PDT 24
Finished Jun 10 05:52:19 PM PDT 24
Peak memory 216704 kb
Host smart-eb7e3211-7c9f-4c98-bd9b-94c19d4ba4fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188417297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.188417297
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.3493038394
Short name T360
Test name
Test status
Simulation time 7585074456 ps
CPU time 20.7 seconds
Started Jun 10 05:51:59 PM PDT 24
Finished Jun 10 05:52:21 PM PDT 24
Peak memory 216688 kb
Host smart-b23d5268-bc9c-4d10-98bd-943325e7fba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493038394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3493038394
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.2288066816
Short name T430
Test name
Test status
Simulation time 407811139 ps
CPU time 2.57 seconds
Started Jun 10 05:52:04 PM PDT 24
Finished Jun 10 05:52:07 PM PDT 24
Peak memory 216632 kb
Host smart-594d2720-3874-4aed-905d-d6ca40e3cc7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288066816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2288066816
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2230269435
Short name T947
Test name
Test status
Simulation time 18528503 ps
CPU time 0.73 seconds
Started Jun 10 05:52:03 PM PDT 24
Finished Jun 10 05:52:04 PM PDT 24
Peak memory 205916 kb
Host smart-2468b98f-d650-480d-8aac-aa6a1c391e32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230269435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2230269435
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.93399925
Short name T12
Test name
Test status
Simulation time 479154387 ps
CPU time 3.21 seconds
Started Jun 10 05:52:06 PM PDT 24
Finished Jun 10 05:52:10 PM PDT 24
Peak memory 219240 kb
Host smart-a3acded3-e04a-47f9-a46e-9b839a281fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93399925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.93399925
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.503385182
Short name T417
Test name
Test status
Simulation time 21034015 ps
CPU time 0.74 seconds
Started Jun 10 05:52:11 PM PDT 24
Finished Jun 10 05:52:12 PM PDT 24
Peak memory 205756 kb
Host smart-db14380b-cc78-44b9-a9c4-539e22a42aed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=503385182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.503385182
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.3368528100
Short name T252
Test name
Test status
Simulation time 4788244019 ps
CPU time 12.22 seconds
Started Jun 10 05:52:06 PM PDT 24
Finished Jun 10 05:52:19 PM PDT 24
Peak memory 233104 kb
Host smart-c7ed2b1e-f83f-4595-9a9c-0886e5b5330b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368528100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.3368528100
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.945483099
Short name T911
Test name
Test status
Simulation time 19119985 ps
CPU time 0.81 seconds
Started Jun 10 05:52:07 PM PDT 24
Finished Jun 10 05:52:09 PM PDT 24
Peak memory 207232 kb
Host smart-847223e0-ac81-43d2-8ab4-b592c161195d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945483099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.945483099
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.3501094438
Short name T224
Test name
Test status
Simulation time 28118858347 ps
CPU time 97.55 seconds
Started Jun 10 05:52:07 PM PDT 24
Finished Jun 10 05:53:45 PM PDT 24
Peak memory 239008 kb
Host smart-d5a23235-2138-45ac-a1ed-812eb63af19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501094438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.3501094438
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.3888346404
Short name T431
Test name
Test status
Simulation time 9041186652 ps
CPU time 51.58 seconds
Started Jun 10 05:52:04 PM PDT 24
Finished Jun 10 05:52:56 PM PDT 24
Peak memory 253092 kb
Host smart-dbfcd415-8e15-48da-b050-f63ee617fac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888346404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3888346404
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.2222537299
Short name T55
Test name
Test status
Simulation time 8070689121 ps
CPU time 63.41 seconds
Started Jun 10 05:52:06 PM PDT 24
Finished Jun 10 05:53:10 PM PDT 24
Peak memory 257604 kb
Host smart-dab3dcc4-acc4-4881-a8c7-601389306359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222537299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.2222537299
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.3430790771
Short name T472
Test name
Test status
Simulation time 408367808 ps
CPU time 14.39 seconds
Started Jun 10 05:52:07 PM PDT 24
Finished Jun 10 05:52:22 PM PDT 24
Peak memory 249920 kb
Host smart-34e77c26-8334-4624-91d7-a9a761c6f803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430790771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.3430790771
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.1547924334
Short name T956
Test name
Test status
Simulation time 1928802163 ps
CPU time 19.34 seconds
Started Jun 10 05:52:02 PM PDT 24
Finished Jun 10 05:52:22 PM PDT 24
Peak memory 224764 kb
Host smart-2994e0e6-16fd-4a5d-a49c-dd7626d2507c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547924334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1547924334
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.4067392212
Short name T797
Test name
Test status
Simulation time 17098488976 ps
CPU time 65.88 seconds
Started Jun 10 05:52:08 PM PDT 24
Finished Jun 10 05:53:14 PM PDT 24
Peak memory 241016 kb
Host smart-f37edcfd-1393-44ef-9e77-9e2d71f7af67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067392212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.4067392212
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.943632141
Short name T293
Test name
Test status
Simulation time 6402819213 ps
CPU time 20.06 seconds
Started Jun 10 05:52:02 PM PDT 24
Finished Jun 10 05:52:23 PM PDT 24
Peak memory 241332 kb
Host smart-f837115f-51d6-4de1-a5b4-c531a69a2fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943632141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.943632141
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.2563113720
Short name T851
Test name
Test status
Simulation time 1976021621 ps
CPU time 11.8 seconds
Started Jun 10 05:52:04 PM PDT 24
Finished Jun 10 05:52:16 PM PDT 24
Peak memory 221268 kb
Host smart-03013424-bd45-48a1-98c9-86f41346c8d9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2563113720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.2563113720
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.580986936
Short name T783
Test name
Test status
Simulation time 82627647 ps
CPU time 1.04 seconds
Started Jun 10 05:52:05 PM PDT 24
Finished Jun 10 05:52:06 PM PDT 24
Peak memory 207180 kb
Host smart-566649a5-d478-456b-8d8e-fb3ce01df48f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580986936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stres
s_all.580986936
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.931391026
Short name T316
Test name
Test status
Simulation time 2061188620 ps
CPU time 9.14 seconds
Started Jun 10 05:52:05 PM PDT 24
Finished Jun 10 05:52:15 PM PDT 24
Peak memory 216568 kb
Host smart-778c27fb-c000-4658-a0e9-ce47f4049a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931391026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.931391026
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1103291018
Short name T563
Test name
Test status
Simulation time 702540946 ps
CPU time 5.19 seconds
Started Jun 10 05:52:06 PM PDT 24
Finished Jun 10 05:52:11 PM PDT 24
Peak memory 216612 kb
Host smart-aad3fdbc-1d32-444a-9e87-65f20649bf14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103291018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1103291018
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.3267519060
Short name T325
Test name
Test status
Simulation time 176715063 ps
CPU time 1.81 seconds
Started Jun 10 05:52:05 PM PDT 24
Finished Jun 10 05:52:07 PM PDT 24
Peak memory 216584 kb
Host smart-5186f257-03b9-4a9a-bae8-021eea31072f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267519060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3267519060
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.4075858482
Short name T864
Test name
Test status
Simulation time 23206229 ps
CPU time 0.72 seconds
Started Jun 10 05:52:03 PM PDT 24
Finished Jun 10 05:52:04 PM PDT 24
Peak memory 206200 kb
Host smart-789d0865-bc68-454c-bdb4-9c30e4424311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075858482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.4075858482
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.242992228
Short name T649
Test name
Test status
Simulation time 73502395 ps
CPU time 2.25 seconds
Started Jun 10 05:52:07 PM PDT 24
Finished Jun 10 05:52:10 PM PDT 24
Peak memory 233028 kb
Host smart-129e7bbf-f8df-4b54-827a-0b819b8f8b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242992228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.242992228
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.2334734428
Short name T347
Test name
Test status
Simulation time 42635994 ps
CPU time 0.7 seconds
Started Jun 10 05:52:09 PM PDT 24
Finished Jun 10 05:52:10 PM PDT 24
Peak memory 206084 kb
Host smart-dc3fa962-4e9c-4789-8367-974af7e4868a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334734428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
2334734428
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.2027051576
Short name T687
Test name
Test status
Simulation time 1023183079 ps
CPU time 11.57 seconds
Started Jun 10 05:52:04 PM PDT 24
Finished Jun 10 05:52:16 PM PDT 24
Peak memory 224844 kb
Host smart-23ef101c-bebb-46e6-b2ff-413475243047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027051576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2027051576
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.392580196
Short name T512
Test name
Test status
Simulation time 66609208 ps
CPU time 0.81 seconds
Started Jun 10 05:52:07 PM PDT 24
Finished Jun 10 05:52:09 PM PDT 24
Peak memory 206904 kb
Host smart-0b81ac02-f843-47bb-b4d1-61b04e475f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392580196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.392580196
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.1371740981
Short name T221
Test name
Test status
Simulation time 4729412203 ps
CPU time 54.13 seconds
Started Jun 10 05:52:11 PM PDT 24
Finished Jun 10 05:53:05 PM PDT 24
Peak memory 255308 kb
Host smart-cc3f1846-150d-4ecb-9c16-c9b85512190d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371740981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.1371740981
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.4018193271
Short name T322
Test name
Test status
Simulation time 8702213943 ps
CPU time 31.06 seconds
Started Jun 10 05:52:09 PM PDT 24
Finished Jun 10 05:52:40 PM PDT 24
Peak memory 248928 kb
Host smart-7afce128-546c-4c38-83b8-f236ec8a3806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018193271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.4018193271
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.1338937472
Short name T235
Test name
Test status
Simulation time 74326889723 ps
CPU time 221.23 seconds
Started Jun 10 05:52:08 PM PDT 24
Finished Jun 10 05:55:50 PM PDT 24
Peak memory 259972 kb
Host smart-1a48e1f4-a709-4df7-b6f9-102b07de66b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338937472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.1338937472
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.2505148098
Short name T309
Test name
Test status
Simulation time 1227959097 ps
CPU time 6.92 seconds
Started Jun 10 05:52:09 PM PDT 24
Finished Jun 10 05:52:16 PM PDT 24
Peak memory 234124 kb
Host smart-f2667ef2-94f6-415f-9568-70699e316fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505148098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2505148098
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.1451508971
Short name T525
Test name
Test status
Simulation time 3037287843 ps
CPU time 26.07 seconds
Started Jun 10 05:52:05 PM PDT 24
Finished Jun 10 05:52:32 PM PDT 24
Peak memory 233124 kb
Host smart-7e107472-442f-4c33-a1df-8dcbab02ca37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451508971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.1451508971
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.955145749
Short name T261
Test name
Test status
Simulation time 18531366572 ps
CPU time 27.48 seconds
Started Jun 10 05:52:07 PM PDT 24
Finished Jun 10 05:52:35 PM PDT 24
Peak memory 241348 kb
Host smart-cf19f822-df50-47f1-bea9-e3f020323bb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955145749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.955145749
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.2421476823
Short name T214
Test name
Test status
Simulation time 3660529179 ps
CPU time 4.02 seconds
Started Jun 10 05:52:15 PM PDT 24
Finished Jun 10 05:52:19 PM PDT 24
Peak memory 224952 kb
Host smart-037b802d-36e4-4dfb-bc43-a841e69f76f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421476823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.2421476823
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.3236956783
Short name T830
Test name
Test status
Simulation time 12582859296 ps
CPU time 10.18 seconds
Started Jun 10 05:52:09 PM PDT 24
Finished Jun 10 05:52:19 PM PDT 24
Peak memory 224944 kb
Host smart-313f16fa-848e-465a-829c-5176ec512c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236956783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3236956783
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.1439393052
Short name T361
Test name
Test status
Simulation time 2384137835 ps
CPU time 7.05 seconds
Started Jun 10 05:52:12 PM PDT 24
Finished Jun 10 05:52:20 PM PDT 24
Peak memory 220940 kb
Host smart-8cf78b09-7f46-48a4-abc1-203bdb1906db
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1439393052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.1439393052
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.2573594088
Short name T766
Test name
Test status
Simulation time 29673922787 ps
CPU time 221 seconds
Started Jun 10 05:52:16 PM PDT 24
Finished Jun 10 05:55:58 PM PDT 24
Peak memory 265392 kb
Host smart-dc973f8c-5328-44c8-8c28-f8ef5f32d7f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573594088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.2573594088
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.2847837417
Short name T385
Test name
Test status
Simulation time 998391418 ps
CPU time 3.69 seconds
Started Jun 10 05:52:18 PM PDT 24
Finished Jun 10 05:52:23 PM PDT 24
Peak memory 216592 kb
Host smart-fcebf588-fbf0-4edf-a058-47ab2df0cde1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847837417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.2847837417
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1156015055
Short name T2
Test name
Test status
Simulation time 356332432 ps
CPU time 3.47 seconds
Started Jun 10 05:52:02 PM PDT 24
Finished Jun 10 05:52:06 PM PDT 24
Peak memory 216608 kb
Host smart-69e5b57a-5a00-4d37-8ca1-05faccc080fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156015055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1156015055
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.3779177971
Short name T456
Test name
Test status
Simulation time 53019410 ps
CPU time 1.46 seconds
Started Jun 10 05:52:01 PM PDT 24
Finished Jun 10 05:52:02 PM PDT 24
Peak memory 216560 kb
Host smart-6fc9834a-731e-42d9-a148-e48e21d48ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779177971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.3779177971
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.3704175272
Short name T336
Test name
Test status
Simulation time 56455411 ps
CPU time 0.86 seconds
Started Jun 10 05:52:04 PM PDT 24
Finished Jun 10 05:52:06 PM PDT 24
Peak memory 206252 kb
Host smart-e3273bfd-258c-4017-8472-1cc260bab50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704175272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.3704175272
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.2413659116
Short name T537
Test name
Test status
Simulation time 179735440 ps
CPU time 2.72 seconds
Started Jun 10 05:52:10 PM PDT 24
Finished Jun 10 05:52:13 PM PDT 24
Peak memory 232772 kb
Host smart-3b2265bf-0024-4793-b64e-76786d79c3c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413659116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.2413659116
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.1865615023
Short name T493
Test name
Test status
Simulation time 11491401 ps
CPU time 0.71 seconds
Started Jun 10 05:52:20 PM PDT 24
Finished Jun 10 05:52:21 PM PDT 24
Peak memory 205180 kb
Host smart-d7094088-dec6-4e70-8d33-4e2e690e7f1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865615023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
1865615023
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.2411038564
Short name T91
Test name
Test status
Simulation time 1562777319 ps
CPU time 12.13 seconds
Started Jun 10 05:52:09 PM PDT 24
Finished Jun 10 05:52:22 PM PDT 24
Peak memory 224760 kb
Host smart-b480bc71-5c3e-4dbf-9218-5d94ec624666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411038564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.2411038564
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.3785097391
Short name T515
Test name
Test status
Simulation time 40955374 ps
CPU time 0.8 seconds
Started Jun 10 05:52:09 PM PDT 24
Finished Jun 10 05:52:10 PM PDT 24
Peak memory 205884 kb
Host smart-82cd6b8a-f89f-4f37-9156-c59775f41d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785097391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.3785097391
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.1229305125
Short name T258
Test name
Test status
Simulation time 3007237138 ps
CPU time 52.67 seconds
Started Jun 10 05:52:18 PM PDT 24
Finished Jun 10 05:53:11 PM PDT 24
Peak memory 257672 kb
Host smart-ae4c9dfe-e33f-4fa1-acac-0bcba350fc2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229305125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.1229305125
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.3955609998
Short name T161
Test name
Test status
Simulation time 11385623497 ps
CPU time 108.66 seconds
Started Jun 10 05:52:14 PM PDT 24
Finished Jun 10 05:54:03 PM PDT 24
Peak memory 239144 kb
Host smart-82354b7a-9d87-4857-a2c7-c6bca232f06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955609998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.3955609998
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.2085672842
Short name T507
Test name
Test status
Simulation time 107545187768 ps
CPU time 267.66 seconds
Started Jun 10 05:52:12 PM PDT 24
Finished Jun 10 05:56:40 PM PDT 24
Peak memory 251788 kb
Host smart-0d628130-511f-47b5-8af6-ed8f347fc914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085672842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.2085672842
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.1259841432
Short name T465
Test name
Test status
Simulation time 4110582176 ps
CPU time 18.64 seconds
Started Jun 10 05:52:28 PM PDT 24
Finished Jun 10 05:52:47 PM PDT 24
Peak memory 233144 kb
Host smart-c99cfd37-827f-4637-a5f8-5f97176296ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259841432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.1259841432
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.3064695018
Short name T528
Test name
Test status
Simulation time 35594676 ps
CPU time 2.61 seconds
Started Jun 10 05:52:05 PM PDT 24
Finished Jun 10 05:52:08 PM PDT 24
Peak memory 233040 kb
Host smart-c0d0529f-a8e9-4ffd-8934-fd651a65fe31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064695018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.3064695018
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.2114697268
Short name T534
Test name
Test status
Simulation time 36583660680 ps
CPU time 37.46 seconds
Started Jun 10 05:52:09 PM PDT 24
Finished Jun 10 05:52:47 PM PDT 24
Peak memory 233080 kb
Host smart-0c823336-1929-411e-8b18-453e1ca7ab45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114697268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.2114697268
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.372043962
Short name T14
Test name
Test status
Simulation time 23333184299 ps
CPU time 11.74 seconds
Started Jun 10 05:52:19 PM PDT 24
Finished Jun 10 05:52:31 PM PDT 24
Peak memory 224864 kb
Host smart-a851e091-c5cd-46c3-b7df-6e69354575b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372043962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap
.372043962
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.2166116111
Short name T197
Test name
Test status
Simulation time 54646051028 ps
CPU time 20.95 seconds
Started Jun 10 05:52:11 PM PDT 24
Finished Jun 10 05:52:32 PM PDT 24
Peak memory 241160 kb
Host smart-0af03417-30ce-44dc-908e-b3200264421d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166116111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2166116111
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.125084077
Short name T918
Test name
Test status
Simulation time 988554879 ps
CPU time 5.93 seconds
Started Jun 10 05:52:15 PM PDT 24
Finished Jun 10 05:52:21 PM PDT 24
Peak memory 223424 kb
Host smart-c1645ba0-e583-46e2-8ac8-576d6d541cde
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=125084077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dire
ct.125084077
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.2012912760
Short name T32
Test name
Test status
Simulation time 38510636 ps
CPU time 1.03 seconds
Started Jun 10 05:52:16 PM PDT 24
Finished Jun 10 05:52:18 PM PDT 24
Peak memory 207056 kb
Host smart-5def3ad3-b3fb-4bd8-8d58-2742ab66066e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012912760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.2012912760
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.2478835531
Short name T899
Test name
Test status
Simulation time 663094582 ps
CPU time 9.34 seconds
Started Jun 10 05:52:09 PM PDT 24
Finished Jun 10 05:52:18 PM PDT 24
Peak memory 219416 kb
Host smart-564cc5f5-ee31-46a2-9f12-c0ae2d00d0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478835531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2478835531
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.2911833276
Short name T529
Test name
Test status
Simulation time 26888850068 ps
CPU time 13.29 seconds
Started Jun 10 05:52:12 PM PDT 24
Finished Jun 10 05:52:25 PM PDT 24
Peak memory 216764 kb
Host smart-a8ba2f6c-c796-4c00-8f7b-273d79ab8ae7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911833276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.2911833276
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.1634690484
Short name T770
Test name
Test status
Simulation time 103549880 ps
CPU time 1.41 seconds
Started Jun 10 05:52:17 PM PDT 24
Finished Jun 10 05:52:19 PM PDT 24
Peak memory 216616 kb
Host smart-f0c195f2-707d-4213-8750-b84dbb043f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634690484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.1634690484
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.318343770
Short name T622
Test name
Test status
Simulation time 209300477 ps
CPU time 0.97 seconds
Started Jun 10 05:52:09 PM PDT 24
Finished Jun 10 05:52:10 PM PDT 24
Peak memory 206204 kb
Host smart-b3537f78-b6f5-4b03-b3d0-7bc3cebe58e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=318343770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.318343770
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.3860720019
Short name T813
Test name
Test status
Simulation time 7359992404 ps
CPU time 8.36 seconds
Started Jun 10 05:52:13 PM PDT 24
Finished Jun 10 05:52:22 PM PDT 24
Peak memory 233116 kb
Host smart-23492333-937c-42da-914e-fc2d5548ba8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860720019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.3860720019
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.2918981256
Short name T837
Test name
Test status
Simulation time 72544680 ps
CPU time 0.75 seconds
Started Jun 10 05:52:19 PM PDT 24
Finished Jun 10 05:52:20 PM PDT 24
Peak memory 205184 kb
Host smart-c11d77aa-fcee-4f6c-b8b5-644fca70345a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918981256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
2918981256
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.1129216732
Short name T146
Test name
Test status
Simulation time 390696262 ps
CPU time 3.41 seconds
Started Jun 10 05:52:12 PM PDT 24
Finished Jun 10 05:52:16 PM PDT 24
Peak memory 232944 kb
Host smart-7e293bdd-9f5c-4202-a432-285a49c9450c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129216732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.1129216732
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.2550074388
Short name T898
Test name
Test status
Simulation time 25565967 ps
CPU time 0.77 seconds
Started Jun 10 05:52:18 PM PDT 24
Finished Jun 10 05:52:19 PM PDT 24
Peak memory 206192 kb
Host smart-2e6c9db0-dba4-4a44-8364-6a44f37b19f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550074388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2550074388
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.1462632781
Short name T231
Test name
Test status
Simulation time 1079480303 ps
CPU time 22.5 seconds
Started Jun 10 05:52:12 PM PDT 24
Finished Jun 10 05:52:35 PM PDT 24
Peak memory 236196 kb
Host smart-168af252-297c-4fbe-8509-734e8d29f785
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1462632781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.1462632781
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.1494382234
Short name T215
Test name
Test status
Simulation time 44497815542 ps
CPU time 190.44 seconds
Started Jun 10 05:52:16 PM PDT 24
Finished Jun 10 05:55:27 PM PDT 24
Peak memory 254380 kb
Host smart-4b9bf4a7-5880-4910-a737-da97636d5400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494382234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.1494382234
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.955319803
Short name T554
Test name
Test status
Simulation time 8361285316 ps
CPU time 47.2 seconds
Started Jun 10 05:52:24 PM PDT 24
Finished Jun 10 05:53:11 PM PDT 24
Peak memory 257556 kb
Host smart-7f3c5a05-1d4b-49c7-aa2d-0df8d3e7f245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955319803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle
.955319803
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.2448193485
Short name T434
Test name
Test status
Simulation time 84251550 ps
CPU time 3.64 seconds
Started Jun 10 05:52:24 PM PDT 24
Finished Jun 10 05:52:28 PM PDT 24
Peak memory 232996 kb
Host smart-2b70b6b4-6e75-4bb1-bcb7-43cbc7cd985f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448193485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.2448193485
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.1060204470
Short name T259
Test name
Test status
Simulation time 158960829 ps
CPU time 4.53 seconds
Started Jun 10 05:52:16 PM PDT 24
Finished Jun 10 05:52:21 PM PDT 24
Peak memory 232984 kb
Host smart-23614351-ea79-4517-8af4-cf1676977361
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060204470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1060204470
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.1499184959
Short name T648
Test name
Test status
Simulation time 9289537675 ps
CPU time 22.1 seconds
Started Jun 10 05:52:14 PM PDT 24
Finished Jun 10 05:52:37 PM PDT 24
Peak memory 233172 kb
Host smart-88fa6180-45a0-4d21-936c-6453f5bcdd5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499184959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1499184959
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.3847560182
Short name T769
Test name
Test status
Simulation time 510198374 ps
CPU time 7.72 seconds
Started Jun 10 05:52:11 PM PDT 24
Finished Jun 10 05:52:19 PM PDT 24
Peak memory 224812 kb
Host smart-fd8e0746-94db-412c-b0af-2c38f3d50dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847560182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.3847560182
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.3350330292
Short name T193
Test name
Test status
Simulation time 3923845259 ps
CPU time 4.57 seconds
Started Jun 10 05:52:19 PM PDT 24
Finished Jun 10 05:52:24 PM PDT 24
Peak memory 224960 kb
Host smart-ab40459b-1d0b-4738-9f46-9ed865781f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350330292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.3350330292
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.696842975
Short name T363
Test name
Test status
Simulation time 5582348717 ps
CPU time 17.69 seconds
Started Jun 10 05:52:21 PM PDT 24
Finished Jun 10 05:52:44 PM PDT 24
Peak memory 223504 kb
Host smart-7f5b7ca1-bc8d-4972-aaa7-1d59fc71ba3d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=696842975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dire
ct.696842975
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.972656966
Short name T840
Test name
Test status
Simulation time 52705567810 ps
CPU time 223.12 seconds
Started Jun 10 05:52:17 PM PDT 24
Finished Jun 10 05:56:00 PM PDT 24
Peak memory 263048 kb
Host smart-c2a706bd-6493-4a42-bbc1-4b0136b0acd9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972656966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stres
s_all.972656966
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.3200424431
Short name T609
Test name
Test status
Simulation time 29475580 ps
CPU time 0.74 seconds
Started Jun 10 05:52:12 PM PDT 24
Finished Jun 10 05:52:13 PM PDT 24
Peak memory 205976 kb
Host smart-da650e91-cbf2-49b3-9900-9d8231a6ecba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200424431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3200424431
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.740343768
Short name T432
Test name
Test status
Simulation time 952681375 ps
CPU time 6.92 seconds
Started Jun 10 05:52:20 PM PDT 24
Finished Jun 10 05:52:27 PM PDT 24
Peak memory 216624 kb
Host smart-222f81b0-bda5-43b7-9cce-270ef8901b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740343768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.740343768
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.786956683
Short name T335
Test name
Test status
Simulation time 17139073 ps
CPU time 0.76 seconds
Started Jun 10 05:52:13 PM PDT 24
Finished Jun 10 05:52:14 PM PDT 24
Peak memory 206228 kb
Host smart-adde0245-748f-44ee-b33a-9c054f9d8e98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786956683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.786956683
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.1972190271
Short name T339
Test name
Test status
Simulation time 59392834 ps
CPU time 0.92 seconds
Started Jun 10 05:52:12 PM PDT 24
Finished Jun 10 05:52:14 PM PDT 24
Peak memory 206200 kb
Host smart-9f9e0e13-2fb0-479a-8b73-b5b923619ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1972190271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.1972190271
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.3357181266
Short name T179
Test name
Test status
Simulation time 1284332084 ps
CPU time 4.13 seconds
Started Jun 10 05:52:17 PM PDT 24
Finished Jun 10 05:52:22 PM PDT 24
Peak memory 224772 kb
Host smart-4e3021ba-26b4-45cb-bb26-372e216b92e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357181266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.3357181266
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.2151731745
Short name T344
Test name
Test status
Simulation time 12964751 ps
CPU time 0.72 seconds
Started Jun 10 05:52:17 PM PDT 24
Finished Jun 10 05:52:19 PM PDT 24
Peak memory 205748 kb
Host smart-baa82d8b-01bf-4dac-842c-bea7c0f3754f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151731745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
2151731745
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.4086570274
Short name T566
Test name
Test status
Simulation time 151217904 ps
CPU time 2.65 seconds
Started Jun 10 05:52:18 PM PDT 24
Finished Jun 10 05:52:21 PM PDT 24
Peak memory 233008 kb
Host smart-0dadd86b-cb9a-4e2f-a8d7-1f4b3582cd2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086570274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.4086570274
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.2941801851
Short name T487
Test name
Test status
Simulation time 47998364 ps
CPU time 0.74 seconds
Started Jun 10 05:52:14 PM PDT 24
Finished Jun 10 05:52:15 PM PDT 24
Peak memory 205884 kb
Host smart-f8af776e-20f0-4b91-8084-4eb0680bd13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941801851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2941801851
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.308238480
Short name T921
Test name
Test status
Simulation time 49629795369 ps
CPU time 191.7 seconds
Started Jun 10 05:52:19 PM PDT 24
Finished Jun 10 05:55:31 PM PDT 24
Peak memory 249528 kb
Host smart-78e52590-5e9c-407e-8471-1220d64f7dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308238480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.308238480
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.3400856283
Short name T246
Test name
Test status
Simulation time 104467784921 ps
CPU time 77.72 seconds
Started Jun 10 05:52:14 PM PDT 24
Finished Jun 10 05:53:32 PM PDT 24
Peak memory 250676 kb
Host smart-cbe8878b-23f5-4416-82fb-1c59f1af4844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400856283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.3400856283
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.1270391690
Short name T800
Test name
Test status
Simulation time 659705791 ps
CPU time 7.64 seconds
Started Jun 10 05:52:18 PM PDT 24
Finished Jun 10 05:52:26 PM PDT 24
Peak memory 224804 kb
Host smart-d0cddfd0-9168-4828-b87b-28f97276e2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270391690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.1270391690
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.4216918133
Short name T8
Test name
Test status
Simulation time 1756601861 ps
CPU time 13.6 seconds
Started Jun 10 05:52:18 PM PDT 24
Finished Jun 10 05:52:32 PM PDT 24
Peak memory 224744 kb
Host smart-b23cba9a-144f-47a1-9b76-4e53cadb30f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4216918133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.4216918133
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.223054133
Short name T545
Test name
Test status
Simulation time 137065746 ps
CPU time 3.12 seconds
Started Jun 10 05:52:23 PM PDT 24
Finished Jun 10 05:52:27 PM PDT 24
Peak memory 224752 kb
Host smart-4acc5e81-8824-4299-9a37-7fc464e4f8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223054133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.223054133
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.1977301065
Short name T552
Test name
Test status
Simulation time 400402053 ps
CPU time 2.34 seconds
Started Jun 10 05:52:16 PM PDT 24
Finished Jun 10 05:52:19 PM PDT 24
Peak memory 218980 kb
Host smart-08192699-21c0-4586-a8ea-cead68506cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977301065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.1977301065
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.2304599285
Short name T943
Test name
Test status
Simulation time 1130224216 ps
CPU time 2.85 seconds
Started Jun 10 05:52:26 PM PDT 24
Finished Jun 10 05:52:30 PM PDT 24
Peak memory 224720 kb
Host smart-fd3d0c45-4bca-4371-8ae9-667cb812e231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304599285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.2304599285
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.3324475177
Short name T874
Test name
Test status
Simulation time 75746666 ps
CPU time 3.25 seconds
Started Jun 10 05:52:19 PM PDT 24
Finished Jun 10 05:52:23 PM PDT 24
Peak memory 220664 kb
Host smart-c744b21c-9d70-47a0-8292-46ce739d86a8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3324475177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.3324475177
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.1531957800
Short name T170
Test name
Test status
Simulation time 70059196688 ps
CPU time 262.16 seconds
Started Jun 10 05:52:18 PM PDT 24
Finished Jun 10 05:56:41 PM PDT 24
Peak memory 252628 kb
Host smart-9c984b96-f880-4d80-a8e6-48826c388ce1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531957800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.1531957800
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1244587729
Short name T872
Test name
Test status
Simulation time 4445443722 ps
CPU time 23.34 seconds
Started Jun 10 05:52:14 PM PDT 24
Finished Jun 10 05:52:37 PM PDT 24
Peak memory 216928 kb
Host smart-ba29a40d-84de-475f-ba65-bb7ac35a0e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244587729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1244587729
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.1799921253
Short name T900
Test name
Test status
Simulation time 4216245202 ps
CPU time 11.54 seconds
Started Jun 10 05:52:20 PM PDT 24
Finished Jun 10 05:52:32 PM PDT 24
Peak memory 216660 kb
Host smart-0aa09b6d-994b-4ba1-883e-9c9dbd9100a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799921253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1799921253
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.3068444030
Short name T818
Test name
Test status
Simulation time 16764918 ps
CPU time 0.82 seconds
Started Jun 10 05:52:22 PM PDT 24
Finished Jun 10 05:52:23 PM PDT 24
Peak memory 206192 kb
Host smart-60c24dc8-470d-4c74-8647-4ed6241c27e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068444030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3068444030
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3692552805
Short name T949
Test name
Test status
Simulation time 108978675 ps
CPU time 0.94 seconds
Started Jun 10 05:52:28 PM PDT 24
Finished Jun 10 05:52:29 PM PDT 24
Peak memory 206208 kb
Host smart-435ccc07-f7ba-42b1-8f2f-15b85d2450dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3692552805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3692552805
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.3202045335
Short name T288
Test name
Test status
Simulation time 5349111479 ps
CPU time 5.4 seconds
Started Jun 10 05:52:17 PM PDT 24
Finished Jun 10 05:52:23 PM PDT 24
Peak memory 233036 kb
Host smart-cb61e4f3-8913-4662-8566-79a79fd3ed39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202045335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.3202045335
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.1325813137
Short name T762
Test name
Test status
Simulation time 36014916 ps
CPU time 0.69 seconds
Started Jun 10 05:52:22 PM PDT 24
Finished Jun 10 05:52:23 PM PDT 24
Peak memory 205768 kb
Host smart-276e278b-a7a7-43bb-86a7-3019f9633ebb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325813137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
1325813137
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.670988612
Short name T83
Test name
Test status
Simulation time 44771912 ps
CPU time 2.66 seconds
Started Jun 10 05:52:22 PM PDT 24
Finished Jun 10 05:52:25 PM PDT 24
Peak memory 233004 kb
Host smart-89080573-f51d-4d12-910b-9413db15d65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670988612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.670988612
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.973196938
Short name T390
Test name
Test status
Simulation time 14787329 ps
CPU time 0.76 seconds
Started Jun 10 05:52:25 PM PDT 24
Finished Jun 10 05:52:26 PM PDT 24
Peak memory 207168 kb
Host smart-6bbf4729-870b-4b7c-b88a-c89715823e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973196938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.973196938
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.4282100675
Short name T674
Test name
Test status
Simulation time 13773863531 ps
CPU time 117.24 seconds
Started Jun 10 05:52:24 PM PDT 24
Finished Jun 10 05:54:22 PM PDT 24
Peak memory 249812 kb
Host smart-297423da-c742-4bb4-bbef-5eb326f945bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282100675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.4282100675
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.2214688334
Short name T445
Test name
Test status
Simulation time 23814674152 ps
CPU time 48.1 seconds
Started Jun 10 05:52:27 PM PDT 24
Finished Jun 10 05:53:15 PM PDT 24
Peak memory 224936 kb
Host smart-6f7ab314-6f1c-428c-a085-39fcdc846cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214688334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.2214688334
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.1189054997
Short name T600
Test name
Test status
Simulation time 24441512096 ps
CPU time 100.22 seconds
Started Jun 10 05:52:21 PM PDT 24
Finished Jun 10 05:54:02 PM PDT 24
Peak memory 251080 kb
Host smart-fcf6fa83-67c0-4d86-96f8-820962f19645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189054997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.1189054997
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.2675069731
Short name T428
Test name
Test status
Simulation time 2652943256 ps
CPU time 22.76 seconds
Started Jun 10 05:52:25 PM PDT 24
Finished Jun 10 05:52:48 PM PDT 24
Peak memory 233140 kb
Host smart-c8b540f2-a606-421d-a002-bdff26a56828
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675069731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.2675069731
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3446583674
Short name T407
Test name
Test status
Simulation time 3740731903 ps
CPU time 14.29 seconds
Started Jun 10 05:52:25 PM PDT 24
Finished Jun 10 05:52:40 PM PDT 24
Peak memory 224840 kb
Host smart-63480c5d-df77-415a-a3c1-d680b62a6256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446583674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3446583674
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.1320591616
Short name T5
Test name
Test status
Simulation time 3252326945 ps
CPU time 13.24 seconds
Started Jun 10 05:52:23 PM PDT 24
Finished Jun 10 05:52:37 PM PDT 24
Peak memory 232996 kb
Host smart-c71c788e-a192-47a0-9396-ebb5bacea7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1320591616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.1320591616
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.2803165
Short name T189
Test name
Test status
Simulation time 340912274 ps
CPU time 3.58 seconds
Started Jun 10 05:52:23 PM PDT 24
Finished Jun 10 05:52:27 PM PDT 24
Peak memory 232976 kb
Host smart-fc2ec4cc-ca8b-4ad5-badb-a41a07753440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap.2803165
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2995618995
Short name T160
Test name
Test status
Simulation time 141373981 ps
CPU time 2.51 seconds
Started Jun 10 05:52:15 PM PDT 24
Finished Jun 10 05:52:18 PM PDT 24
Peak memory 232804 kb
Host smart-31bde1a4-3ea4-4e45-8f90-819716fae308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995618995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2995618995
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.1190149872
Short name T878
Test name
Test status
Simulation time 3338353978 ps
CPU time 10.47 seconds
Started Jun 10 05:52:22 PM PDT 24
Finished Jun 10 05:52:33 PM PDT 24
Peak memory 221160 kb
Host smart-6774c913-9174-4d30-b1be-33cc740d8804
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1190149872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.1190149872
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.1514030296
Short name T513
Test name
Test status
Simulation time 87299884071 ps
CPU time 153.84 seconds
Started Jun 10 05:52:23 PM PDT 24
Finished Jun 10 05:54:57 PM PDT 24
Peak memory 249588 kb
Host smart-05aad3cb-4039-4dfd-afa5-9abe4a6729e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514030296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.1514030296
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2119676
Short name T690
Test name
Test status
Simulation time 1299612423 ps
CPU time 11.44 seconds
Started Jun 10 05:52:17 PM PDT 24
Finished Jun 10 05:52:29 PM PDT 24
Peak memory 216576 kb
Host smart-8fd1f844-c7fd-47fc-9190-afb49f920600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2119676
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.2403986922
Short name T342
Test name
Test status
Simulation time 6010862035 ps
CPU time 11.96 seconds
Started Jun 10 05:52:22 PM PDT 24
Finished Jun 10 05:52:34 PM PDT 24
Peak memory 216752 kb
Host smart-ccd6bc26-c81b-405f-baf1-a83d13a4304f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403986922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.2403986922
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.4040025401
Short name T925
Test name
Test status
Simulation time 86948789 ps
CPU time 1.22 seconds
Started Jun 10 05:52:18 PM PDT 24
Finished Jun 10 05:52:20 PM PDT 24
Peak memory 216580 kb
Host smart-fa965ab7-ffe0-400c-aab1-07a0310aa9e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040025401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.4040025401
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.697924697
Short name T382
Test name
Test status
Simulation time 64826049 ps
CPU time 0.84 seconds
Started Jun 10 05:52:20 PM PDT 24
Finished Jun 10 05:52:21 PM PDT 24
Peak memory 206180 kb
Host smart-18e7265b-b623-4891-9c21-a2cd7df468c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697924697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.697924697
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.2135667761
Short name T706
Test name
Test status
Simulation time 13860172603 ps
CPU time 13.88 seconds
Started Jun 10 05:52:23 PM PDT 24
Finished Jun 10 05:52:37 PM PDT 24
Peak memory 233120 kb
Host smart-cc4be628-3a5a-45a1-b39e-ae0afae39aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135667761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2135667761
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.1424555642
Short name T463
Test name
Test status
Simulation time 42958062 ps
CPU time 0.69 seconds
Started Jun 10 05:52:24 PM PDT 24
Finished Jun 10 05:52:25 PM PDT 24
Peak memory 205768 kb
Host smart-6a782820-8a2a-4a61-9000-6501240b1add
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424555642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
1424555642
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.2569993646
Short name T886
Test name
Test status
Simulation time 112774792 ps
CPU time 2.45 seconds
Started Jun 10 05:52:25 PM PDT 24
Finished Jun 10 05:52:27 PM PDT 24
Peak memory 224232 kb
Host smart-8fc2b58e-66ad-4b80-a0f4-c980b727bfd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569993646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2569993646
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.624297285
Short name T831
Test name
Test status
Simulation time 37544573 ps
CPU time 0.79 seconds
Started Jun 10 05:52:22 PM PDT 24
Finished Jun 10 05:52:23 PM PDT 24
Peak memory 207244 kb
Host smart-ac8d21b8-af8a-44f9-8e99-a299488fcb8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624297285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.624297285
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.3318128115
Short name T618
Test name
Test status
Simulation time 10332911513 ps
CPU time 41.32 seconds
Started Jun 10 05:52:32 PM PDT 24
Finished Jun 10 05:53:14 PM PDT 24
Peak memory 249508 kb
Host smart-35115494-4899-40fe-a0dc-83320cdf2d42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318128115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.3318128115
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.1440340646
Short name T788
Test name
Test status
Simulation time 20796169216 ps
CPU time 77.83 seconds
Started Jun 10 05:52:32 PM PDT 24
Finished Jun 10 05:53:50 PM PDT 24
Peak memory 255208 kb
Host smart-5c5a3102-7199-4993-959b-e9be99119ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440340646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.1440340646
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.2220020388
Short name T11
Test name
Test status
Simulation time 3092547873 ps
CPU time 28.95 seconds
Started Jun 10 05:52:28 PM PDT 24
Finished Jun 10 05:52:58 PM PDT 24
Peak memory 241316 kb
Host smart-e233acd3-69c9-45d3-9f1f-91ae4d43b872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220020388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.2220020388
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3926759481
Short name T274
Test name
Test status
Simulation time 2273968238 ps
CPU time 12.74 seconds
Started Jun 10 05:52:25 PM PDT 24
Finished Jun 10 05:52:38 PM PDT 24
Peak memory 233152 kb
Host smart-6fd6b0f5-7955-4dc5-85db-bfd1ad86b5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926759481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3926759481
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.448001840
Short name T44
Test name
Test status
Simulation time 57878993881 ps
CPU time 146.1 seconds
Started Jun 10 05:52:21 PM PDT 24
Finished Jun 10 05:54:48 PM PDT 24
Peak memory 241132 kb
Host smart-6bf2110e-889c-49a3-9d1f-eedd4ce9f16c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448001840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.448001840
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.831418817
Short name T243
Test name
Test status
Simulation time 287318440 ps
CPU time 4.23 seconds
Started Jun 10 05:52:21 PM PDT 24
Finished Jun 10 05:52:26 PM PDT 24
Peak memory 224880 kb
Host smart-657490f6-156c-4be7-a790-c1a6d1d27d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831418817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap
.831418817
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3759912919
Short name T905
Test name
Test status
Simulation time 1792164348 ps
CPU time 6.74 seconds
Started Jun 10 05:52:19 PM PDT 24
Finished Jun 10 05:52:26 PM PDT 24
Peak memory 240708 kb
Host smart-34f6a88e-1b3e-48fb-b5c3-2b18b70391a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759912919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3759912919
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.949574467
Short name T412
Test name
Test status
Simulation time 804465149 ps
CPU time 7.39 seconds
Started Jun 10 05:52:25 PM PDT 24
Finished Jun 10 05:52:33 PM PDT 24
Peak memory 223400 kb
Host smart-6912687f-da6c-45eb-86c6-ebaa3bd571ed
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=949574467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dire
ct.949574467
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.1156490564
Short name T245
Test name
Test status
Simulation time 12953804402 ps
CPU time 81.41 seconds
Started Jun 10 05:52:26 PM PDT 24
Finished Jun 10 05:53:48 PM PDT 24
Peak memory 253348 kb
Host smart-e1a656f5-2a24-4c89-9374-72f82911b625
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156490564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.1156490564
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.3618524811
Short name T530
Test name
Test status
Simulation time 366545755 ps
CPU time 4.16 seconds
Started Jun 10 05:52:21 PM PDT 24
Finished Jun 10 05:52:25 PM PDT 24
Peak memory 216640 kb
Host smart-73401fda-d6ab-4cdd-b7e0-b80cbea2cada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618524811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3618524811
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.447835424
Short name T620
Test name
Test status
Simulation time 5475283858 ps
CPU time 5.44 seconds
Started Jun 10 05:52:24 PM PDT 24
Finished Jun 10 05:52:30 PM PDT 24
Peak memory 216756 kb
Host smart-6d2f56ba-18f5-44ec-bd95-d747227813b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447835424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.447835424
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.72997525
Short name T527
Test name
Test status
Simulation time 20163752 ps
CPU time 0.85 seconds
Started Jun 10 05:52:27 PM PDT 24
Finished Jun 10 05:52:28 PM PDT 24
Peak memory 206700 kb
Host smart-cbde5d69-6a57-497f-b67a-9eb3faabf887
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72997525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.72997525
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.3705303809
Short name T25
Test name
Test status
Simulation time 149254691 ps
CPU time 0.87 seconds
Started Jun 10 05:52:22 PM PDT 24
Finished Jun 10 05:52:24 PM PDT 24
Peak memory 207248 kb
Host smart-0cbe542a-3335-451b-bf7c-47f50fe0e29d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705303809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.3705303809
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.1643110857
Short name T798
Test name
Test status
Simulation time 3205760080 ps
CPU time 12.91 seconds
Started Jun 10 05:52:22 PM PDT 24
Finished Jun 10 05:52:35 PM PDT 24
Peak memory 241284 kb
Host smart-bde42039-25af-4dba-81b7-4ffcd9635f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643110857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.1643110857
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.1324612465
Short name T491
Test name
Test status
Simulation time 12677448 ps
CPU time 0.73 seconds
Started Jun 10 05:51:04 PM PDT 24
Finished Jun 10 05:51:06 PM PDT 24
Peak memory 205776 kb
Host smart-05962af4-b18f-45e1-b818-a0337c5829e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324612465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.1
324612465
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.2254260916
Short name T926
Test name
Test status
Simulation time 4211852148 ps
CPU time 9.19 seconds
Started Jun 10 05:51:04 PM PDT 24
Finished Jun 10 05:51:13 PM PDT 24
Peak memory 224840 kb
Host smart-343a4054-a0f9-419a-a8cd-1e6edc237b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254260916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.2254260916
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.3493907918
Short name T395
Test name
Test status
Simulation time 79092812 ps
CPU time 0.75 seconds
Started Jun 10 05:50:57 PM PDT 24
Finished Jun 10 05:50:58 PM PDT 24
Peak memory 206924 kb
Host smart-e51492f9-eeab-4b20-a728-7c3ce1c12596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493907918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.3493907918
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.3116440489
Short name T778
Test name
Test status
Simulation time 2085712173 ps
CPU time 18.31 seconds
Started Jun 10 05:50:58 PM PDT 24
Finished Jun 10 05:51:17 PM PDT 24
Peak memory 236920 kb
Host smart-437d4ac4-e746-45e9-b79a-8cc933e9fda7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116440489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3116440489
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_intercept.2896966989
Short name T634
Test name
Test status
Simulation time 248007368 ps
CPU time 4.64 seconds
Started Jun 10 05:50:56 PM PDT 24
Finished Jun 10 05:51:02 PM PDT 24
Peak memory 224828 kb
Host smart-a872d18c-4309-4572-ae85-37bbe3f38f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896966989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2896966989
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.3611909601
Short name T646
Test name
Test status
Simulation time 3792958185 ps
CPU time 45.22 seconds
Started Jun 10 05:51:05 PM PDT 24
Finished Jun 10 05:51:51 PM PDT 24
Peak memory 233088 kb
Host smart-40f104ce-70f3-47de-ac4a-598d1898e33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611909601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3611909601
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3848703469
Short name T805
Test name
Test status
Simulation time 10515717813 ps
CPU time 30.53 seconds
Started Jun 10 05:50:56 PM PDT 24
Finished Jun 10 05:51:27 PM PDT 24
Peak memory 241216 kb
Host smart-ce6f6186-9724-4fb3-8bf4-0eace0d9b8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848703469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3848703469
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.2908577742
Short name T192
Test name
Test status
Simulation time 4253422139 ps
CPU time 8.16 seconds
Started Jun 10 05:51:13 PM PDT 24
Finished Jun 10 05:51:22 PM PDT 24
Peak memory 218920 kb
Host smart-4cb8a369-a336-4d0c-97fa-b3252dcbb248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908577742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.2908577742
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.2332597844
Short name T489
Test name
Test status
Simulation time 6488459982 ps
CPU time 13.87 seconds
Started Jun 10 05:51:12 PM PDT 24
Finished Jun 10 05:51:26 PM PDT 24
Peak memory 223604 kb
Host smart-30dc3c79-16d6-49f4-8703-51c7a6707050
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2332597844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.2332597844
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.3239841144
Short name T76
Test name
Test status
Simulation time 252168933 ps
CPU time 1.01 seconds
Started Jun 10 05:51:00 PM PDT 24
Finished Jun 10 05:51:02 PM PDT 24
Peak memory 236024 kb
Host smart-ea8a68ae-097b-447e-96fe-dc60befa230b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239841144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.3239841144
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.3475435349
Short name T18
Test name
Test status
Simulation time 52197913 ps
CPU time 0.99 seconds
Started Jun 10 05:51:00 PM PDT 24
Finished Jun 10 05:51:01 PM PDT 24
Peak memory 206900 kb
Host smart-87b85f14-bb06-4336-a1c9-202574fd6d6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475435349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.3475435349
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.1727565738
Short name T675
Test name
Test status
Simulation time 3915939805 ps
CPU time 16.48 seconds
Started Jun 10 05:50:54 PM PDT 24
Finished Jun 10 05:51:11 PM PDT 24
Peak memory 217004 kb
Host smart-2eb0340b-8214-430f-919d-7830d1e17219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727565738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.1727565738
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.4013080958
Short name T556
Test name
Test status
Simulation time 7132493853 ps
CPU time 13.88 seconds
Started Jun 10 05:51:00 PM PDT 24
Finished Jun 10 05:51:14 PM PDT 24
Peak memory 216756 kb
Host smart-4062c054-7708-4adc-93bf-543bc80109a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013080958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.4013080958
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.1142373732
Short name T535
Test name
Test status
Simulation time 868631465 ps
CPU time 3.08 seconds
Started Jun 10 05:50:56 PM PDT 24
Finished Jun 10 05:51:00 PM PDT 24
Peak memory 216632 kb
Host smart-b543c7c5-5540-4a27-9c60-decf1d42ec91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142373732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1142373732
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.141537990
Short name T462
Test name
Test status
Simulation time 45944359 ps
CPU time 0.89 seconds
Started Jun 10 05:51:11 PM PDT 24
Finished Jun 10 05:51:12 PM PDT 24
Peak memory 206204 kb
Host smart-14224388-0683-4fd8-aa69-c7a9a9ed4d3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141537990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.141537990
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.477221079
Short name T832
Test name
Test status
Simulation time 11066090313 ps
CPU time 11.03 seconds
Started Jun 10 05:51:04 PM PDT 24
Finished Jun 10 05:51:16 PM PDT 24
Peak memory 233136 kb
Host smart-5b88c07c-4291-4c1b-98ae-3fddd72e0fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477221079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.477221079
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.808011606
Short name T420
Test name
Test status
Simulation time 58701120 ps
CPU time 0.75 seconds
Started Jun 10 05:52:30 PM PDT 24
Finished Jun 10 05:52:31 PM PDT 24
Peak memory 205708 kb
Host smart-f8dd1b9c-2b74-41b1-a639-5c329fb63c05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808011606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.808011606
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.3479149844
Short name T950
Test name
Test status
Simulation time 246271083 ps
CPU time 3.58 seconds
Started Jun 10 05:52:29 PM PDT 24
Finished Jun 10 05:52:33 PM PDT 24
Peak memory 233004 kb
Host smart-d7d2b051-ff7c-4473-b872-e760ab3c04e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479149844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.3479149844
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.3505335949
Short name T466
Test name
Test status
Simulation time 64470319 ps
CPU time 0.75 seconds
Started Jun 10 05:52:26 PM PDT 24
Finished Jun 10 05:52:27 PM PDT 24
Peak memory 205876 kb
Host smart-a1629bb5-db9d-42b0-92fa-55f83db62e6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505335949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3505335949
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.2548100367
Short name T793
Test name
Test status
Simulation time 10148900202 ps
CPU time 82.6 seconds
Started Jun 10 05:52:32 PM PDT 24
Finished Jun 10 05:53:55 PM PDT 24
Peak memory 249520 kb
Host smart-976b7f2e-cf64-432a-ab9a-2520125183e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548100367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.2548100367
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.3616535106
Short name T206
Test name
Test status
Simulation time 268695522505 ps
CPU time 451.39 seconds
Started Jun 10 05:52:30 PM PDT 24
Finished Jun 10 06:00:02 PM PDT 24
Peak memory 250872 kb
Host smart-0a8f1547-68a5-4cbe-94e3-5c4520a8ac40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616535106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.3616535106
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.3830013746
Short name T50
Test name
Test status
Simulation time 1821908406 ps
CPU time 42.35 seconds
Started Jun 10 05:52:29 PM PDT 24
Finished Jun 10 05:53:12 PM PDT 24
Peak memory 249468 kb
Host smart-7172a876-ac00-4774-af3e-9baa82b61824
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830013746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.3830013746
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.759287882
Short name T499
Test name
Test status
Simulation time 1526226652 ps
CPU time 9.61 seconds
Started Jun 10 05:52:29 PM PDT 24
Finished Jun 10 05:52:39 PM PDT 24
Peak memory 249400 kb
Host smart-ced191e5-27b6-47bc-b0b6-829533607485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759287882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.759287882
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.2408823466
Short name T870
Test name
Test status
Simulation time 1314221830 ps
CPU time 11.57 seconds
Started Jun 10 05:52:30 PM PDT 24
Finished Jun 10 05:52:42 PM PDT 24
Peak memory 232940 kb
Host smart-af19d692-8afb-46d4-a0d3-64aad99032d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408823466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.2408823466
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.2383545506
Short name T610
Test name
Test status
Simulation time 124581556 ps
CPU time 2.32 seconds
Started Jun 10 05:52:25 PM PDT 24
Finished Jun 10 05:52:28 PM PDT 24
Peak memory 232924 kb
Host smart-d111272c-1e7e-4c3e-8f1d-2c763243f5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383545506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2383545506
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2655910676
Short name T299
Test name
Test status
Simulation time 15579272663 ps
CPU time 25.45 seconds
Started Jun 10 05:52:29 PM PDT 24
Finished Jun 10 05:52:55 PM PDT 24
Peak memory 241320 kb
Host smart-c260c874-f747-4ed0-a818-49572e6785c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655910676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.2655910676
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1003744267
Short name T771
Test name
Test status
Simulation time 4860232765 ps
CPU time 9.87 seconds
Started Jun 10 05:52:23 PM PDT 24
Finished Jun 10 05:52:33 PM PDT 24
Peak memory 224960 kb
Host smart-692a2191-6366-4a39-97f5-9e4c5c89d85a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003744267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1003744267
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.1175720789
Short name T375
Test name
Test status
Simulation time 2011756725 ps
CPU time 6.45 seconds
Started Jun 10 05:52:45 PM PDT 24
Finished Jun 10 05:52:52 PM PDT 24
Peak memory 222888 kb
Host smart-c70e2879-a3d9-4bfe-ac26-c2e647855b04
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1175720789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.1175720789
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.3452517557
Short name T159
Test name
Test status
Simulation time 199557634 ps
CPU time 0.97 seconds
Started Jun 10 05:52:33 PM PDT 24
Finished Jun 10 05:52:34 PM PDT 24
Peak memory 206032 kb
Host smart-46e7c25b-0c98-434d-b6e3-a0af0dd2304a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452517557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.3452517557
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.876042533
Short name T625
Test name
Test status
Simulation time 2768519823 ps
CPU time 12.33 seconds
Started Jun 10 05:52:25 PM PDT 24
Finished Jun 10 05:52:38 PM PDT 24
Peak memory 216744 kb
Host smart-bb685268-5406-4f09-9b48-8772b4f38027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876042533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.876042533
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.2461201926
Short name T780
Test name
Test status
Simulation time 1143422598 ps
CPU time 1.59 seconds
Started Jun 10 05:52:26 PM PDT 24
Finished Jun 10 05:52:28 PM PDT 24
Peak memory 208096 kb
Host smart-3b01d9cf-8fb4-45db-b7d8-5abcd11472c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461201926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2461201926
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.2069643773
Short name T484
Test name
Test status
Simulation time 98457549 ps
CPU time 1.11 seconds
Started Jun 10 05:52:25 PM PDT 24
Finished Jun 10 05:52:27 PM PDT 24
Peak memory 208076 kb
Host smart-75c16057-1e9a-4f0a-8c65-97276a74bbfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069643773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2069643773
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.387938033
Short name T833
Test name
Test status
Simulation time 66761269 ps
CPU time 0.78 seconds
Started Jun 10 05:52:30 PM PDT 24
Finished Jun 10 05:52:32 PM PDT 24
Peak memory 206188 kb
Host smart-616cf931-d70c-4f88-a8f4-3513a2111258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387938033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.387938033
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.471408441
Short name T514
Test name
Test status
Simulation time 6358587974 ps
CPU time 9.01 seconds
Started Jun 10 05:52:36 PM PDT 24
Finished Jun 10 05:52:45 PM PDT 24
Peak memory 224880 kb
Host smart-3bfb749c-ae79-47b3-984d-70fb7fd51657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471408441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.471408441
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.512759777
Short name T671
Test name
Test status
Simulation time 47844308 ps
CPU time 0.76 seconds
Started Jun 10 05:52:30 PM PDT 24
Finished Jun 10 05:52:31 PM PDT 24
Peak memory 205780 kb
Host smart-59a2b871-ded0-471d-b776-a421bedac0fc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512759777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.512759777
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.2193777909
Short name T576
Test name
Test status
Simulation time 3928783322 ps
CPU time 12.79 seconds
Started Jun 10 05:52:30 PM PDT 24
Finished Jun 10 05:52:48 PM PDT 24
Peak memory 233040 kb
Host smart-cac872ea-8f72-4904-8dcb-2915803f0852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193777909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.2193777909
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.1922600017
Short name T352
Test name
Test status
Simulation time 73014084 ps
CPU time 0.76 seconds
Started Jun 10 05:52:28 PM PDT 24
Finished Jun 10 05:52:29 PM PDT 24
Peak memory 205896 kb
Host smart-b73c66cf-f04a-46dc-aab4-515dcc1d2b33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922600017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1922600017
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.1535522212
Short name T748
Test name
Test status
Simulation time 3762425943 ps
CPU time 50.02 seconds
Started Jun 10 05:52:42 PM PDT 24
Finished Jun 10 05:53:32 PM PDT 24
Peak memory 250636 kb
Host smart-b05208e7-9522-47f7-8313-fdbe8421d6d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535522212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.1535522212
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.390390258
Short name T239
Test name
Test status
Simulation time 16468883752 ps
CPU time 64.88 seconds
Started Jun 10 05:52:48 PM PDT 24
Finished Jun 10 05:53:54 PM PDT 24
Peak memory 249504 kb
Host smart-492b10eb-6c65-4a13-8034-65b9b4f3b551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390390258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.390390258
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.3638251831
Short name T287
Test name
Test status
Simulation time 4533468662 ps
CPU time 50.64 seconds
Started Jun 10 05:52:52 PM PDT 24
Finished Jun 10 05:53:43 PM PDT 24
Peak memory 236268 kb
Host smart-a4aa0903-3c64-47b2-beff-ccb433246545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638251831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.3638251831
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.2238938538
Short name T371
Test name
Test status
Simulation time 1411194963 ps
CPU time 14.22 seconds
Started Jun 10 05:52:33 PM PDT 24
Finished Jun 10 05:52:48 PM PDT 24
Peak memory 237892 kb
Host smart-05afd0c1-c8f7-46fd-aae5-3bc7d66809cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238938538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.2238938538
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.296453953
Short name T717
Test name
Test status
Simulation time 10595058983 ps
CPU time 24.17 seconds
Started Jun 10 05:52:28 PM PDT 24
Finished Jun 10 05:52:52 PM PDT 24
Peak memory 233144 kb
Host smart-c0dbe006-1e81-4889-bce6-5d9fe55735c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296453953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.296453953
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.3867093206
Short name T291
Test name
Test status
Simulation time 206586824 ps
CPU time 7.7 seconds
Started Jun 10 05:52:45 PM PDT 24
Finished Jun 10 05:52:53 PM PDT 24
Peak memory 232964 kb
Host smart-96484c58-d82d-4a52-8c1c-b97bf7be5443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867093206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.3867093206
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.1660823263
Short name T789
Test name
Test status
Simulation time 31019251 ps
CPU time 2.23 seconds
Started Jun 10 05:52:30 PM PDT 24
Finished Jun 10 05:52:33 PM PDT 24
Peak memory 232748 kb
Host smart-302d7e37-c3d7-4561-9e4c-e34ad8d88d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660823263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.1660823263
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.2279532385
Short name T724
Test name
Test status
Simulation time 6386510616 ps
CPU time 8.56 seconds
Started Jun 10 05:52:32 PM PDT 24
Finished Jun 10 05:52:41 PM PDT 24
Peak memory 233160 kb
Host smart-2e5d5874-0673-4cb1-a8f7-1573e1e02dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2279532385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.2279532385
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.2865700979
Short name T739
Test name
Test status
Simulation time 771937037 ps
CPU time 4.54 seconds
Started Jun 10 05:52:45 PM PDT 24
Finished Jun 10 05:52:50 PM PDT 24
Peak memory 219268 kb
Host smart-e7087b33-b84e-458d-b7d4-5bfd6950e9f0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2865700979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.2865700979
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.3457603185
Short name T269
Test name
Test status
Simulation time 3119924580 ps
CPU time 57.09 seconds
Started Jun 10 05:52:37 PM PDT 24
Finished Jun 10 05:53:35 PM PDT 24
Peak memory 249496 kb
Host smart-28cb8676-3adc-469a-a455-b3bd9efc4e3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457603185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.3457603185
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.3949940275
Short name T843
Test name
Test status
Simulation time 5477679858 ps
CPU time 7.95 seconds
Started Jun 10 05:52:29 PM PDT 24
Finished Jun 10 05:52:37 PM PDT 24
Peak memory 216716 kb
Host smart-4ca09559-aae1-4b58-bc56-5e4dbfceda4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949940275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.3949940275
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.2728591193
Short name T358
Test name
Test status
Simulation time 238060663 ps
CPU time 1.17 seconds
Started Jun 10 05:52:46 PM PDT 24
Finished Jun 10 05:52:47 PM PDT 24
Peak memory 207696 kb
Host smart-b1fadf49-0c76-4fb4-bf94-81aa3a99977a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728591193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.2728591193
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.2595322032
Short name T882
Test name
Test status
Simulation time 61206986 ps
CPU time 0.87 seconds
Started Jun 10 05:52:43 PM PDT 24
Finished Jun 10 05:52:44 PM PDT 24
Peak memory 206180 kb
Host smart-7137d727-992f-4c12-9cfb-2a07636aa4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595322032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.2595322032
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.4039512797
Short name T426
Test name
Test status
Simulation time 105206823 ps
CPU time 2.98 seconds
Started Jun 10 05:52:33 PM PDT 24
Finished Jun 10 05:52:36 PM PDT 24
Peak memory 233012 kb
Host smart-e262100f-0cea-40f2-a791-255359fc52c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039512797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.4039512797
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.2142937799
Short name T586
Test name
Test status
Simulation time 11761284 ps
CPU time 0.69 seconds
Started Jun 10 05:52:50 PM PDT 24
Finished Jun 10 05:52:51 PM PDT 24
Peak memory 205748 kb
Host smart-476d15e3-8349-4502-99be-023bcaa9c9ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142937799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
2142937799
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.46146586
Short name T892
Test name
Test status
Simulation time 644119261 ps
CPU time 3.64 seconds
Started Jun 10 05:52:34 PM PDT 24
Finished Jun 10 05:52:38 PM PDT 24
Peak memory 233016 kb
Host smart-edc7dbad-b24c-45ee-bf34-849a05fd024a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46146586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.46146586
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.602678500
Short name T63
Test name
Test status
Simulation time 66775043 ps
CPU time 0.81 seconds
Started Jun 10 05:52:44 PM PDT 24
Finished Jun 10 05:52:45 PM PDT 24
Peak memory 207224 kb
Host smart-8c2b2f1b-5594-455a-9531-9f505f195490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602678500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.602678500
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.55799227
Short name T28
Test name
Test status
Simulation time 38997650143 ps
CPU time 368.45 seconds
Started Jun 10 05:52:35 PM PDT 24
Finished Jun 10 05:58:44 PM PDT 24
Peak memory 269636 kb
Host smart-010f2b88-b78c-4549-bfab-88299d6df7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55799227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.55799227
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.37854017
Short name T256
Test name
Test status
Simulation time 21565586031 ps
CPU time 114.04 seconds
Started Jun 10 05:52:34 PM PDT 24
Finished Jun 10 05:54:29 PM PDT 24
Peak memory 241352 kb
Host smart-876bfc23-ddc2-40fa-8712-508f55a2d061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37854017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle.37854017
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.2890772718
Short name T485
Test name
Test status
Simulation time 6034623744 ps
CPU time 22.06 seconds
Started Jun 10 05:52:45 PM PDT 24
Finished Jun 10 05:53:08 PM PDT 24
Peak memory 224864 kb
Host smart-9883ee9e-a13a-44ab-b966-cf32958dd3e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890772718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2890772718
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.601728685
Short name T207
Test name
Test status
Simulation time 269701174 ps
CPU time 5.42 seconds
Started Jun 10 05:52:40 PM PDT 24
Finished Jun 10 05:52:46 PM PDT 24
Peak memory 224796 kb
Host smart-e8856083-9212-4ac0-86f0-de6077a07b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=601728685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.601728685
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.3575092115
Short name T853
Test name
Test status
Simulation time 8554440318 ps
CPU time 8.91 seconds
Started Jun 10 05:52:35 PM PDT 24
Finished Jun 10 05:52:45 PM PDT 24
Peak memory 224856 kb
Host smart-e1b2ddaa-e6b1-448f-b5e6-3d2d3be46c8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575092115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3575092115
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.3527076366
Short name T755
Test name
Test status
Simulation time 286978698 ps
CPU time 6.64 seconds
Started Jun 10 05:52:33 PM PDT 24
Finished Jun 10 05:52:40 PM PDT 24
Peak memory 232996 kb
Host smart-ffc3795b-024c-43f4-903f-b723f06ef602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527076366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.3527076366
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.2084435256
Short name T630
Test name
Test status
Simulation time 744870893 ps
CPU time 2.8 seconds
Started Jun 10 05:52:46 PM PDT 24
Finished Jun 10 05:52:59 PM PDT 24
Peak memory 233028 kb
Host smart-1899ebff-7d1e-4e68-bc63-a0ce265e6728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084435256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2084435256
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.1937735773
Short name T393
Test name
Test status
Simulation time 123415740 ps
CPU time 3.53 seconds
Started Jun 10 05:52:47 PM PDT 24
Finished Jun 10 05:52:51 PM PDT 24
Peak memory 220808 kb
Host smart-a3105a09-f8ad-424f-868c-0f34ee4a0f24
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1937735773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.1937735773
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.3534247351
Short name T909
Test name
Test status
Simulation time 3002253518 ps
CPU time 5.94 seconds
Started Jun 10 05:52:35 PM PDT 24
Finished Jun 10 05:52:41 PM PDT 24
Peak memory 216844 kb
Host smart-89e39adf-b673-43a2-9135-24d8b9271d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534247351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3534247351
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.2817536232
Short name T523
Test name
Test status
Simulation time 5362124842 ps
CPU time 7.85 seconds
Started Jun 10 05:52:35 PM PDT 24
Finished Jun 10 05:52:44 PM PDT 24
Peak memory 216660 kb
Host smart-78924571-de8d-43bf-b731-6f7c3822d718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817536232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.2817536232
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.4143451654
Short name T604
Test name
Test status
Simulation time 690106750 ps
CPU time 2.18 seconds
Started Jun 10 05:52:31 PM PDT 24
Finished Jun 10 05:52:33 PM PDT 24
Peak memory 216604 kb
Host smart-8f1a7aa1-0e4e-483c-a2e2-8752bbe611a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143451654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.4143451654
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.3078262394
Short name T501
Test name
Test status
Simulation time 144516768 ps
CPU time 0.77 seconds
Started Jun 10 05:52:34 PM PDT 24
Finished Jun 10 05:52:36 PM PDT 24
Peak memory 206152 kb
Host smart-f876176b-7cc7-4c44-a1b6-0c17485a1338
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078262394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3078262394
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.1884550154
Short name T845
Test name
Test status
Simulation time 239225763 ps
CPU time 2.44 seconds
Started Jun 10 05:52:33 PM PDT 24
Finished Jun 10 05:52:36 PM PDT 24
Peak memory 223956 kb
Host smart-ab83b344-0d6d-40ce-bc99-0648e8c7508e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884550154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1884550154
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.592304164
Short name T400
Test name
Test status
Simulation time 44842673 ps
CPU time 0.74 seconds
Started Jun 10 05:52:37 PM PDT 24
Finished Jun 10 05:52:38 PM PDT 24
Peak memory 205768 kb
Host smart-d85c0ddc-0cb0-4643-8094-36f3bf8140ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592304164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.592304164
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.3995446716
Short name T958
Test name
Test status
Simulation time 3833527200 ps
CPU time 12.1 seconds
Started Jun 10 05:52:45 PM PDT 24
Finished Jun 10 05:52:57 PM PDT 24
Peak memory 224952 kb
Host smart-48eac255-7580-4c19-adc3-09f33d854155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995446716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.3995446716
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.1351016266
Short name T451
Test name
Test status
Simulation time 15437147 ps
CPU time 0.78 seconds
Started Jun 10 05:52:36 PM PDT 24
Finished Jun 10 05:52:37 PM PDT 24
Peak memory 206868 kb
Host smart-dd3638e5-1e03-47ba-85a8-4595e0800c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351016266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1351016266
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.1337745981
Short name T751
Test name
Test status
Simulation time 24610892730 ps
CPU time 79.32 seconds
Started Jun 10 05:52:36 PM PDT 24
Finished Jun 10 05:53:56 PM PDT 24
Peak memory 249512 kb
Host smart-64efc748-00a5-4bd3-8341-6e7548d4b724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337745981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.1337745981
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.1079802991
Short name T794
Test name
Test status
Simulation time 12538432371 ps
CPU time 116.71 seconds
Started Jun 10 05:52:40 PM PDT 24
Finished Jun 10 05:54:37 PM PDT 24
Peak memory 249584 kb
Host smart-7f980527-cd70-469d-807a-61d5181df200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079802991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1079802991
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.3915669993
Short name T354
Test name
Test status
Simulation time 63536697 ps
CPU time 3.37 seconds
Started Jun 10 05:52:35 PM PDT 24
Finished Jun 10 05:52:39 PM PDT 24
Peak memory 233036 kb
Host smart-9e34b333-e6c3-4822-b8b5-b7143d5d4264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915669993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.3915669993
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.3245469488
Short name T257
Test name
Test status
Simulation time 1286929924 ps
CPU time 6.4 seconds
Started Jun 10 05:52:48 PM PDT 24
Finished Jun 10 05:52:55 PM PDT 24
Peak memory 224740 kb
Host smart-37315126-89d2-4c3d-94b6-63f2ae4e703d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245469488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.3245469488
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.2734442861
Short name T578
Test name
Test status
Simulation time 128325208 ps
CPU time 2.55 seconds
Started Jun 10 05:52:47 PM PDT 24
Finished Jun 10 05:52:50 PM PDT 24
Peak memory 232844 kb
Host smart-123065ce-0ef5-4473-a4d5-af648aa33c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734442861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2734442861
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.724520957
Short name T1
Test name
Test status
Simulation time 403218073 ps
CPU time 4.88 seconds
Started Jun 10 05:52:52 PM PDT 24
Finished Jun 10 05:52:57 PM PDT 24
Peak memory 233004 kb
Host smart-05ff0f4b-c96c-48b9-936f-24f6d342481b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724520957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap
.724520957
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.1464260878
Short name T289
Test name
Test status
Simulation time 193232315 ps
CPU time 2.74 seconds
Started Jun 10 05:52:49 PM PDT 24
Finished Jun 10 05:52:52 PM PDT 24
Peak memory 224796 kb
Host smart-6f33c7c8-85f3-4f21-bbdc-ab253c66efa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464260878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.1464260878
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.2384805111
Short name T569
Test name
Test status
Simulation time 1689906251 ps
CPU time 17.38 seconds
Started Jun 10 05:52:50 PM PDT 24
Finished Jun 10 05:53:08 PM PDT 24
Peak memory 219420 kb
Host smart-c6832979-bcd7-49ed-8726-a50ed3d4ad3b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2384805111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.2384805111
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.2974564777
Short name T155
Test name
Test status
Simulation time 41819479509 ps
CPU time 384.14 seconds
Started Jun 10 05:52:42 PM PDT 24
Finished Jun 10 05:59:07 PM PDT 24
Peak memory 251184 kb
Host smart-055bfbf9-8da6-48c3-9eba-b5d1366f4e25
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974564777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.2974564777
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.3570987515
Short name T759
Test name
Test status
Simulation time 3184247742 ps
CPU time 15.02 seconds
Started Jun 10 05:52:42 PM PDT 24
Finished Jun 10 05:52:58 PM PDT 24
Peak memory 216780 kb
Host smart-1ecdbfb4-0b40-4241-abc3-17d80e5ce230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570987515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3570987515
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.3477306110
Short name T705
Test name
Test status
Simulation time 11693072898 ps
CPU time 12.11 seconds
Started Jun 10 05:52:40 PM PDT 24
Finished Jun 10 05:52:52 PM PDT 24
Peak memory 216736 kb
Host smart-e3fef7bd-9a3b-430a-9c9f-ecb717855428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477306110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3477306110
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.3440815982
Short name T713
Test name
Test status
Simulation time 661717967 ps
CPU time 2.52 seconds
Started Jun 10 05:52:38 PM PDT 24
Finished Jun 10 05:52:41 PM PDT 24
Peak memory 216644 kb
Host smart-b00b370a-5a86-4c11-b7aa-cb3ba86cd4e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440815982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3440815982
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.3205729938
Short name T595
Test name
Test status
Simulation time 52888524 ps
CPU time 0.82 seconds
Started Jun 10 05:52:46 PM PDT 24
Finished Jun 10 05:52:47 PM PDT 24
Peak memory 206188 kb
Host smart-6113f27a-9168-42fe-a47c-764f00e2e8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205729938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.3205729938
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.1450472121
Short name T937
Test name
Test status
Simulation time 7285362880 ps
CPU time 14.92 seconds
Started Jun 10 05:52:37 PM PDT 24
Finished Jun 10 05:52:52 PM PDT 24
Peak memory 224844 kb
Host smart-8225d782-3bbb-4904-a0b5-79c37931f39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450472121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.1450472121
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.748503992
Short name T885
Test name
Test status
Simulation time 13172844 ps
CPU time 0.7 seconds
Started Jun 10 05:52:41 PM PDT 24
Finished Jun 10 05:52:43 PM PDT 24
Peak memory 205720 kb
Host smart-b5c9e1c7-0ae4-40f9-9ede-f2f46f277f8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748503992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.748503992
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.1209436404
Short name T504
Test name
Test status
Simulation time 254163636 ps
CPU time 2.54 seconds
Started Jun 10 05:52:48 PM PDT 24
Finished Jun 10 05:52:51 PM PDT 24
Peak memory 232836 kb
Host smart-8eab0f7b-4d40-4949-8eb7-cd3dfdbb8f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209436404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.1209436404
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.229637657
Short name T808
Test name
Test status
Simulation time 47786862 ps
CPU time 0.79 seconds
Started Jun 10 05:52:36 PM PDT 24
Finished Jun 10 05:52:37 PM PDT 24
Peak memory 206932 kb
Host smart-5ceac874-bbe6-4edc-a116-33216ee9e6c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229637657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.229637657
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.569144803
Short name T656
Test name
Test status
Simulation time 4872639241 ps
CPU time 15.36 seconds
Started Jun 10 05:52:41 PM PDT 24
Finished Jun 10 05:52:57 PM PDT 24
Peak memory 250536 kb
Host smart-94ef032a-2c28-47cd-bd55-d17eac2405b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569144803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.569144803
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.1344480868
Short name T171
Test name
Test status
Simulation time 160381904937 ps
CPU time 171.99 seconds
Started Jun 10 05:52:44 PM PDT 24
Finished Jun 10 05:55:36 PM PDT 24
Peak memory 241368 kb
Host smart-a51529e3-bdb6-495d-9bc1-b521a710c352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344480868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1344480868
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.1591324151
Short name T236
Test name
Test status
Simulation time 3387084910 ps
CPU time 64.84 seconds
Started Jun 10 05:52:48 PM PDT 24
Finished Jun 10 05:53:53 PM PDT 24
Peak memory 257660 kb
Host smart-982a5263-fc92-48d3-9451-1c54cbfb3df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591324151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.1591324151
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.2056419520
Short name T372
Test name
Test status
Simulation time 256414744 ps
CPU time 4.56 seconds
Started Jun 10 05:52:44 PM PDT 24
Finished Jun 10 05:52:48 PM PDT 24
Peak memory 224800 kb
Host smart-2526105e-9d0b-4c36-b182-42f0586de0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056419520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.2056419520
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.2973820641
Short name T492
Test name
Test status
Simulation time 717409585 ps
CPU time 7.52 seconds
Started Jun 10 05:52:37 PM PDT 24
Finished Jun 10 05:52:45 PM PDT 24
Peak memory 224772 kb
Host smart-d0c243ac-499d-49b2-91d2-c141839941dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973820641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.2973820641
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.2947315375
Short name T922
Test name
Test status
Simulation time 65574364795 ps
CPU time 149.77 seconds
Started Jun 10 05:52:38 PM PDT 24
Finished Jun 10 05:55:08 PM PDT 24
Peak memory 233056 kb
Host smart-d1fe73ac-6798-49da-aca6-22cd25955577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947315375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.2947315375
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.3001775415
Short name T665
Test name
Test status
Simulation time 1887411349 ps
CPU time 6.98 seconds
Started Jun 10 05:52:40 PM PDT 24
Finished Jun 10 05:52:48 PM PDT 24
Peak memory 232924 kb
Host smart-75e61792-e545-486c-9fc0-7681d8f26d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001775415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.3001775415
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.1821564756
Short name T265
Test name
Test status
Simulation time 21731734647 ps
CPU time 10.18 seconds
Started Jun 10 05:52:36 PM PDT 24
Finished Jun 10 05:52:47 PM PDT 24
Peak memory 233076 kb
Host smart-1a5704ad-9eff-4053-8275-c2acb670e711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821564756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.1821564756
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.3689396554
Short name T760
Test name
Test status
Simulation time 7289802332 ps
CPU time 9.81 seconds
Started Jun 10 05:52:44 PM PDT 24
Finished Jun 10 05:52:54 PM PDT 24
Peak memory 223444 kb
Host smart-e6041e68-29d6-459c-b932-d74d584105da
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3689396554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.3689396554
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.889890825
Short name T854
Test name
Test status
Simulation time 1852543195 ps
CPU time 29.68 seconds
Started Jun 10 05:52:47 PM PDT 24
Finished Jun 10 05:53:17 PM PDT 24
Peak memory 216908 kb
Host smart-8d0f104e-caff-447f-b489-12eb02784369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889890825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.889890825
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1097940641
Short name T475
Test name
Test status
Simulation time 4011949744 ps
CPU time 10.92 seconds
Started Jun 10 05:52:36 PM PDT 24
Finished Jun 10 05:52:48 PM PDT 24
Peak memory 216728 kb
Host smart-d836943c-5b06-4337-a0d0-d57d7cd0e1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097940641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1097940641
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.354978226
Short name T669
Test name
Test status
Simulation time 38101403 ps
CPU time 2.57 seconds
Started Jun 10 05:52:53 PM PDT 24
Finished Jun 10 05:52:57 PM PDT 24
Peak memory 216496 kb
Host smart-306ecbdc-f893-49d4-ba2d-e48d76fd30b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354978226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.354978226
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.1216209818
Short name T927
Test name
Test status
Simulation time 271808638 ps
CPU time 0.99 seconds
Started Jun 10 05:52:40 PM PDT 24
Finished Jun 10 05:52:42 PM PDT 24
Peak memory 206724 kb
Host smart-fa5a818e-ba66-4dca-9007-7b5a757e1b8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216209818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.1216209818
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.1839136989
Short name T614
Test name
Test status
Simulation time 1887507724 ps
CPU time 12.32 seconds
Started Jun 10 05:52:47 PM PDT 24
Finished Jun 10 05:52:59 PM PDT 24
Peak memory 240992 kb
Host smart-3621ded5-3aa3-4371-8c8c-d5dd4faf78c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839136989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1839136989
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.1724286854
Short name T915
Test name
Test status
Simulation time 11007708 ps
CPU time 0.71 seconds
Started Jun 10 05:52:46 PM PDT 24
Finished Jun 10 05:52:48 PM PDT 24
Peak memory 205108 kb
Host smart-263448e8-0e30-42f8-b743-44c21b25d4cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724286854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
1724286854
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.725172614
Short name T198
Test name
Test status
Simulation time 124930412 ps
CPU time 2.54 seconds
Started Jun 10 05:52:49 PM PDT 24
Finished Jun 10 05:52:52 PM PDT 24
Peak memory 233020 kb
Host smart-ee8250f2-1672-4955-8f28-78c60f60925e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725172614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.725172614
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.578063158
Short name T573
Test name
Test status
Simulation time 21813110 ps
CPU time 0.8 seconds
Started Jun 10 05:52:42 PM PDT 24
Finished Jun 10 05:52:43 PM PDT 24
Peak memory 206892 kb
Host smart-7bfac92a-77f5-4ba6-b777-9db8108714a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578063158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.578063158
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.2065993058
Short name T692
Test name
Test status
Simulation time 13569460 ps
CPU time 0.77 seconds
Started Jun 10 05:52:47 PM PDT 24
Finished Jun 10 05:52:48 PM PDT 24
Peak memory 215948 kb
Host smart-0734a442-d94c-4395-a865-0f60514a5fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065993058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.2065993058
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.3043355864
Short name T488
Test name
Test status
Simulation time 104372910 ps
CPU time 2.75 seconds
Started Jun 10 05:52:44 PM PDT 24
Finished Jun 10 05:52:47 PM PDT 24
Peak memory 224732 kb
Host smart-a618fcdb-cfac-4769-bb17-94d1ce4a597c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043355864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.3043355864
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2927501994
Short name T195
Test name
Test status
Simulation time 1315236841 ps
CPU time 7.45 seconds
Started Jun 10 05:52:40 PM PDT 24
Finished Jun 10 05:52:48 PM PDT 24
Peak memory 232980 kb
Host smart-69a9f49a-d830-403e-a2fa-40abf56dfce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927501994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2927501994
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.3312555177
Short name T676
Test name
Test status
Simulation time 23098894788 ps
CPU time 54.1 seconds
Started Jun 10 05:52:47 PM PDT 24
Finished Jun 10 05:53:42 PM PDT 24
Peak memory 234112 kb
Host smart-30291ebc-de72-43cb-9f96-3907089ea5aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312555177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3312555177
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.3023940622
Short name T240
Test name
Test status
Simulation time 2016916282 ps
CPU time 8.97 seconds
Started Jun 10 05:52:39 PM PDT 24
Finished Jun 10 05:52:48 PM PDT 24
Peak memory 242684 kb
Host smart-fb7743b8-e425-4e3d-8e10-574083136159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023940622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.3023940622
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.935412502
Short name T775
Test name
Test status
Simulation time 513427088 ps
CPU time 6.91 seconds
Started Jun 10 05:52:42 PM PDT 24
Finished Jun 10 05:52:50 PM PDT 24
Peak memory 224764 kb
Host smart-665a1f69-e3a6-4389-8cad-48266bd302ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935412502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.935412502
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.2217548065
Short name T615
Test name
Test status
Simulation time 908510749 ps
CPU time 8.91 seconds
Started Jun 10 05:52:43 PM PDT 24
Finished Jun 10 05:52:52 PM PDT 24
Peak memory 219200 kb
Host smart-82a2afce-8a5d-4189-beda-82641c8d878e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2217548065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.2217548065
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.3955516427
Short name T232
Test name
Test status
Simulation time 57028040257 ps
CPU time 544.86 seconds
Started Jun 10 05:52:51 PM PDT 24
Finished Jun 10 06:01:57 PM PDT 24
Peak memory 249576 kb
Host smart-ef496050-3635-48e5-9e69-7a02a2be6af6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955516427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.3955516427
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.2521299547
Short name T320
Test name
Test status
Simulation time 17476440481 ps
CPU time 30.91 seconds
Started Jun 10 05:52:46 PM PDT 24
Finished Jun 10 05:53:17 PM PDT 24
Peak memory 217000 kb
Host smart-518843d9-83c8-4c14-8f8c-3ba8bfe0b5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521299547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.2521299547
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.3234372661
Short name T4
Test name
Test status
Simulation time 744152827 ps
CPU time 4.6 seconds
Started Jun 10 05:52:44 PM PDT 24
Finished Jun 10 05:52:49 PM PDT 24
Peak memory 216576 kb
Host smart-937f4a3d-2835-4526-9bfd-31eaf9b7ae75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234372661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3234372661
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2174356185
Short name T486
Test name
Test status
Simulation time 45610013 ps
CPU time 1.3 seconds
Started Jun 10 05:52:47 PM PDT 24
Finished Jun 10 05:52:49 PM PDT 24
Peak memory 216560 kb
Host smart-d12438e8-4444-4eb1-8bd3-f800ca37495e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174356185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2174356185
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.1533575687
Short name T509
Test name
Test status
Simulation time 29387638 ps
CPU time 0.77 seconds
Started Jun 10 05:52:40 PM PDT 24
Finished Jun 10 05:52:41 PM PDT 24
Peak memory 206184 kb
Host smart-e5190d91-12a9-4ee5-8e9c-c06f8071639f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533575687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.1533575687
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.2728562196
Short name T677
Test name
Test status
Simulation time 55697488 ps
CPU time 2.05 seconds
Started Jun 10 05:52:49 PM PDT 24
Finished Jun 10 05:52:52 PM PDT 24
Peak memory 224576 kb
Host smart-4d6c895d-339f-4ba3-a54d-e36d3b80b326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728562196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2728562196
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.3228108676
Short name T396
Test name
Test status
Simulation time 36303251 ps
CPU time 0.69 seconds
Started Jun 10 05:52:54 PM PDT 24
Finished Jun 10 05:52:55 PM PDT 24
Peak memory 206100 kb
Host smart-4c995033-01e0-487e-9652-3f41693025cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228108676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
3228108676
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.2581915205
Short name T209
Test name
Test status
Simulation time 104667623 ps
CPU time 3.3 seconds
Started Jun 10 05:52:51 PM PDT 24
Finished Jun 10 05:52:55 PM PDT 24
Peak memory 224832 kb
Host smart-a771c597-f038-4724-a912-1d5a76aac938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581915205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2581915205
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.1033755144
Short name T359
Test name
Test status
Simulation time 16458470 ps
CPU time 0.81 seconds
Started Jun 10 05:52:46 PM PDT 24
Finished Jun 10 05:52:47 PM PDT 24
Peak memory 206864 kb
Host smart-512f0d90-c655-4520-b26e-ba39fe76b82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033755144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.1033755144
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.689701230
Short name T935
Test name
Test status
Simulation time 4132928164 ps
CPU time 26.05 seconds
Started Jun 10 05:52:47 PM PDT 24
Finished Jun 10 05:53:13 PM PDT 24
Peak memory 255380 kb
Host smart-1eb59a70-0902-4072-8fe1-bc4cf8692b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689701230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.689701230
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.2496491800
Short name T682
Test name
Test status
Simulation time 17126298769 ps
CPU time 54.21 seconds
Started Jun 10 05:52:47 PM PDT 24
Finished Jun 10 05:53:42 PM PDT 24
Peak memory 249616 kb
Host smart-8456fcf9-996b-4e82-ae87-54a933ec2c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2496491800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.2496491800
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.1537371573
Short name T546
Test name
Test status
Simulation time 12838369831 ps
CPU time 166.11 seconds
Started Jun 10 05:52:42 PM PDT 24
Finished Jun 10 05:55:29 PM PDT 24
Peak memory 249616 kb
Host smart-7cab34d7-46b1-4d65-91c0-0469aac80b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537371573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.1537371573
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.1770674600
Short name T349
Test name
Test status
Simulation time 281282820 ps
CPU time 2.55 seconds
Started Jun 10 05:52:51 PM PDT 24
Finished Jun 10 05:52:54 PM PDT 24
Peak memory 224768 kb
Host smart-26a487a5-e156-48d8-8351-b7e4ebfccd8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770674600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.1770674600
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.2615783346
Short name T254
Test name
Test status
Simulation time 170234556 ps
CPU time 3.2 seconds
Started Jun 10 05:52:50 PM PDT 24
Finished Jun 10 05:52:54 PM PDT 24
Peak memory 224788 kb
Host smart-052620fc-e9d5-4e9d-a26a-d16e736e74d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615783346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2615783346
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.4271772521
Short name T522
Test name
Test status
Simulation time 2161708418 ps
CPU time 9.03 seconds
Started Jun 10 05:52:55 PM PDT 24
Finished Jun 10 05:53:04 PM PDT 24
Peak memory 241224 kb
Host smart-45a795ea-74ef-47ff-ba17-c932add55a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271772521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.4271772521
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3836701214
Short name T204
Test name
Test status
Simulation time 2203596315 ps
CPU time 14.99 seconds
Started Jun 10 05:53:03 PM PDT 24
Finished Jun 10 05:53:18 PM PDT 24
Peak memory 224856 kb
Host smart-ae246a14-c054-4037-a637-81cdb2a12c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836701214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3836701214
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1250556344
Short name T536
Test name
Test status
Simulation time 148820701 ps
CPU time 2.34 seconds
Started Jun 10 05:52:55 PM PDT 24
Finished Jun 10 05:52:58 PM PDT 24
Peak memory 232976 kb
Host smart-2bc67ca9-c8b5-4978-a31d-ea8ca7fa9562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250556344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1250556344
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.4044748733
Short name T683
Test name
Test status
Simulation time 2248759908 ps
CPU time 12.95 seconds
Started Jun 10 05:52:53 PM PDT 24
Finished Jun 10 05:53:06 PM PDT 24
Peak memory 220744 kb
Host smart-09f6b514-20cf-466d-bdfa-df5a2d8f529d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4044748733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.4044748733
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.4283870282
Short name T220
Test name
Test status
Simulation time 48023577473 ps
CPU time 103.15 seconds
Started Jun 10 05:52:46 PM PDT 24
Finished Jun 10 05:54:30 PM PDT 24
Peak memory 234792 kb
Host smart-00bfa1ae-40cd-4141-b8c9-95a8e50864be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283870282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.4283870282
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.4073568948
Short name T590
Test name
Test status
Simulation time 1725518535 ps
CPU time 21.25 seconds
Started Jun 10 05:52:43 PM PDT 24
Finished Jun 10 05:53:05 PM PDT 24
Peak memory 220320 kb
Host smart-deeaf7bd-0a36-4b0b-8c06-13031e369efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073568948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.4073568948
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.4031055558
Short name T408
Test name
Test status
Simulation time 539439740 ps
CPU time 3.7 seconds
Started Jun 10 05:52:53 PM PDT 24
Finished Jun 10 05:52:57 PM PDT 24
Peak memory 216600 kb
Host smart-73a123bf-2003-41fb-86e8-cacde84cbdf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031055558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.4031055558
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.4054240665
Short name T691
Test name
Test status
Simulation time 543989988 ps
CPU time 3.31 seconds
Started Jun 10 05:52:46 PM PDT 24
Finished Jun 10 05:52:50 PM PDT 24
Peak memory 216616 kb
Host smart-16188bb1-04cc-4ed2-baa7-b0b0f816a426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054240665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.4054240665
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.3927530974
Short name T857
Test name
Test status
Simulation time 408790777 ps
CPU time 0.77 seconds
Started Jun 10 05:52:53 PM PDT 24
Finished Jun 10 05:52:54 PM PDT 24
Peak memory 206020 kb
Host smart-7a8663b4-6626-4ae3-9f3b-f4d87ea80836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927530974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.3927530974
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.2929410702
Short name T541
Test name
Test status
Simulation time 130772014 ps
CPU time 2.61 seconds
Started Jun 10 05:52:47 PM PDT 24
Finished Jun 10 05:52:50 PM PDT 24
Peak memory 224616 kb
Host smart-68a4a308-29e7-4347-8ddb-8fdb4371c7d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929410702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.2929410702
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.4140499738
Short name T582
Test name
Test status
Simulation time 13065754 ps
CPU time 0.71 seconds
Started Jun 10 05:52:55 PM PDT 24
Finished Jun 10 05:52:56 PM PDT 24
Peak memory 205200 kb
Host smart-747105ae-b5a2-4fe2-a772-2bd22ddfbd2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140499738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
4140499738
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.542820849
Short name T476
Test name
Test status
Simulation time 41709133 ps
CPU time 2.08 seconds
Started Jun 10 05:52:52 PM PDT 24
Finished Jun 10 05:52:54 PM PDT 24
Peak memory 224696 kb
Host smart-a605aab1-9cf9-4d17-b8e1-72d4666fad46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542820849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.542820849
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.43283597
Short name T398
Test name
Test status
Simulation time 59127475 ps
CPU time 0.76 seconds
Started Jun 10 05:52:54 PM PDT 24
Finished Jun 10 05:52:55 PM PDT 24
Peak memory 206888 kb
Host smart-404fccd8-60b1-4566-a4bd-3c916766b202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43283597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.43283597
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.2172458851
Short name T584
Test name
Test status
Simulation time 3520545640 ps
CPU time 25.66 seconds
Started Jun 10 05:52:52 PM PDT 24
Finished Jun 10 05:53:19 PM PDT 24
Peak memory 237720 kb
Host smart-317fa862-fa84-4cf3-92fa-6f9ff35cf10c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172458851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.2172458851
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.280386545
Short name T809
Test name
Test status
Simulation time 20298062414 ps
CPU time 34.75 seconds
Started Jun 10 05:52:52 PM PDT 24
Finished Jun 10 05:53:28 PM PDT 24
Peak memory 223088 kb
Host smart-7eb30b53-5cb5-4cec-a47d-2bb65c267f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280386545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.280386545
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.4294278298
Short name T216
Test name
Test status
Simulation time 20707238018 ps
CPU time 105.8 seconds
Started Jun 10 05:52:53 PM PDT 24
Finished Jun 10 05:54:39 PM PDT 24
Peak memory 251728 kb
Host smart-00c0be55-382c-46bf-b92b-4b7d081b5d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294278298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.4294278298
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.2778274439
Short name T312
Test name
Test status
Simulation time 2403603743 ps
CPU time 31.79 seconds
Started Jun 10 05:52:49 PM PDT 24
Finished Jun 10 05:53:22 PM PDT 24
Peak memory 234516 kb
Host smart-dbe1adef-da42-4890-a55d-4541baea1d37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778274439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.2778274439
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.1328927617
Short name T201
Test name
Test status
Simulation time 4084921380 ps
CPU time 15.42 seconds
Started Jun 10 05:52:57 PM PDT 24
Finished Jun 10 05:53:13 PM PDT 24
Peak memory 224816 kb
Host smart-bdabd9c7-10e4-43a5-8100-9d9a93110f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328927617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.1328927617
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3791007520
Short name T838
Test name
Test status
Simulation time 694106653 ps
CPU time 4.17 seconds
Started Jun 10 05:52:52 PM PDT 24
Finished Jun 10 05:52:57 PM PDT 24
Peak memory 233032 kb
Host smart-df9e9c28-3217-47b8-9c22-292d591c7b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3791007520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3791007520
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.879199900
Short name T38
Test name
Test status
Simulation time 11815128115 ps
CPU time 18.07 seconds
Started Jun 10 05:52:57 PM PDT 24
Finished Jun 10 05:53:15 PM PDT 24
Peak memory 233132 kb
Host smart-74e73069-13fa-4d5f-8ed9-133375ab43cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879199900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap
.879199900
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.744856953
Short name T275
Test name
Test status
Simulation time 1787929933 ps
CPU time 7.02 seconds
Started Jun 10 05:52:51 PM PDT 24
Finished Jun 10 05:52:58 PM PDT 24
Peak memory 233032 kb
Host smart-f8ff5d09-e89c-4f4d-8080-a6483cfe37b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744856953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.744856953
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.1922759916
Short name T894
Test name
Test status
Simulation time 1509659884 ps
CPU time 9.95 seconds
Started Jun 10 05:53:01 PM PDT 24
Finished Jun 10 05:53:11 PM PDT 24
Peak memory 220752 kb
Host smart-0a55aee4-79ae-4c4d-bdb8-0acc5e6d3826
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1922759916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.1922759916
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.4067248087
Short name T670
Test name
Test status
Simulation time 8661256640 ps
CPU time 85.47 seconds
Started Jun 10 05:53:09 PM PDT 24
Finished Jun 10 05:54:35 PM PDT 24
Peak memory 240888 kb
Host smart-fec33783-0956-47cb-84b2-106a69555ff1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067248087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.4067248087
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.2017023239
Short name T26
Test name
Test status
Simulation time 14693066390 ps
CPU time 27.88 seconds
Started Jun 10 05:52:55 PM PDT 24
Finished Jun 10 05:53:24 PM PDT 24
Peak memory 216676 kb
Host smart-1cf4b320-9e73-4a1f-a827-767f6d8502b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017023239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.2017023239
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.401262857
Short name T519
Test name
Test status
Simulation time 27120006 ps
CPU time 0.73 seconds
Started Jun 10 05:52:46 PM PDT 24
Finished Jun 10 05:52:47 PM PDT 24
Peak memory 206028 kb
Host smart-f5717a00-9e1d-4b0a-87aa-08288606e968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=401262857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.401262857
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.3982410490
Short name T598
Test name
Test status
Simulation time 114548507 ps
CPU time 3.15 seconds
Started Jun 10 05:53:01 PM PDT 24
Finished Jun 10 05:53:05 PM PDT 24
Peak memory 216616 kb
Host smart-b93cda94-5781-41f1-b78d-a65709128056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982410490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.3982410490
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.3270945734
Short name T539
Test name
Test status
Simulation time 66644884 ps
CPU time 0.89 seconds
Started Jun 10 05:52:48 PM PDT 24
Finished Jun 10 05:52:49 PM PDT 24
Peak memory 206184 kb
Host smart-6684fc7b-1eee-4ba5-aad7-411e6049bae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270945734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.3270945734
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.794478417
Short name T558
Test name
Test status
Simulation time 475711064 ps
CPU time 6.48 seconds
Started Jun 10 05:52:50 PM PDT 24
Finished Jun 10 05:52:57 PM PDT 24
Peak memory 232912 kb
Host smart-9491217e-7513-4a11-a9fc-880e010f4727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794478417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.794478417
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.96159467
Short name T477
Test name
Test status
Simulation time 45899057 ps
CPU time 0.77 seconds
Started Jun 10 05:52:57 PM PDT 24
Finished Jun 10 05:52:58 PM PDT 24
Peak memory 205752 kb
Host smart-c4438a4f-d08c-4a26-9c29-b87c44822fb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96159467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.96159467
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.4288241101
Short name T169
Test name
Test status
Simulation time 183208118 ps
CPU time 2.86 seconds
Started Jun 10 05:52:53 PM PDT 24
Finished Jun 10 05:52:57 PM PDT 24
Peak memory 233020 kb
Host smart-16f3c88b-29b1-43f1-9fa8-dfc09154b03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288241101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.4288241101
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.1528116883
Short name T694
Test name
Test status
Simulation time 107967599 ps
CPU time 0.74 seconds
Started Jun 10 05:53:07 PM PDT 24
Finished Jun 10 05:53:08 PM PDT 24
Peak memory 207128 kb
Host smart-92092e81-404e-48f6-ae7b-c745e979a65e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528116883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1528116883
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.3279467481
Short name T277
Test name
Test status
Simulation time 186768016069 ps
CPU time 213.12 seconds
Started Jun 10 05:52:55 PM PDT 24
Finished Jun 10 05:56:29 PM PDT 24
Peak memory 249520 kb
Host smart-c64a1a62-3dd1-4950-a05b-fd2588913ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279467481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.3279467481
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.3709527233
Short name T260
Test name
Test status
Simulation time 2369368226 ps
CPU time 59.3 seconds
Started Jun 10 05:53:04 PM PDT 24
Finished Jun 10 05:54:04 PM PDT 24
Peak memory 255376 kb
Host smart-dfbfc6c9-18b3-4aa3-9137-f8b491c6d1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709527233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3709527233
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.2047549228
Short name T52
Test name
Test status
Simulation time 23559612555 ps
CPU time 248.96 seconds
Started Jun 10 05:52:57 PM PDT 24
Finished Jun 10 05:57:06 PM PDT 24
Peak memory 257692 kb
Host smart-6b95878d-04c2-4dee-bf25-9caa55417266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047549228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.2047549228
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.4093515361
Short name T699
Test name
Test status
Simulation time 62057955 ps
CPU time 2.75 seconds
Started Jun 10 05:52:56 PM PDT 24
Finished Jun 10 05:52:59 PM PDT 24
Peak memory 232940 kb
Host smart-1f938cce-94cf-4bcb-8a37-cbb09e30086f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093515361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.4093515361
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.770964116
Short name T555
Test name
Test status
Simulation time 2238727567 ps
CPU time 7.41 seconds
Started Jun 10 05:53:04 PM PDT 24
Finished Jun 10 05:53:12 PM PDT 24
Peak memory 224884 kb
Host smart-40d12b7f-71d6-4ddc-a01d-75ff198ed919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770964116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.770964116
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.3917907523
Short name T861
Test name
Test status
Simulation time 6623265170 ps
CPU time 18.21 seconds
Started Jun 10 05:52:57 PM PDT 24
Finished Jun 10 05:53:15 PM PDT 24
Peak memory 233152 kb
Host smart-43bdc72a-5920-439e-9d2c-b844b0044559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917907523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3917907523
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2502665311
Short name T495
Test name
Test status
Simulation time 27153451916 ps
CPU time 20.02 seconds
Started Jun 10 05:52:49 PM PDT 24
Finished Jun 10 05:53:10 PM PDT 24
Peak memory 233148 kb
Host smart-fea492e7-8f4e-406a-bb28-103aafbb47b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502665311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2502665311
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.2528557747
Short name T297
Test name
Test status
Simulation time 394538471 ps
CPU time 5.76 seconds
Started Jun 10 05:52:59 PM PDT 24
Finished Jun 10 05:53:05 PM PDT 24
Peak memory 224716 kb
Host smart-5e4f7110-3b7c-41f0-a84b-b87a94ab5af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528557747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.2528557747
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.3228807427
Short name T884
Test name
Test status
Simulation time 524874368 ps
CPU time 4.82 seconds
Started Jun 10 05:52:52 PM PDT 24
Finished Jun 10 05:52:57 PM PDT 24
Peak memory 223300 kb
Host smart-a7ce2e98-6348-4006-99bb-db491498e26b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3228807427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.3228807427
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.3032788671
Short name T787
Test name
Test status
Simulation time 3302688726 ps
CPU time 21.63 seconds
Started Jun 10 05:52:52 PM PDT 24
Finished Jun 10 05:53:14 PM PDT 24
Peak memory 220296 kb
Host smart-fec585b5-ecca-4bfd-835c-7499712f05d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032788671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3032788671
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.1891038429
Short name T474
Test name
Test status
Simulation time 3938280668 ps
CPU time 3.9 seconds
Started Jun 10 05:52:59 PM PDT 24
Finished Jun 10 05:53:03 PM PDT 24
Peak memory 216756 kb
Host smart-6b37a031-4344-4e68-9f7a-37cd1c802ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891038429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.1891038429
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.1280494969
Short name T348
Test name
Test status
Simulation time 1249252379 ps
CPU time 3.13 seconds
Started Jun 10 05:52:55 PM PDT 24
Finished Jun 10 05:52:59 PM PDT 24
Peak memory 216628 kb
Host smart-938638c5-e24a-4c71-9e85-4185e848479b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280494969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1280494969
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.3105368672
Short name T879
Test name
Test status
Simulation time 93462181 ps
CPU time 1.12 seconds
Started Jun 10 05:52:50 PM PDT 24
Finished Jun 10 05:52:51 PM PDT 24
Peak memory 206672 kb
Host smart-f290fa97-d543-4384-afcd-7e1215a9bc72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105368672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3105368672
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.1563410531
Short name T940
Test name
Test status
Simulation time 14094363307 ps
CPU time 12.12 seconds
Started Jun 10 05:53:02 PM PDT 24
Finished Jun 10 05:53:15 PM PDT 24
Peak memory 241348 kb
Host smart-e9dbd46c-41e6-47af-8f2c-4e90535615c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563410531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1563410531
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.3190756072
Short name T697
Test name
Test status
Simulation time 41884062 ps
CPU time 0.81 seconds
Started Jun 10 05:53:02 PM PDT 24
Finished Jun 10 05:53:03 PM PDT 24
Peak memory 205660 kb
Host smart-71092bbb-5854-4a5b-95b1-61276cd3512b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190756072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
3190756072
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.809853772
Short name T871
Test name
Test status
Simulation time 1837076721 ps
CPU time 17.65 seconds
Started Jun 10 05:52:54 PM PDT 24
Finished Jun 10 05:53:12 PM PDT 24
Peak memory 233016 kb
Host smart-8dee44f4-4423-4850-91f1-5c57ddbf68dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809853772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.809853772
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.3095639750
Short name T606
Test name
Test status
Simulation time 158213006 ps
CPU time 0.77 seconds
Started Jun 10 05:52:59 PM PDT 24
Finished Jun 10 05:53:00 PM PDT 24
Peak memory 205824 kb
Host smart-08fb7ea2-7de4-47f9-8afb-f32539258370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095639750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.3095639750
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.3488043746
Short name T617
Test name
Test status
Simulation time 74218147777 ps
CPU time 260.23 seconds
Started Jun 10 05:52:54 PM PDT 24
Finished Jun 10 05:57:15 PM PDT 24
Peak memory 249536 kb
Host smart-2d773111-3579-4ab7-9a53-018760bb12e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488043746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.3488043746
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.1806220013
Short name T302
Test name
Test status
Simulation time 2224080368 ps
CPU time 34.32 seconds
Started Jun 10 05:53:11 PM PDT 24
Finished Jun 10 05:53:45 PM PDT 24
Peak memory 224940 kb
Host smart-09bdd187-5e77-4ee9-9f40-43d19f710992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806220013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.1806220013
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.1856608803
Short name T324
Test name
Test status
Simulation time 25861912983 ps
CPU time 110.21 seconds
Started Jun 10 05:52:55 PM PDT 24
Finished Jun 10 05:54:46 PM PDT 24
Peak memory 255712 kb
Host smart-c378a146-b519-4873-ad30-dd7880855b66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856608803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.1856608803
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.3306470252
Short name T337
Test name
Test status
Simulation time 856779320 ps
CPU time 9.2 seconds
Started Jun 10 05:53:01 PM PDT 24
Finished Jun 10 05:53:11 PM PDT 24
Peak memory 224724 kb
Host smart-e1ead4c5-ae76-4d7d-b3e2-e04a07cdd0e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306470252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.3306470252
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.2820184311
Short name T196
Test name
Test status
Simulation time 1614076884 ps
CPU time 12.19 seconds
Started Jun 10 05:52:58 PM PDT 24
Finished Jun 10 05:53:11 PM PDT 24
Peak memory 232992 kb
Host smart-cd8e16a1-eda9-4f0d-86df-2a723157adbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820184311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.2820184311
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.707537839
Short name T720
Test name
Test status
Simulation time 11808107643 ps
CPU time 44.98 seconds
Started Jun 10 05:52:54 PM PDT 24
Finished Jun 10 05:53:40 PM PDT 24
Peak memory 249504 kb
Host smart-24ee7daf-5f82-4247-b7f2-576cdc07bbfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707537839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.707537839
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.3885932071
Short name T660
Test name
Test status
Simulation time 8928291997 ps
CPU time 9.78 seconds
Started Jun 10 05:53:04 PM PDT 24
Finished Jun 10 05:53:14 PM PDT 24
Peak memory 233068 kb
Host smart-370ef2a1-07e0-405f-8ab1-029fbe512c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885932071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.3885932071
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2145772096
Short name T626
Test name
Test status
Simulation time 23067336438 ps
CPU time 22.7 seconds
Started Jun 10 05:53:10 PM PDT 24
Finished Jun 10 05:53:34 PM PDT 24
Peak memory 233072 kb
Host smart-b9d81e35-3d17-4580-9970-f8ccaa4ad64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145772096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2145772096
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.101986203
Short name T47
Test name
Test status
Simulation time 7299490840 ps
CPU time 16.85 seconds
Started Jun 10 05:53:03 PM PDT 24
Finished Jun 10 05:53:20 PM PDT 24
Peak memory 219824 kb
Host smart-1583e546-37fc-4268-9558-ec3dae626474
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=101986203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dire
ct.101986203
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.3994365069
Short name T746
Test name
Test status
Simulation time 167209369 ps
CPU time 1 seconds
Started Jun 10 05:52:54 PM PDT 24
Finished Jun 10 05:52:56 PM PDT 24
Peak memory 207832 kb
Host smart-9469061a-691f-4789-9f50-bb0a46ca4efa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994365069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.3994365069
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.1415104358
Short name T468
Test name
Test status
Simulation time 11785027294 ps
CPU time 35.34 seconds
Started Jun 10 05:52:50 PM PDT 24
Finished Jun 10 05:53:26 PM PDT 24
Peak memory 216936 kb
Host smart-a015f933-af4d-4630-a35d-8cbe8f9febcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415104358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1415104358
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.1465213421
Short name T518
Test name
Test status
Simulation time 1879471993 ps
CPU time 10.64 seconds
Started Jun 10 05:53:03 PM PDT 24
Finished Jun 10 05:53:14 PM PDT 24
Peak memory 216536 kb
Host smart-2e08a353-f84a-4a96-aaad-d114bf27091c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465213421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.1465213421
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.556160360
Short name T786
Test name
Test status
Simulation time 144191299 ps
CPU time 1.98 seconds
Started Jun 10 05:52:55 PM PDT 24
Finished Jun 10 05:52:57 PM PDT 24
Peak memory 216568 kb
Host smart-ffcb8cd3-b01f-4c07-88f7-bd845c017539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556160360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.556160360
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.1355018850
Short name T470
Test name
Test status
Simulation time 31821482 ps
CPU time 0.87 seconds
Started Jun 10 05:52:57 PM PDT 24
Finished Jun 10 05:52:59 PM PDT 24
Peak memory 206448 kb
Host smart-4583c04d-2547-43f2-93cb-fecc1a6623c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355018850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.1355018850
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.1708623094
Short name T267
Test name
Test status
Simulation time 6612374595 ps
CPU time 10.53 seconds
Started Jun 10 05:53:01 PM PDT 24
Finished Jun 10 05:53:12 PM PDT 24
Peak memory 239380 kb
Host smart-48bddafc-b564-4942-abec-ed7b6bab2660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708623094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1708623094
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.2017111442
Short name T811
Test name
Test status
Simulation time 84108941 ps
CPU time 0.76 seconds
Started Jun 10 05:51:11 PM PDT 24
Finished Jun 10 05:51:12 PM PDT 24
Peak memory 205772 kb
Host smart-9ca508ba-761f-43fa-8e0c-0f9497e440da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017111442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2
017111442
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.2011348370
Short name T333
Test name
Test status
Simulation time 76720237 ps
CPU time 2.28 seconds
Started Jun 10 05:51:05 PM PDT 24
Finished Jun 10 05:51:07 PM PDT 24
Peak memory 223576 kb
Host smart-900b30f5-e6ed-4bee-b31b-54c826e5bc48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011348370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2011348370
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.107748588
Short name T516
Test name
Test status
Simulation time 20175556 ps
CPU time 0.81 seconds
Started Jun 10 05:51:16 PM PDT 24
Finished Jun 10 05:51:17 PM PDT 24
Peak memory 206932 kb
Host smart-4f4f8b99-784d-4f0b-8a0a-04e7710c2a1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107748588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.107748588
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.1556905394
Short name T718
Test name
Test status
Simulation time 17903269600 ps
CPU time 119.4 seconds
Started Jun 10 05:51:08 PM PDT 24
Finished Jun 10 05:53:08 PM PDT 24
Peak memory 249580 kb
Host smart-9af65b1e-3b73-462a-9f34-1258e0cd699f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556905394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.1556905394
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.2409826033
Short name T592
Test name
Test status
Simulation time 14683014116 ps
CPU time 10.43 seconds
Started Jun 10 05:51:06 PM PDT 24
Finished Jun 10 05:51:17 PM PDT 24
Peak memory 218012 kb
Host smart-6defdd7e-857f-4412-bf15-0f40e0d7838e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409826033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2409826033
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.3112145953
Short name T389
Test name
Test status
Simulation time 8300082628 ps
CPU time 30.45 seconds
Started Jun 10 05:51:00 PM PDT 24
Finished Jun 10 05:51:31 PM PDT 24
Peak memory 251464 kb
Host smart-10c1d4a3-69ac-4f84-89a9-ddcc2ca1fea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112145953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.3112145953
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.3467928299
Short name T577
Test name
Test status
Simulation time 2425812434 ps
CPU time 22.09 seconds
Started Jun 10 05:51:00 PM PDT 24
Finished Jun 10 05:51:23 PM PDT 24
Peak memory 233092 kb
Host smart-a5116595-d99e-47a5-bca7-3277614d0f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467928299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3467928299
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.1581994060
Short name T896
Test name
Test status
Simulation time 3524620866 ps
CPU time 30.84 seconds
Started Jun 10 05:51:08 PM PDT 24
Finished Jun 10 05:51:39 PM PDT 24
Peak memory 233032 kb
Host smart-4a2df2e6-25f1-4224-a948-9d543456405f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581994060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1581994060
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.157217447
Short name T686
Test name
Test status
Simulation time 268090306 ps
CPU time 2.33 seconds
Started Jun 10 05:51:13 PM PDT 24
Finished Jun 10 05:51:16 PM PDT 24
Peak memory 223288 kb
Host smart-8e83d526-8581-461d-b74b-d246288aa126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=157217447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.
157217447
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.120509006
Short name T281
Test name
Test status
Simulation time 907694533 ps
CPU time 4.11 seconds
Started Jun 10 05:51:00 PM PDT 24
Finished Jun 10 05:51:04 PM PDT 24
Peak memory 224796 kb
Host smart-43a67754-1223-44b5-a11a-753094605ebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120509006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.120509006
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.1418788645
Short name T553
Test name
Test status
Simulation time 521757614 ps
CPU time 8.05 seconds
Started Jun 10 05:51:08 PM PDT 24
Finished Jun 10 05:51:16 PM PDT 24
Peak memory 222552 kb
Host smart-f8e79707-7368-44c8-8419-3b1aaefdae22
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1418788645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.1418788645
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.1360476935
Short name T75
Test name
Test status
Simulation time 302336462 ps
CPU time 0.98 seconds
Started Jun 10 05:51:10 PM PDT 24
Finished Jun 10 05:51:11 PM PDT 24
Peak memory 235260 kb
Host smart-5e3bd73e-5d7b-46f3-a247-dc3b0e97588c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360476935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1360476935
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.2109403842
Short name T471
Test name
Test status
Simulation time 37490651 ps
CPU time 1.07 seconds
Started Jun 10 05:51:04 PM PDT 24
Finished Jun 10 05:51:06 PM PDT 24
Peak memory 207324 kb
Host smart-42902092-348c-43e7-a750-755b1e978221
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109403842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.2109403842
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.3602033910
Short name T323
Test name
Test status
Simulation time 52398864239 ps
CPU time 40.92 seconds
Started Jun 10 05:51:01 PM PDT 24
Finished Jun 10 05:51:42 PM PDT 24
Peak memory 216756 kb
Host smart-78931340-bfb5-4ebe-815e-3f5fa8622353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602033910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.3602033910
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.1551153192
Short name T893
Test name
Test status
Simulation time 11186353169 ps
CPU time 10.66 seconds
Started Jun 10 05:51:05 PM PDT 24
Finished Jun 10 05:51:16 PM PDT 24
Peak memory 216768 kb
Host smart-bd56f88d-417f-4361-817c-6444838fbe2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551153192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.1551153192
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.3042941171
Short name T858
Test name
Test status
Simulation time 77222950 ps
CPU time 2.57 seconds
Started Jun 10 05:51:07 PM PDT 24
Finished Jun 10 05:51:10 PM PDT 24
Peak memory 216572 kb
Host smart-84967a32-cc99-4e0d-9484-451769b783a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042941171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3042941171
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.2380811561
Short name T392
Test name
Test status
Simulation time 33086215 ps
CPU time 0.66 seconds
Started Jun 10 05:51:14 PM PDT 24
Finished Jun 10 05:51:16 PM PDT 24
Peak memory 205920 kb
Host smart-ec4feae7-34e8-426d-a2df-4d139275f214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380811561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.2380811561
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.2429900137
Short name T194
Test name
Test status
Simulation time 6185275992 ps
CPU time 12.15 seconds
Started Jun 10 05:51:04 PM PDT 24
Finished Jun 10 05:51:16 PM PDT 24
Peak memory 224948 kb
Host smart-93520f19-68eb-426f-b6fc-65eee0e0aeb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429900137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.2429900137
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.2727469255
Short name T957
Test name
Test status
Simulation time 44117460 ps
CPU time 0.71 seconds
Started Jun 10 05:53:06 PM PDT 24
Finished Jun 10 05:53:07 PM PDT 24
Peak memory 206088 kb
Host smart-b9130c22-8616-4a91-aa51-fac2ee7ae3d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727469255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
2727469255
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.27004696
Short name T175
Test name
Test status
Simulation time 12457675554 ps
CPU time 14.69 seconds
Started Jun 10 05:53:09 PM PDT 24
Finished Jun 10 05:53:24 PM PDT 24
Peak memory 224968 kb
Host smart-2be39e17-4ecc-4a83-8467-7538ddcdfeef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27004696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.27004696
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.1059335477
Short name T673
Test name
Test status
Simulation time 22165428 ps
CPU time 0.94 seconds
Started Jun 10 05:53:01 PM PDT 24
Finished Jun 10 05:53:03 PM PDT 24
Peak memory 207128 kb
Host smart-541b052a-e21d-4a47-988f-af7d92ac6a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059335477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1059335477
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.1587599025
Short name T33
Test name
Test status
Simulation time 98247498906 ps
CPU time 139.85 seconds
Started Jun 10 05:53:09 PM PDT 24
Finished Jun 10 05:55:35 PM PDT 24
Peak memory 250496 kb
Host smart-df7e1f0e-0489-44cf-b5d9-f2d62fb057a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587599025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.1587599025
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.3595940083
Short name T863
Test name
Test status
Simulation time 953895841 ps
CPU time 10.32 seconds
Started Jun 10 05:52:58 PM PDT 24
Finished Jun 10 05:53:08 PM PDT 24
Peak memory 224812 kb
Host smart-24b40f8d-c900-4cf5-8d92-715ea7ea8344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595940083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.3595940083
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.482913020
Short name T295
Test name
Test status
Simulation time 5680576426 ps
CPU time 13.96 seconds
Started Jun 10 05:53:00 PM PDT 24
Finished Jun 10 05:53:14 PM PDT 24
Peak memory 224812 kb
Host smart-eaeb8a2a-322b-4232-a6f1-d6fee59e2128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482913020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.482913020
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.2422543459
Short name T304
Test name
Test status
Simulation time 3131319787 ps
CPU time 30.09 seconds
Started Jun 10 05:53:05 PM PDT 24
Finished Jun 10 05:53:35 PM PDT 24
Peak memory 241284 kb
Host smart-c68a1132-0d07-45a9-805c-d3193bbae3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422543459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.2422543459
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.1449232922
Short name T597
Test name
Test status
Simulation time 4943071476 ps
CPU time 8.26 seconds
Started Jun 10 05:53:03 PM PDT 24
Finished Jun 10 05:53:12 PM PDT 24
Peak memory 233128 kb
Host smart-93ec3262-5aae-4761-9118-543939048644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449232922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.1449232922
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.4043844412
Short name T100
Test name
Test status
Simulation time 307670199 ps
CPU time 5.53 seconds
Started Jun 10 05:52:59 PM PDT 24
Finished Jun 10 05:53:05 PM PDT 24
Peak memory 233020 kb
Host smart-2705bb1a-94c6-4a1b-b467-53d5b0a0b10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043844412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.4043844412
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.2417591647
Short name T810
Test name
Test status
Simulation time 162485359 ps
CPU time 4.11 seconds
Started Jun 10 05:52:57 PM PDT 24
Finished Jun 10 05:53:01 PM PDT 24
Peak memory 219152 kb
Host smart-346e4a94-8c37-4e6c-a01d-3780068f480e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2417591647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.2417591647
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.4156145101
Short name T51
Test name
Test status
Simulation time 4772376881 ps
CPU time 35.3 seconds
Started Jun 10 05:53:11 PM PDT 24
Finished Jun 10 05:53:47 PM PDT 24
Peak memory 241332 kb
Host smart-3bdcde35-4402-4ec2-9392-5dd6627e21cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156145101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.4156145101
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2464485416
Short name T752
Test name
Test status
Simulation time 2370204514 ps
CPU time 9.91 seconds
Started Jun 10 05:53:11 PM PDT 24
Finished Jun 10 05:53:22 PM PDT 24
Peak memory 216580 kb
Host smart-de647936-993f-4d5a-b542-a107ee7c739e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464485416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2464485416
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.3064547301
Short name T433
Test name
Test status
Simulation time 54656055 ps
CPU time 1.02 seconds
Started Jun 10 05:53:00 PM PDT 24
Finished Jun 10 05:53:01 PM PDT 24
Peak memory 207476 kb
Host smart-96a2fc31-5698-43ae-9b48-d8d16a6227dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064547301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.3064547301
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.2033584052
Short name T346
Test name
Test status
Simulation time 21098695 ps
CPU time 0.8 seconds
Started Jun 10 05:52:56 PM PDT 24
Finished Jun 10 05:52:58 PM PDT 24
Peak memory 206220 kb
Host smart-eae97fc3-dfae-431e-bc22-1252ba87f9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033584052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.2033584052
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.2390114896
Short name T355
Test name
Test status
Simulation time 236911535 ps
CPU time 2.95 seconds
Started Jun 10 05:52:59 PM PDT 24
Finished Jun 10 05:53:02 PM PDT 24
Peak memory 232956 kb
Host smart-c312286e-3e4a-4e2d-809d-c1f2bad862ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390114896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.2390114896
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.4018047119
Short name T66
Test name
Test status
Simulation time 13742422 ps
CPU time 0.74 seconds
Started Jun 10 05:53:04 PM PDT 24
Finished Jun 10 05:53:05 PM PDT 24
Peak memory 205172 kb
Host smart-a5b5663a-7b26-4190-a46f-6cde92ed5625
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018047119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
4018047119
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.1681406079
Short name T208
Test name
Test status
Simulation time 235354555 ps
CPU time 4.62 seconds
Started Jun 10 05:53:13 PM PDT 24
Finished Jun 10 05:53:18 PM PDT 24
Peak memory 224700 kb
Host smart-af690a74-f28a-457d-baeb-7f27b547326b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681406079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.1681406079
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.1416139325
Short name T889
Test name
Test status
Simulation time 19629480 ps
CPU time 0.83 seconds
Started Jun 10 05:52:55 PM PDT 24
Finished Jun 10 05:52:57 PM PDT 24
Peak memory 206900 kb
Host smart-80282a7c-1153-4120-875d-e6ae8d4d6827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416139325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1416139325
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.3486272828
Short name T741
Test name
Test status
Simulation time 23220341425 ps
CPU time 70.54 seconds
Started Jun 10 05:53:14 PM PDT 24
Finished Jun 10 05:54:25 PM PDT 24
Peak memory 250772 kb
Host smart-1da99986-3ada-4d5a-809c-83cdab2ccbc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486272828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.3486272828
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.2142425897
Short name T318
Test name
Test status
Simulation time 14400644547 ps
CPU time 45.29 seconds
Started Jun 10 05:53:10 PM PDT 24
Finished Jun 10 05:53:56 PM PDT 24
Peak memory 239912 kb
Host smart-be2cd95b-b815-422b-a9b5-5ae23c2faaf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142425897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.2142425897
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.515137861
Short name T222
Test name
Test status
Simulation time 293440923895 ps
CPU time 686.47 seconds
Started Jun 10 05:53:03 PM PDT 24
Finished Jun 10 06:04:30 PM PDT 24
Peak memory 257376 kb
Host smart-f6f46ff3-088e-4183-9f11-89f0f93973fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515137861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle
.515137861
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.3058419027
Short name T868
Test name
Test status
Simulation time 13955474905 ps
CPU time 22.86 seconds
Started Jun 10 05:53:03 PM PDT 24
Finished Jun 10 05:53:26 PM PDT 24
Peak memory 233080 kb
Host smart-c78c0dec-1ca1-4cbf-8b88-652e77db144f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058419027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.3058419027
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.1133163601
Short name T667
Test name
Test status
Simulation time 231633435 ps
CPU time 2.77 seconds
Started Jun 10 05:53:06 PM PDT 24
Finished Jun 10 05:53:09 PM PDT 24
Peak memory 233024 kb
Host smart-0bb5da4f-c6a9-4f97-94f7-ed25c096b1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133163601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.1133163601
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2036446788
Short name T581
Test name
Test status
Simulation time 8731909082 ps
CPU time 26.82 seconds
Started Jun 10 05:52:59 PM PDT 24
Finished Jun 10 05:53:27 PM PDT 24
Peak memory 252372 kb
Host smart-610e3b0d-940b-495e-9c50-c0c41c530ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036446788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2036446788
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.177952251
Short name T13
Test name
Test status
Simulation time 1140276523 ps
CPU time 3.25 seconds
Started Jun 10 05:53:14 PM PDT 24
Finished Jun 10 05:53:18 PM PDT 24
Peak memory 224704 kb
Host smart-41fcfdd7-c01a-4aed-a117-d8760ce95fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177952251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap
.177952251
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.276676654
Short name T836
Test name
Test status
Simulation time 1395457670 ps
CPU time 10.45 seconds
Started Jun 10 05:53:08 PM PDT 24
Finished Jun 10 05:53:19 PM PDT 24
Peak memory 241204 kb
Host smart-a5b3d2f4-1627-429c-ac49-da2ded43f73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276676654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.276676654
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.499816519
Short name T141
Test name
Test status
Simulation time 3992282343 ps
CPU time 11.21 seconds
Started Jun 10 05:53:02 PM PDT 24
Finished Jun 10 05:53:14 PM PDT 24
Peak memory 223464 kb
Host smart-64bd7f28-851a-41eb-97de-bcb8337e5af3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=499816519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dire
ct.499816519
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.1381482211
Short name T603
Test name
Test status
Simulation time 42980881590 ps
CPU time 378.62 seconds
Started Jun 10 05:53:02 PM PDT 24
Finished Jun 10 05:59:21 PM PDT 24
Peak memory 250840 kb
Host smart-3ee988d3-c329-431a-8f32-ab9a3214f6b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381482211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.1381482211
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.3765784524
Short name T895
Test name
Test status
Simulation time 38109142080 ps
CPU time 31.11 seconds
Started Jun 10 05:53:14 PM PDT 24
Finished Jun 10 05:53:46 PM PDT 24
Peak memory 216676 kb
Host smart-65f0397a-3a2b-42a7-b1d6-bb92f1e34fe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765784524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.3765784524
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.3919958571
Short name T350
Test name
Test status
Simulation time 4740367328 ps
CPU time 5.92 seconds
Started Jun 10 05:53:14 PM PDT 24
Finished Jun 10 05:53:20 PM PDT 24
Peak memory 216776 kb
Host smart-f4197d40-9ec4-4c95-a886-609d6f58d76e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919958571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.3919958571
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.2063056329
Short name T587
Test name
Test status
Simulation time 63849307 ps
CPU time 3.67 seconds
Started Jun 10 05:52:59 PM PDT 24
Finished Jun 10 05:53:03 PM PDT 24
Peak memory 216600 kb
Host smart-330069ce-998b-47a1-9a48-7b095a0b62cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063056329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.2063056329
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.734890505
Short name T544
Test name
Test status
Simulation time 15392486 ps
CPU time 0.7 seconds
Started Jun 10 05:52:56 PM PDT 24
Finished Jun 10 05:52:57 PM PDT 24
Peak memory 206184 kb
Host smart-22a8da69-da03-4357-8e1a-26c488f50f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734890505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.734890505
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.804913419
Short name T611
Test name
Test status
Simulation time 1677789600 ps
CPU time 5.46 seconds
Started Jun 10 05:52:59 PM PDT 24
Finished Jun 10 05:53:04 PM PDT 24
Peak memory 224816 kb
Host smart-3f9d4d9f-17f7-4fc6-bc1f-2764948759a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804913419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.804913419
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.363733655
Short name T490
Test name
Test status
Simulation time 27321858 ps
CPU time 0.76 seconds
Started Jun 10 05:53:07 PM PDT 24
Finished Jun 10 05:53:08 PM PDT 24
Peak memory 205768 kb
Host smart-7fe62585-30ff-4286-ad5a-c1f026bdcdd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363733655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.363733655
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.3641718259
Short name T483
Test name
Test status
Simulation time 83736660 ps
CPU time 2.91 seconds
Started Jun 10 05:53:10 PM PDT 24
Finished Jun 10 05:53:13 PM PDT 24
Peak memory 233044 kb
Host smart-efaa8a96-f428-42df-a804-69924bb2e04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641718259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.3641718259
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.1800021014
Short name T564
Test name
Test status
Simulation time 21037378 ps
CPU time 0.72 seconds
Started Jun 10 05:53:10 PM PDT 24
Finished Jun 10 05:53:11 PM PDT 24
Peak memory 206196 kb
Host smart-1abb898e-ee2f-495f-b572-8a26f7fafb8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1800021014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.1800021014
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.1712061465
Short name T162
Test name
Test status
Simulation time 4129819113 ps
CPU time 31.35 seconds
Started Jun 10 05:53:12 PM PDT 24
Finished Jun 10 05:53:43 PM PDT 24
Peak memory 249524 kb
Host smart-a79188dd-f332-4033-82b0-2fd9b668c4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712061465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1712061465
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.1014796837
Short name T29
Test name
Test status
Simulation time 23963132889 ps
CPU time 125.3 seconds
Started Jun 10 05:53:02 PM PDT 24
Finished Jun 10 05:55:08 PM PDT 24
Peak memory 251720 kb
Host smart-f99e0499-f6c7-464d-a57d-bd220d234cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014796837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.1014796837
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.1756909372
Short name T653
Test name
Test status
Simulation time 29901320442 ps
CPU time 301.36 seconds
Started Jun 10 05:53:02 PM PDT 24
Finished Jun 10 05:58:04 PM PDT 24
Peak memory 265124 kb
Host smart-b7efa587-cfc8-4c12-82bd-aac894d42543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756909372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.1756909372
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.2020266877
Short name T369
Test name
Test status
Simulation time 143438131 ps
CPU time 3.83 seconds
Started Jun 10 05:53:09 PM PDT 24
Finished Jun 10 05:53:14 PM PDT 24
Peak memory 224668 kb
Host smart-7cbf07e5-49c1-4828-a9e0-cab828543cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020266877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.2020266877
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.1815543818
Short name T912
Test name
Test status
Simulation time 1466165703 ps
CPU time 4.85 seconds
Started Jun 10 05:53:02 PM PDT 24
Finished Jun 10 05:53:07 PM PDT 24
Peak memory 233028 kb
Host smart-77856b81-63bb-4ea7-8ad3-16a6dc89be0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815543818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1815543818
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.1285633386
Short name T421
Test name
Test status
Simulation time 1633292038 ps
CPU time 20.92 seconds
Started Jun 10 05:53:03 PM PDT 24
Finished Jun 10 05:53:25 PM PDT 24
Peak memory 232900 kb
Host smart-4fd1ca86-4e78-4a17-a5c1-c471eaf091e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285633386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.1285633386
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.1424657898
Short name T498
Test name
Test status
Simulation time 32048201 ps
CPU time 2.1 seconds
Started Jun 10 05:53:10 PM PDT 24
Finished Jun 10 05:53:12 PM PDT 24
Peak memory 223544 kb
Host smart-6bf19068-a9c4-4d5b-a194-696d35eea892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424657898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.1424657898
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.3480841959
Short name T619
Test name
Test status
Simulation time 2816643464 ps
CPU time 8.8 seconds
Started Jun 10 05:53:03 PM PDT 24
Finished Jun 10 05:53:12 PM PDT 24
Peak memory 233116 kb
Host smart-cc22e0bc-84c9-4518-93e2-750fa8bc9843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480841959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.3480841959
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.153324340
Short name T575
Test name
Test status
Simulation time 704020144 ps
CPU time 3.63 seconds
Started Jun 10 05:53:13 PM PDT 24
Finished Jun 10 05:53:18 PM PDT 24
Peak memory 223312 kb
Host smart-13b3a2f2-1810-4e06-8f46-e65421a34044
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=153324340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dire
ct.153324340
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.4126148767
Short name T157
Test name
Test status
Simulation time 78220906891 ps
CPU time 741.97 seconds
Started Jun 10 05:53:08 PM PDT 24
Finished Jun 10 06:05:30 PM PDT 24
Peak memory 266004 kb
Host smart-fe644288-f435-426b-ab34-1070674e2d5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126148767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.4126148767
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.499741232
Short name T743
Test name
Test status
Simulation time 2625270680 ps
CPU time 14.35 seconds
Started Jun 10 05:53:08 PM PDT 24
Finished Jun 10 05:53:23 PM PDT 24
Peak memory 216672 kb
Host smart-ee6dca10-39b3-49d8-8ded-bfed3eb763a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499741232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.499741232
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.880627961
Short name T605
Test name
Test status
Simulation time 19843270777 ps
CPU time 16.37 seconds
Started Jun 10 05:53:03 PM PDT 24
Finished Jun 10 05:53:20 PM PDT 24
Peak memory 216756 kb
Host smart-54ac16f0-4457-46b1-8a90-5a7aa063491c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880627961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.880627961
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.1367474236
Short name T328
Test name
Test status
Simulation time 53217760 ps
CPU time 1.19 seconds
Started Jun 10 05:53:02 PM PDT 24
Finished Jun 10 05:53:04 PM PDT 24
Peak memory 208128 kb
Host smart-16f04ccd-0fec-4486-bac2-da03ff580ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367474236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.1367474236
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.2069008599
Short name T734
Test name
Test status
Simulation time 193915898 ps
CPU time 0.92 seconds
Started Jun 10 05:53:05 PM PDT 24
Finished Jun 10 05:53:07 PM PDT 24
Peak memory 206196 kb
Host smart-2d81349e-a0b4-44b8-b3d9-80a7e9b7ce74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069008599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2069008599
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.205604434
Short name T264
Test name
Test status
Simulation time 45042551939 ps
CPU time 37.96 seconds
Started Jun 10 05:53:12 PM PDT 24
Finished Jun 10 05:53:50 PM PDT 24
Peak memory 235612 kb
Host smart-623e41d8-b8b1-4e6e-af46-c463e20b2394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205604434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.205604434
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.1247669412
Short name T78
Test name
Test status
Simulation time 15247973 ps
CPU time 0.79 seconds
Started Jun 10 05:53:10 PM PDT 24
Finished Jun 10 05:53:11 PM PDT 24
Peak memory 205192 kb
Host smart-c8ebe832-fea5-4971-ac51-bed49cfd834b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247669412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
1247669412
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.1167315192
Short name T946
Test name
Test status
Simulation time 242788435 ps
CPU time 5.36 seconds
Started Jun 10 05:53:15 PM PDT 24
Finished Jun 10 05:53:21 PM PDT 24
Peak memory 233000 kb
Host smart-2160a183-d24f-403e-b3bb-1d6d3c6eceea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167315192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1167315192
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.2601345248
Short name T803
Test name
Test status
Simulation time 236909484 ps
CPU time 0.82 seconds
Started Jun 10 05:53:05 PM PDT 24
Finished Jun 10 05:53:06 PM PDT 24
Peak memory 206868 kb
Host smart-55016f00-12b9-450d-9e61-d5f14901f96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601345248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2601345248
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.1111554757
Short name T65
Test name
Test status
Simulation time 5937011164 ps
CPU time 75.29 seconds
Started Jun 10 05:53:08 PM PDT 24
Finished Jun 10 05:54:23 PM PDT 24
Peak memory 249504 kb
Host smart-5391eb01-162e-4153-970d-7ab873ab6cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111554757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.1111554757
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.2158189851
Short name T124
Test name
Test status
Simulation time 18463215727 ps
CPU time 93.01 seconds
Started Jun 10 05:53:16 PM PDT 24
Finished Jun 10 05:54:49 PM PDT 24
Peak memory 265304 kb
Host smart-09989d32-824c-46c9-aca5-01bbcaa42ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158189851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.2158189851
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.2956868878
Short name T441
Test name
Test status
Simulation time 4827251175 ps
CPU time 20.57 seconds
Started Jun 10 05:53:16 PM PDT 24
Finished Jun 10 05:53:37 PM PDT 24
Peak memory 241268 kb
Host smart-28b571ef-0413-4426-9cf5-9d535ce7af05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956868878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.2956868878
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.109639581
Short name T10
Test name
Test status
Simulation time 162876367 ps
CPU time 3.94 seconds
Started Jun 10 05:53:02 PM PDT 24
Finished Jun 10 05:53:07 PM PDT 24
Peak memory 224772 kb
Host smart-fa2e58f1-58b9-4d41-8177-432be56658d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109639581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.109639581
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.4187982851
Short name T710
Test name
Test status
Simulation time 166277823 ps
CPU time 4.21 seconds
Started Jun 10 05:53:15 PM PDT 24
Finished Jun 10 05:53:20 PM PDT 24
Peak memory 232936 kb
Host smart-a9e43427-63da-410d-b71e-b2e24fa293bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187982851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.4187982851
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.3780080019
Short name T131
Test name
Test status
Simulation time 570403541 ps
CPU time 3.29 seconds
Started Jun 10 05:53:07 PM PDT 24
Finished Jun 10 05:53:11 PM PDT 24
Peak memory 224680 kb
Host smart-f7f8edb0-227e-4457-abfe-08e01a22711e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780080019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3780080019
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2406583151
Short name T709
Test name
Test status
Simulation time 647167892 ps
CPU time 3.25 seconds
Started Jun 10 05:53:07 PM PDT 24
Finished Jun 10 05:53:11 PM PDT 24
Peak memory 232992 kb
Host smart-66b6e2f1-4c89-43ec-af2c-6c84cc3a709b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406583151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2406583151
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.3292929809
Short name T211
Test name
Test status
Simulation time 348196741 ps
CPU time 3.17 seconds
Started Jun 10 05:53:04 PM PDT 24
Finished Jun 10 05:53:08 PM PDT 24
Peak memory 224720 kb
Host smart-f07e43c8-8dcb-4e53-8369-d1ebce7827c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292929809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3292929809
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.4112061927
Short name T901
Test name
Test status
Simulation time 1310383506 ps
CPU time 4.14 seconds
Started Jun 10 05:53:19 PM PDT 24
Finished Jun 10 05:53:24 PM PDT 24
Peak memory 220992 kb
Host smart-6b9775ed-545a-4e5c-8d46-a76723ea171d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4112061927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.4112061927
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.433483645
Short name T906
Test name
Test status
Simulation time 4090241179 ps
CPU time 6.58 seconds
Started Jun 10 05:53:21 PM PDT 24
Finished Jun 10 05:53:28 PM PDT 24
Peak memory 217940 kb
Host smart-dcdd6269-d76a-47f2-aab5-9e744cc8579f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433483645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.433483645
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.4243521446
Short name T455
Test name
Test status
Simulation time 6286571328 ps
CPU time 17.74 seconds
Started Jun 10 05:53:07 PM PDT 24
Finished Jun 10 05:53:25 PM PDT 24
Peak memory 216628 kb
Host smart-a7bd0f78-ffd8-4abd-ada2-947a3153fb2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243521446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.4243521446
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.1699883008
Short name T781
Test name
Test status
Simulation time 52154644 ps
CPU time 0.92 seconds
Started Jun 10 05:53:10 PM PDT 24
Finished Jun 10 05:53:11 PM PDT 24
Peak memory 207008 kb
Host smart-d97975ec-9d6f-483e-870e-978ad8b0bb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699883008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.1699883008
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.1288951286
Short name T792
Test name
Test status
Simulation time 66749310 ps
CPU time 0.88 seconds
Started Jun 10 05:53:05 PM PDT 24
Finished Jun 10 05:53:06 PM PDT 24
Peak memory 206560 kb
Host smart-5d701cc9-90d6-4f7f-ae9e-d0735d54f00b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1288951286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1288951286
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.1498130996
Short name T931
Test name
Test status
Simulation time 934759521 ps
CPU time 7.14 seconds
Started Jun 10 05:53:15 PM PDT 24
Finished Jun 10 05:53:23 PM PDT 24
Peak memory 233008 kb
Host smart-adc88561-2deb-43e1-880b-970daf546298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498130996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.1498130996
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.3719372963
Short name T353
Test name
Test status
Simulation time 40834438 ps
CPU time 0.78 seconds
Started Jun 10 05:53:14 PM PDT 24
Finished Jun 10 05:53:16 PM PDT 24
Peak memory 205168 kb
Host smart-41667fed-a263-40e3-aa17-1a0ec111ae86
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3719372963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
3719372963
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.4197789093
Short name T826
Test name
Test status
Simulation time 81273693 ps
CPU time 2.87 seconds
Started Jun 10 05:53:16 PM PDT 24
Finished Jun 10 05:53:19 PM PDT 24
Peak memory 232956 kb
Host smart-9a16ee79-bd68-4847-a532-1e83cf738db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4197789093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.4197789093
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.1604336476
Short name T742
Test name
Test status
Simulation time 79201590 ps
CPU time 0.77 seconds
Started Jun 10 05:53:07 PM PDT 24
Finished Jun 10 05:53:09 PM PDT 24
Peak memory 206808 kb
Host smart-894b81a7-3f7b-40b7-a1e4-8e7aa69aa78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604336476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.1604336476
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.3906058180
Short name T39
Test name
Test status
Simulation time 25020544595 ps
CPU time 65.74 seconds
Started Jun 10 05:53:12 PM PDT 24
Finished Jun 10 05:54:18 PM PDT 24
Peak memory 253124 kb
Host smart-c3be80e9-92a4-4553-b99a-ffa8b546ee5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906058180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.3906058180
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.611804800
Short name T916
Test name
Test status
Simulation time 1646042245 ps
CPU time 48.1 seconds
Started Jun 10 05:53:19 PM PDT 24
Finished Jun 10 05:54:07 PM PDT 24
Peak memory 249432 kb
Host smart-b784b391-3b0e-4e00-b4b9-8252be8758dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611804800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.611804800
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.3223479585
Short name T846
Test name
Test status
Simulation time 7699628707 ps
CPU time 49.74 seconds
Started Jun 10 05:53:26 PM PDT 24
Finished Jun 10 05:54:16 PM PDT 24
Peak memory 232872 kb
Host smart-539ecefc-e0b7-4fae-8c5d-08d7d270d208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223479585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.3223479585
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_intercept.1656367576
Short name T202
Test name
Test status
Simulation time 692530746 ps
CPU time 9.9 seconds
Started Jun 10 05:53:15 PM PDT 24
Finished Jun 10 05:53:26 PM PDT 24
Peak memory 232988 kb
Host smart-fd43b20a-9485-47a7-8072-52ceff9b50fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1656367576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.1656367576
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.751106466
Short name T655
Test name
Test status
Simulation time 3422014398 ps
CPU time 20.16 seconds
Started Jun 10 05:53:12 PM PDT 24
Finished Jun 10 05:53:33 PM PDT 24
Peak memory 249752 kb
Host smart-e7e25fdc-0363-490d-be34-81a419b87605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751106466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.751106466
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.2371081032
Short name T904
Test name
Test status
Simulation time 3889124644 ps
CPU time 13.05 seconds
Started Jun 10 05:53:16 PM PDT 24
Finished Jun 10 05:53:29 PM PDT 24
Peak memory 233124 kb
Host smart-05b3a255-ea67-4d06-b570-bf3c3a6cc895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371081032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.2371081032
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3687043956
Short name T190
Test name
Test status
Simulation time 5324091720 ps
CPU time 14.26 seconds
Started Jun 10 05:53:20 PM PDT 24
Finished Jun 10 05:53:35 PM PDT 24
Peak memory 224924 kb
Host smart-fc890842-9754-4295-b225-c4f6f320d030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687043956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3687043956
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.360019673
Short name T761
Test name
Test status
Simulation time 7033476611 ps
CPU time 12.88 seconds
Started Jun 10 05:53:16 PM PDT 24
Finished Jun 10 05:53:30 PM PDT 24
Peak memory 221612 kb
Host smart-0903a89b-5353-4f17-a630-c2ed7a16a86f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=360019673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dire
ct.360019673
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.822639054
Short name T84
Test name
Test status
Simulation time 26659777127 ps
CPU time 105.75 seconds
Started Jun 10 05:53:13 PM PDT 24
Finished Jun 10 05:55:00 PM PDT 24
Peak memory 249556 kb
Host smart-ab421b71-7385-40a7-84d4-3e9efa17a7f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822639054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stres
s_all.822639054
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.4114458008
Short name T439
Test name
Test status
Simulation time 11465381586 ps
CPU time 17.08 seconds
Started Jun 10 05:53:16 PM PDT 24
Finished Jun 10 05:53:34 PM PDT 24
Peak memory 216692 kb
Host smart-2a9264a7-b7ee-4d81-9a21-37b7abfea1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114458008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.4114458008
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.1932098790
Short name T737
Test name
Test status
Simulation time 13779965518 ps
CPU time 7.05 seconds
Started Jun 10 05:53:08 PM PDT 24
Finished Jun 10 05:53:16 PM PDT 24
Peak memory 216816 kb
Host smart-ade29c05-0e31-48a6-ad7f-98091d40c9c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932098790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1932098790
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.1996949147
Short name T327
Test name
Test status
Simulation time 1092124635 ps
CPU time 1.77 seconds
Started Jun 10 05:53:13 PM PDT 24
Finished Jun 10 05:53:15 PM PDT 24
Peak memory 216568 kb
Host smart-a2cfc3b7-c1bd-4c6d-a72f-93420225e58c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996949147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1996949147
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.70330255
Short name T424
Test name
Test status
Simulation time 106676527 ps
CPU time 1.12 seconds
Started Jun 10 05:53:05 PM PDT 24
Finished Jun 10 05:53:06 PM PDT 24
Peak memory 206668 kb
Host smart-f5bc8860-d7d3-45f1-a6ed-c0634fa348b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70330255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.70330255
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.1758121685
Short name T127
Test name
Test status
Simulation time 598491557 ps
CPU time 2.89 seconds
Started Jun 10 05:53:19 PM PDT 24
Finished Jun 10 05:53:22 PM PDT 24
Peak memory 224752 kb
Host smart-e35b49e6-f912-4397-8626-01756e52ade4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758121685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.1758121685
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.1407005878
Short name T467
Test name
Test status
Simulation time 40886691 ps
CPU time 0.71 seconds
Started Jun 10 05:53:18 PM PDT 24
Finished Jun 10 05:53:19 PM PDT 24
Peak memory 205752 kb
Host smart-bffd2d7e-0bad-47ba-84ac-89f654ad0d3b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407005878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
1407005878
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3684377053
Short name T629
Test name
Test status
Simulation time 844415060 ps
CPU time 9.52 seconds
Started Jun 10 05:53:15 PM PDT 24
Finished Jun 10 05:53:25 PM PDT 24
Peak memory 232984 kb
Host smart-09f5dbc0-f788-4278-981b-8d18af6f1dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684377053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3684377053
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.1533604332
Short name T80
Test name
Test status
Simulation time 17181792 ps
CPU time 0.76 seconds
Started Jun 10 05:53:28 PM PDT 24
Finished Jun 10 05:53:30 PM PDT 24
Peak memory 206180 kb
Host smart-ee90bd2e-b8c2-4f54-b85f-0b947d75f598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533604332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.1533604332
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.2465792370
Short name T45
Test name
Test status
Simulation time 19135734286 ps
CPU time 33.76 seconds
Started Jun 10 05:53:14 PM PDT 24
Finished Jun 10 05:53:48 PM PDT 24
Peak memory 234896 kb
Host smart-9f825b83-2a42-4a14-a856-787fc2ea78dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465792370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.2465792370
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.2115330293
Short name T53
Test name
Test status
Simulation time 30452638665 ps
CPU time 97.33 seconds
Started Jun 10 05:53:17 PM PDT 24
Finished Jun 10 05:54:55 PM PDT 24
Peak memory 249584 kb
Host smart-2e504738-a4a7-45da-bfc3-e658135541a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115330293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.2115330293
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.550698225
Short name T875
Test name
Test status
Simulation time 54062569911 ps
CPU time 149.96 seconds
Started Jun 10 05:53:20 PM PDT 24
Finished Jun 10 05:55:50 PM PDT 24
Peak memory 250764 kb
Host smart-e3cc977a-55da-4056-b955-ba580fc15ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550698225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle
.550698225
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.2116803502
Short name T315
Test name
Test status
Simulation time 290853159 ps
CPU time 4.07 seconds
Started Jun 10 05:53:14 PM PDT 24
Finished Jun 10 05:53:19 PM PDT 24
Peak memory 232968 kb
Host smart-d1f1ebc3-b065-46b8-ace8-6d12bd81a1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116803502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.2116803502
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.369692381
Short name T167
Test name
Test status
Simulation time 3649110667 ps
CPU time 18.04 seconds
Started Jun 10 05:53:20 PM PDT 24
Finished Jun 10 05:53:39 PM PDT 24
Peak memory 220296 kb
Host smart-53f47e05-fd5e-478d-a0c7-c5de63d242ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369692381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.369692381
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.1472790279
Short name T859
Test name
Test status
Simulation time 27671383116 ps
CPU time 130.26 seconds
Started Jun 10 05:53:14 PM PDT 24
Finished Jun 10 05:55:25 PM PDT 24
Peak memory 233088 kb
Host smart-14e564fe-ef4c-46c8-b2f8-1a29bfc94d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472790279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.1472790279
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.3970912628
Short name T681
Test name
Test status
Simulation time 4652357766 ps
CPU time 5.8 seconds
Started Jun 10 05:53:14 PM PDT 24
Finished Jun 10 05:53:20 PM PDT 24
Peak memory 241284 kb
Host smart-ae1e122b-d7d8-405b-a059-f550a7934ae1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970912628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.3970912628
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2239361477
Short name T891
Test name
Test status
Simulation time 258343579 ps
CPU time 2.12 seconds
Started Jun 10 05:53:14 PM PDT 24
Finished Jun 10 05:53:17 PM PDT 24
Peak memory 223332 kb
Host smart-04d5517d-8d2b-477a-974a-e2a6ec031925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239361477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2239361477
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.3957054388
Short name T678
Test name
Test status
Simulation time 1085634197 ps
CPU time 5.4 seconds
Started Jun 10 05:53:13 PM PDT 24
Finished Jun 10 05:53:20 PM PDT 24
Peak memory 220992 kb
Host smart-57498efd-0301-4d6f-b84c-4ca93e58b012
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3957054388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.3957054388
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.4200621658
Short name T177
Test name
Test status
Simulation time 595700655998 ps
CPU time 638.4 seconds
Started Jun 10 05:53:15 PM PDT 24
Finished Jun 10 06:03:53 PM PDT 24
Peak memory 274120 kb
Host smart-cdf44ec8-b6dc-40cc-b1b1-4738e4c958dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200621658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.4200621658
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3364968878
Short name T570
Test name
Test status
Simulation time 2246378272 ps
CPU time 6.48 seconds
Started Jun 10 05:53:16 PM PDT 24
Finished Jun 10 05:53:23 PM PDT 24
Peak memory 216680 kb
Host smart-4c465be8-ea24-4189-aded-f1d7a1c29c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364968878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3364968878
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.1317478892
Short name T763
Test name
Test status
Simulation time 847205132 ps
CPU time 6.58 seconds
Started Jun 10 05:53:14 PM PDT 24
Finished Jun 10 05:53:21 PM PDT 24
Peak memory 216604 kb
Host smart-640b6373-3de0-49e3-a928-ce55546bdd04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317478892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.1317478892
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.1917059742
Short name T591
Test name
Test status
Simulation time 55694991 ps
CPU time 1.12 seconds
Started Jun 10 05:53:22 PM PDT 24
Finished Jun 10 05:53:23 PM PDT 24
Peak memory 216368 kb
Host smart-a0cdbd23-e370-4f0a-80ab-ff510499e101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917059742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.1917059742
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.3624123528
Short name T343
Test name
Test status
Simulation time 142133484 ps
CPU time 0.82 seconds
Started Jun 10 05:53:29 PM PDT 24
Finished Jun 10 05:53:30 PM PDT 24
Peak memory 206188 kb
Host smart-018b053a-f3e7-422c-8efb-df148b6b251f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624123528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3624123528
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.839165775
Short name T268
Test name
Test status
Simulation time 1643037926 ps
CPU time 7.7 seconds
Started Jun 10 05:53:35 PM PDT 24
Finished Jun 10 05:53:44 PM PDT 24
Peak memory 224724 kb
Host smart-8f3c8950-7cf4-4e22-9041-54fc1c5f209f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839165775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.839165775
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.3878435409
Short name T777
Test name
Test status
Simulation time 29712155 ps
CPU time 0.69 seconds
Started Jun 10 05:53:17 PM PDT 24
Finished Jun 10 05:53:18 PM PDT 24
Peak memory 205760 kb
Host smart-ffd80be7-022f-45ff-ba1d-4de85764b204
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878435409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
3878435409
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.2580569266
Short name T944
Test name
Test status
Simulation time 88611218 ps
CPU time 2.64 seconds
Started Jun 10 05:53:42 PM PDT 24
Finished Jun 10 05:53:46 PM PDT 24
Peak memory 233016 kb
Host smart-a526bcfe-bf75-4905-b137-ac4aa472a89c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580569266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2580569266
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.2331466208
Short name T511
Test name
Test status
Simulation time 26782138 ps
CPU time 0.75 seconds
Started Jun 10 05:53:13 PM PDT 24
Finished Jun 10 05:53:15 PM PDT 24
Peak memory 206148 kb
Host smart-5f279f3c-fff2-4faa-950e-ecc58b38aed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331466208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.2331466208
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.2938172452
Short name T890
Test name
Test status
Simulation time 19710003598 ps
CPU time 47.7 seconds
Started Jun 10 05:53:26 PM PDT 24
Finished Jun 10 05:54:14 PM PDT 24
Peak memory 239140 kb
Host smart-916366a3-3b0b-400a-8847-104da282e470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938172452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.2938172452
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.1510333799
Short name T533
Test name
Test status
Simulation time 9652303176 ps
CPU time 136.34 seconds
Started Jun 10 05:53:23 PM PDT 24
Finished Jun 10 05:55:40 PM PDT 24
Peak memory 249600 kb
Host smart-b8521c49-d248-464f-a14b-91135309f2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510333799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.1510333799
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.2649584646
Short name T580
Test name
Test status
Simulation time 18953855532 ps
CPU time 186.71 seconds
Started Jun 10 05:53:16 PM PDT 24
Finished Jun 10 05:56:23 PM PDT 24
Peak memory 249792 kb
Host smart-9943b083-88f6-4a9a-9998-56703ca36dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649584646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.2649584646
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.4001621208
Short name T311
Test name
Test status
Simulation time 802329766 ps
CPU time 15.01 seconds
Started Jun 10 05:53:19 PM PDT 24
Finished Jun 10 05:53:34 PM PDT 24
Peak memory 235548 kb
Host smart-bb5e28dd-e6a6-4155-9eff-5a80609c79b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001621208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.4001621208
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.4252389670
Short name T712
Test name
Test status
Simulation time 38384019 ps
CPU time 2.96 seconds
Started Jun 10 05:53:24 PM PDT 24
Finished Jun 10 05:53:28 PM PDT 24
Peak memory 233012 kb
Host smart-8781b8c6-fadd-46f4-ba8d-b884b45054b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252389670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.4252389670
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.1191894124
Short name T565
Test name
Test status
Simulation time 3069241849 ps
CPU time 13.1 seconds
Started Jun 10 05:53:29 PM PDT 24
Finished Jun 10 05:53:43 PM PDT 24
Peak memory 240804 kb
Host smart-56567777-3168-4a48-85cd-f30c1b631e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191894124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.1191894124
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.2499786655
Short name T203
Test name
Test status
Simulation time 285480286 ps
CPU time 4.77 seconds
Started Jun 10 05:53:21 PM PDT 24
Finished Jun 10 05:53:26 PM PDT 24
Peak memory 224796 kb
Host smart-19d37082-31b0-4fd2-a76a-3c26decd779c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499786655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.2499786655
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.1366864282
Short name T862
Test name
Test status
Simulation time 3199407332 ps
CPU time 7.03 seconds
Started Jun 10 05:53:40 PM PDT 24
Finished Jun 10 05:53:47 PM PDT 24
Peak memory 224888 kb
Host smart-707b79a4-790e-4324-94ab-41df473e33ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366864282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1366864282
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.974510412
Short name T384
Test name
Test status
Simulation time 247265270 ps
CPU time 5.09 seconds
Started Jun 10 05:53:30 PM PDT 24
Finished Jun 10 05:53:36 PM PDT 24
Peak memory 220436 kb
Host smart-908a2bb5-598d-4b4e-99d2-5bc2a73c6672
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=974510412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dire
ct.974510412
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.1018844816
Short name T15
Test name
Test status
Simulation time 153472375744 ps
CPU time 86.55 seconds
Started Jun 10 05:53:23 PM PDT 24
Finished Jun 10 05:54:50 PM PDT 24
Peak memory 241248 kb
Host smart-b74d4907-5127-4b31-a7ce-6692c2bb7941
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018844816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.1018844816
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.2777105810
Short name T496
Test name
Test status
Simulation time 3168120078 ps
CPU time 24.1 seconds
Started Jun 10 05:53:15 PM PDT 24
Finished Jun 10 05:53:40 PM PDT 24
Peak memory 216908 kb
Host smart-d7ff96a2-4bc6-45d1-8558-118876e35f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777105810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.2777105810
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2973508995
Short name T696
Test name
Test status
Simulation time 11211361 ps
CPU time 0.68 seconds
Started Jun 10 05:53:15 PM PDT 24
Finished Jun 10 05:53:16 PM PDT 24
Peak memory 206004 kb
Host smart-3d76f5f5-61b8-4182-a7d3-23569c69cd11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973508995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2973508995
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.1832913667
Short name T448
Test name
Test status
Simulation time 24028887 ps
CPU time 0.79 seconds
Started Jun 10 05:53:20 PM PDT 24
Finished Jun 10 05:53:22 PM PDT 24
Peak memory 206140 kb
Host smart-3fa52739-1384-49c2-8283-5c67310c6456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832913667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.1832913667
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.3130790149
Short name T594
Test name
Test status
Simulation time 18952246 ps
CPU time 0.71 seconds
Started Jun 10 05:53:15 PM PDT 24
Finished Jun 10 05:53:16 PM PDT 24
Peak memory 206164 kb
Host smart-cf4cfed6-6033-4ac0-a6bb-1ecdcaf47267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130790149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.3130790149
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.25907727
Short name T458
Test name
Test status
Simulation time 116849053 ps
CPU time 2.28 seconds
Started Jun 10 05:53:20 PM PDT 24
Finished Jun 10 05:53:23 PM PDT 24
Peak memory 224604 kb
Host smart-7a2908bd-b95d-4b5a-9c9f-af984f8a082c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25907727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.25907727
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2506902178
Short name T876
Test name
Test status
Simulation time 17294380 ps
CPU time 0.66 seconds
Started Jun 10 05:53:35 PM PDT 24
Finished Jun 10 05:53:37 PM PDT 24
Peak memory 205712 kb
Host smart-961f6f6c-744f-4981-9a35-0e5dc6707c9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506902178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2506902178
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.3480440413
Short name T661
Test name
Test status
Simulation time 4430287396 ps
CPU time 13.41 seconds
Started Jun 10 05:53:23 PM PDT 24
Finished Jun 10 05:53:37 PM PDT 24
Peak memory 224960 kb
Host smart-203e5659-e9fa-45b8-b739-1d680aeef559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3480440413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3480440413
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.4285479572
Short name T365
Test name
Test status
Simulation time 17501462 ps
CPU time 0.74 seconds
Started Jun 10 05:53:19 PM PDT 24
Finished Jun 10 05:53:20 PM PDT 24
Peak memory 206176 kb
Host smart-d17d4537-f413-4772-b65a-591d9eae4d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285479572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.4285479572
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.2972656954
Short name T56
Test name
Test status
Simulation time 130502531654 ps
CPU time 120 seconds
Started Jun 10 05:53:22 PM PDT 24
Finished Jun 10 05:55:23 PM PDT 24
Peak memory 241396 kb
Host smart-28261f4b-3163-4c34-b1fc-f0e4dbff8843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972656954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.2972656954
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.1174540794
Short name T217
Test name
Test status
Simulation time 13633193878 ps
CPU time 100.88 seconds
Started Jun 10 05:53:46 PM PDT 24
Finished Jun 10 05:55:27 PM PDT 24
Peak memory 249544 kb
Host smart-f8556d3c-e897-4f91-b0cb-73d9a4a7a0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174540794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.1174540794
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.3650274262
Short name T733
Test name
Test status
Simulation time 5343849470 ps
CPU time 35.83 seconds
Started Jun 10 05:53:24 PM PDT 24
Finished Jun 10 05:54:01 PM PDT 24
Peak memory 233008 kb
Host smart-a3680f37-ac98-4e5e-8c2f-171912fa0978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650274262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.3650274262
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.2479214271
Short name T842
Test name
Test status
Simulation time 4527776778 ps
CPU time 12.22 seconds
Started Jun 10 05:53:23 PM PDT 24
Finished Jun 10 05:53:36 PM PDT 24
Peak memory 220644 kb
Host smart-3a6b2154-a8e8-4686-b55b-40040cc12499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479214271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.2479214271
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.3667571498
Short name T187
Test name
Test status
Simulation time 11838263334 ps
CPU time 54.27 seconds
Started Jun 10 05:53:21 PM PDT 24
Finished Jun 10 05:54:15 PM PDT 24
Peak memory 233152 kb
Host smart-2d318a94-d714-4711-9a81-c40f69955e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667571498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.3667571498
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.1724528339
Short name T416
Test name
Test status
Simulation time 4368595548 ps
CPU time 5.32 seconds
Started Jun 10 05:53:42 PM PDT 24
Finished Jun 10 05:53:48 PM PDT 24
Peak memory 233144 kb
Host smart-838a7bf0-5321-482a-b389-5d16eb2bdca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724528339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.1724528339
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.224342910
Short name T505
Test name
Test status
Simulation time 383471371 ps
CPU time 4.41 seconds
Started Jun 10 05:53:35 PM PDT 24
Finished Jun 10 05:53:39 PM PDT 24
Peak memory 223388 kb
Host smart-aacbb60b-28a8-4148-bbcc-91a5365a07fb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=224342910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dire
ct.224342910
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.3720972016
Short name T158
Test name
Test status
Simulation time 213185882151 ps
CPU time 231.25 seconds
Started Jun 10 05:53:24 PM PDT 24
Finished Jun 10 05:57:16 PM PDT 24
Peak memory 241304 kb
Host smart-a9bf45f9-524f-4a44-9bf5-cbb71ea01311
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720972016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.3720972016
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.2852249789
Short name T86
Test name
Test status
Simulation time 13206273732 ps
CPU time 33.41 seconds
Started Jun 10 05:53:19 PM PDT 24
Finished Jun 10 05:53:52 PM PDT 24
Peak memory 216768 kb
Host smart-0ebafebb-d6a5-46bd-8c52-82a05039f45c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852249789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.2852249789
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.2118265362
Short name T850
Test name
Test status
Simulation time 2667624985 ps
CPU time 7.24 seconds
Started Jun 10 05:53:24 PM PDT 24
Finished Jun 10 05:53:31 PM PDT 24
Peak memory 216684 kb
Host smart-ddc0551e-0cbe-4b49-aa15-69405106d83d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118265362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2118265362
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.1269784159
Short name T659
Test name
Test status
Simulation time 148592841 ps
CPU time 1.51 seconds
Started Jun 10 05:53:31 PM PDT 24
Finished Jun 10 05:53:33 PM PDT 24
Peak memory 216624 kb
Host smart-cf2600ae-6b17-4662-90d1-fdee26a012df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269784159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.1269784159
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.4034468793
Short name T828
Test name
Test status
Simulation time 103175770 ps
CPU time 0.74 seconds
Started Jun 10 05:53:37 PM PDT 24
Finished Jun 10 05:53:39 PM PDT 24
Peak memory 206204 kb
Host smart-60d08d97-c4fe-40aa-bc04-aa2d9569db27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034468793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.4034468793
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.1566610346
Short name T409
Test name
Test status
Simulation time 4331195472 ps
CPU time 14.75 seconds
Started Jun 10 05:53:28 PM PDT 24
Finished Jun 10 05:53:43 PM PDT 24
Peak memory 224924 kb
Host smart-8eb320a8-0459-408e-af5e-d0648a7429a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566610346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.1566610346
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.1095192994
Short name T454
Test name
Test status
Simulation time 13470996 ps
CPU time 0.72 seconds
Started Jun 10 05:53:25 PM PDT 24
Finished Jun 10 05:53:26 PM PDT 24
Peak memory 205732 kb
Host smart-11079445-3098-4011-ad0d-ece4889eaa32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1095192994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
1095192994
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.2614724748
Short name T413
Test name
Test status
Simulation time 2275716232 ps
CPU time 3.7 seconds
Started Jun 10 05:53:24 PM PDT 24
Finished Jun 10 05:53:28 PM PDT 24
Peak memory 224896 kb
Host smart-19928140-a6ed-48d9-ab85-6475f66eba70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614724748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.2614724748
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3494620280
Short name T602
Test name
Test status
Simulation time 23669150 ps
CPU time 0.83 seconds
Started Jun 10 05:53:26 PM PDT 24
Finished Jun 10 05:53:27 PM PDT 24
Peak memory 206888 kb
Host smart-f14f662e-7b29-4d70-8b4e-7189a5a0e184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494620280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3494620280
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.3212406916
Short name T461
Test name
Test status
Simulation time 12954802 ps
CPU time 0.76 seconds
Started Jun 10 05:53:23 PM PDT 24
Finished Jun 10 05:53:25 PM PDT 24
Peak memory 216108 kb
Host smart-1a6d63fa-93fe-4d41-8059-92097cfd50c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212406916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.3212406916
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.1649581346
Short name T266
Test name
Test status
Simulation time 20318911939 ps
CPU time 70.72 seconds
Started Jun 10 05:53:36 PM PDT 24
Finished Jun 10 05:54:47 PM PDT 24
Peak memory 248648 kb
Host smart-7a6cde35-1b63-4c73-a067-b2d37deaa596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649581346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.1649581346
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3671182801
Short name T740
Test name
Test status
Simulation time 46082971852 ps
CPU time 455.17 seconds
Started Jun 10 05:53:35 PM PDT 24
Finished Jun 10 06:01:11 PM PDT 24
Peak memory 253648 kb
Host smart-e7a22968-4423-4a32-83cf-c192041ff643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671182801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.3671182801
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.3968544366
Short name T306
Test name
Test status
Simulation time 11609144749 ps
CPU time 92.13 seconds
Started Jun 10 05:53:26 PM PDT 24
Finished Jun 10 05:54:58 PM PDT 24
Peak memory 241388 kb
Host smart-4853804c-ae50-4527-a2ce-e8389dd243cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968544366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.3968544366
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3120279324
Short name T703
Test name
Test status
Simulation time 149847521 ps
CPU time 2.18 seconds
Started Jun 10 05:53:25 PM PDT 24
Finished Jun 10 05:53:28 PM PDT 24
Peak memory 223324 kb
Host smart-25524f4e-5327-41e0-86f4-29fa5bb3de5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120279324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3120279324
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.4001437812
Short name T824
Test name
Test status
Simulation time 35974665470 ps
CPU time 57.89 seconds
Started Jun 10 05:53:29 PM PDT 24
Finished Jun 10 05:54:27 PM PDT 24
Peak memory 224864 kb
Host smart-f3e4d1ac-0b16-4d63-8a4c-aa8547333ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001437812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.4001437812
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.3033811420
Short name T273
Test name
Test status
Simulation time 12322138037 ps
CPU time 19.43 seconds
Started Jun 10 05:53:26 PM PDT 24
Finished Jun 10 05:53:46 PM PDT 24
Peak memory 233088 kb
Host smart-c428711f-b5dd-4311-8c63-c746b38eb983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033811420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.3033811420
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.3737748035
Short name T176
Test name
Test status
Simulation time 5936927151 ps
CPU time 18.33 seconds
Started Jun 10 05:53:35 PM PDT 24
Finished Jun 10 05:53:54 PM PDT 24
Peak memory 233104 kb
Host smart-f3bd2bf0-3d56-4739-86b5-3bcd3afa853f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737748035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3737748035
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.2570303428
Short name T903
Test name
Test status
Simulation time 602898674 ps
CPU time 7.61 seconds
Started Jun 10 05:53:26 PM PDT 24
Finished Jun 10 05:53:34 PM PDT 24
Peak memory 219628 kb
Host smart-2c458e5c-4940-42e2-bd55-6a9e0a589db4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2570303428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.2570303428
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.2709192245
Short name T779
Test name
Test status
Simulation time 7041574065 ps
CPU time 72.51 seconds
Started Jun 10 05:53:25 PM PDT 24
Finished Jun 10 05:54:38 PM PDT 24
Peak memory 249520 kb
Host smart-446b9392-073b-451a-8231-108804f3effd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709192245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.2709192245
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.2957450521
Short name T130
Test name
Test status
Simulation time 2290176765 ps
CPU time 7.9 seconds
Started Jun 10 05:53:31 PM PDT 24
Finished Jun 10 05:53:39 PM PDT 24
Peak memory 219184 kb
Host smart-089449a4-d43a-417a-b2dc-934dea2b6c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957450521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.2957450521
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2403858602
Short name T579
Test name
Test status
Simulation time 8000473609 ps
CPU time 24.04 seconds
Started Jun 10 05:53:31 PM PDT 24
Finished Jun 10 05:53:55 PM PDT 24
Peak memory 216684 kb
Host smart-fdf339af-d16f-45c0-9884-6036fce8d379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403858602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2403858602
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.370230840
Short name T704
Test name
Test status
Simulation time 308988080 ps
CPU time 1.19 seconds
Started Jun 10 05:53:26 PM PDT 24
Finished Jun 10 05:53:28 PM PDT 24
Peak memory 208316 kb
Host smart-aeb65676-259b-4c7e-9527-b70fc33dee26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370230840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.370230840
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.3265615055
Short name T715
Test name
Test status
Simulation time 21715037 ps
CPU time 0.76 seconds
Started Jun 10 05:53:23 PM PDT 24
Finished Jun 10 05:53:25 PM PDT 24
Peak memory 206200 kb
Host smart-9a5730a7-ced3-4468-9c77-f860eb46106e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265615055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.3265615055
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.1961261314
Short name T639
Test name
Test status
Simulation time 2307319038 ps
CPU time 3.8 seconds
Started Jun 10 05:53:26 PM PDT 24
Finished Jun 10 05:53:30 PM PDT 24
Peak memory 224856 kb
Host smart-c22b99e4-aeff-47ee-9ff5-ce31b2d911ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961261314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.1961261314
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.1894502255
Short name T714
Test name
Test status
Simulation time 14382121 ps
CPU time 0.7 seconds
Started Jun 10 05:53:36 PM PDT 24
Finished Jun 10 05:53:37 PM PDT 24
Peak memory 205200 kb
Host smart-c2ab87ec-8b1f-4650-9c27-b3b55c35926e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894502255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
1894502255
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.3988551341
Short name T213
Test name
Test status
Simulation time 599391490 ps
CPU time 4.23 seconds
Started Jun 10 05:53:32 PM PDT 24
Finished Jun 10 05:53:37 PM PDT 24
Peak memory 232840 kb
Host smart-a96bd237-1e90-4faa-bac8-61974c6a910f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988551341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.3988551341
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.1104797338
Short name T910
Test name
Test status
Simulation time 58251530 ps
CPU time 0.78 seconds
Started Jun 10 05:53:28 PM PDT 24
Finished Jun 10 05:53:29 PM PDT 24
Peak memory 207176 kb
Host smart-0226441d-dca9-4d93-9722-6e83a4c0a94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104797338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1104797338
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.2857648847
Short name T636
Test name
Test status
Simulation time 5108812008 ps
CPU time 10.51 seconds
Started Jun 10 05:53:27 PM PDT 24
Finished Jun 10 05:53:38 PM PDT 24
Peak memory 234100 kb
Host smart-e16e8428-f336-4f11-bf28-5adbf53e97e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857648847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.2857648847
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.4047117065
Short name T716
Test name
Test status
Simulation time 15721613143 ps
CPU time 104.17 seconds
Started Jun 10 05:53:32 PM PDT 24
Finished Jun 10 05:55:17 PM PDT 24
Peak memory 233180 kb
Host smart-53ed204d-fe27-4ecd-82a6-ccf784f0a266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047117065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.4047117065
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.3846290149
Short name T934
Test name
Test status
Simulation time 5818628958 ps
CPU time 98.73 seconds
Started Jun 10 05:53:46 PM PDT 24
Finished Jun 10 05:55:26 PM PDT 24
Peak memory 250148 kb
Host smart-329555e0-64e8-494e-95a0-751a317ad5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846290149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.3846290149
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.1811332352
Short name T574
Test name
Test status
Simulation time 174897230 ps
CPU time 4.56 seconds
Started Jun 10 05:53:29 PM PDT 24
Finished Jun 10 05:53:34 PM PDT 24
Peak memory 233064 kb
Host smart-3ed18914-d9c4-4fb6-a187-7f2fa02e3940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811332352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.1811332352
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.836480650
Short name T101
Test name
Test status
Simulation time 2043287761 ps
CPU time 5.38 seconds
Started Jun 10 05:53:30 PM PDT 24
Finished Jun 10 05:53:35 PM PDT 24
Peak memory 232896 kb
Host smart-1a6a1880-17a8-410d-90ff-0247bb8eee53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836480650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.836480650
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.2730062887
Short name T907
Test name
Test status
Simulation time 2437294030 ps
CPU time 18.96 seconds
Started Jun 10 05:53:38 PM PDT 24
Finished Jun 10 05:53:57 PM PDT 24
Peak memory 220076 kb
Host smart-1c868f10-7557-4ce2-b706-a6cc39e15d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730062887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.2730062887
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3437997312
Short name T303
Test name
Test status
Simulation time 1166321697 ps
CPU time 3.45 seconds
Started Jun 10 05:53:28 PM PDT 24
Finished Jun 10 05:53:32 PM PDT 24
Peak memory 229172 kb
Host smart-97454717-e9a6-4909-a853-c623d1ced56d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437997312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3437997312
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.1744036858
Short name T263
Test name
Test status
Simulation time 8344312087 ps
CPU time 16.15 seconds
Started Jun 10 05:53:31 PM PDT 24
Finished Jun 10 05:53:48 PM PDT 24
Peak memory 241216 kb
Host smart-04ac62c0-7e36-48f0-a77e-1e5480611220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744036858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1744036858
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.1322499558
Short name T62
Test name
Test status
Simulation time 420317784 ps
CPU time 5.01 seconds
Started Jun 10 05:53:40 PM PDT 24
Finished Jun 10 05:53:46 PM PDT 24
Peak memory 222984 kb
Host smart-b7f84822-0093-4b51-8c91-d8bd7d865bc3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1322499558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.1322499558
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.1552557489
Short name T436
Test name
Test status
Simulation time 31340357 ps
CPU time 0.9 seconds
Started Jun 10 05:53:39 PM PDT 24
Finished Jun 10 05:53:40 PM PDT 24
Peak memory 205944 kb
Host smart-20d6c1b7-3899-4e35-891b-c6592b1096bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552557489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.1552557489
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.1547570576
Short name T754
Test name
Test status
Simulation time 1282211909 ps
CPU time 5.8 seconds
Started Jun 10 05:53:37 PM PDT 24
Finished Jun 10 05:53:43 PM PDT 24
Peak memory 216624 kb
Host smart-af53991d-5818-429b-b3ee-a9424586dfd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547570576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1547570576
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.1508763205
Short name T664
Test name
Test status
Simulation time 791346733 ps
CPU time 2.7 seconds
Started Jun 10 05:53:37 PM PDT 24
Finished Jun 10 05:53:40 PM PDT 24
Peak memory 216392 kb
Host smart-be7aabbf-8e93-4e93-9af1-657071c4710c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508763205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1508763205
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.60433281
Short name T549
Test name
Test status
Simulation time 100455638 ps
CPU time 1.24 seconds
Started Jun 10 05:53:28 PM PDT 24
Finished Jun 10 05:53:30 PM PDT 24
Peak memory 216396 kb
Host smart-48f1111e-58e4-4daa-b895-f8e3849c785d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60433281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.60433281
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3698369297
Short name T338
Test name
Test status
Simulation time 70340599 ps
CPU time 0.76 seconds
Started Jun 10 05:53:30 PM PDT 24
Finished Jun 10 05:53:32 PM PDT 24
Peak memory 206188 kb
Host smart-300843ec-da7e-4518-88f8-fec23b7aac4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698369297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3698369297
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.2455029583
Short name T799
Test name
Test status
Simulation time 1116387162 ps
CPU time 6.12 seconds
Started Jun 10 05:53:38 PM PDT 24
Finished Jun 10 05:53:44 PM PDT 24
Peak memory 224812 kb
Host smart-ac3c802d-a8d3-4124-ae88-dde300070b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455029583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2455029583
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.3333611363
Short name T388
Test name
Test status
Simulation time 116020901 ps
CPU time 0.75 seconds
Started Jun 10 05:51:09 PM PDT 24
Finished Jun 10 05:51:10 PM PDT 24
Peak memory 205148 kb
Host smart-4b57edf8-d071-4c3e-b5da-c3687cdc8024
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333611363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3
333611363
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.3967354753
Short name T200
Test name
Test status
Simulation time 380545026 ps
CPU time 6.25 seconds
Started Jun 10 05:51:07 PM PDT 24
Finished Jun 10 05:51:13 PM PDT 24
Peak memory 224780 kb
Host smart-c22a97b2-b41d-491c-933a-f27d831732a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967354753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3967354753
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.1409792796
Short name T532
Test name
Test status
Simulation time 14216750 ps
CPU time 0.77 seconds
Started Jun 10 05:51:13 PM PDT 24
Finished Jun 10 05:51:14 PM PDT 24
Peak memory 205872 kb
Host smart-1f16e03a-7851-431d-97b7-637c9cf4ce90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409792796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1409792796
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.1558423714
Short name T233
Test name
Test status
Simulation time 104631394069 ps
CPU time 221.49 seconds
Started Jun 10 05:51:09 PM PDT 24
Finished Jun 10 05:54:51 PM PDT 24
Peak memory 249528 kb
Host smart-d85e1ce2-eabc-4bff-bd14-d5ba3e6797d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558423714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.1558423714
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.1279958365
Short name T929
Test name
Test status
Simulation time 28651527167 ps
CPU time 215.5 seconds
Started Jun 10 05:51:12 PM PDT 24
Finished Jun 10 05:54:48 PM PDT 24
Peak memory 257636 kb
Host smart-558ec8b8-4bde-4dfa-a87c-1c868b6b419a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279958365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.1279958365
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.354391981
Short name T666
Test name
Test status
Simulation time 8872671086 ps
CPU time 22.55 seconds
Started Jun 10 05:51:14 PM PDT 24
Finished Jun 10 05:51:37 PM PDT 24
Peak memory 218108 kb
Host smart-a7ae135c-b8b0-4564-bd90-adeaf0b32486
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354391981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.
354391981
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.174838528
Short name T59
Test name
Test status
Simulation time 551288577 ps
CPU time 7.54 seconds
Started Jun 10 05:51:06 PM PDT 24
Finished Jun 10 05:51:13 PM PDT 24
Peak memory 224740 kb
Host smart-e579dd05-8705-4bf1-83df-1c00926a7189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174838528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.174838528
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.7467889
Short name T298
Test name
Test status
Simulation time 768271016 ps
CPU time 8.6 seconds
Started Jun 10 05:51:14 PM PDT 24
Finished Jun 10 05:51:23 PM PDT 24
Peak memory 224776 kb
Host smart-71fd6d6c-f9ab-4048-8662-c2e9fcc526c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7467889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.7467889
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.3307597343
Short name T452
Test name
Test status
Simulation time 15073288361 ps
CPU time 45.8 seconds
Started Jun 10 05:51:01 PM PDT 24
Finished Jun 10 05:51:47 PM PDT 24
Peak memory 241192 kb
Host smart-e4248f31-1f89-47fb-a79b-ce1979f7e34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307597343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.3307597343
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2256922722
Short name T796
Test name
Test status
Simulation time 3010931742 ps
CPU time 8.08 seconds
Started Jun 10 05:51:03 PM PDT 24
Finished Jun 10 05:51:12 PM PDT 24
Peak memory 224840 kb
Host smart-5d7e635a-7bb8-4d27-a5db-0dc35a76cc15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256922722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2256922722
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.1286837062
Short name T296
Test name
Test status
Simulation time 340425761 ps
CPU time 5.84 seconds
Started Jun 10 05:51:05 PM PDT 24
Finished Jun 10 05:51:12 PM PDT 24
Peak memory 241220 kb
Host smart-e4936d70-02ea-4bbe-91e5-7a37f5ac39dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286837062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1286837062
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.4100607112
Short name T81
Test name
Test status
Simulation time 5552680070 ps
CPU time 9.96 seconds
Started Jun 10 05:51:09 PM PDT 24
Finished Jun 10 05:51:20 PM PDT 24
Peak memory 223592 kb
Host smart-b07380d9-b2ff-4e72-bdfe-66f9beb6c3f6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4100607112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.4100607112
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.3940914743
Short name T757
Test name
Test status
Simulation time 690672149 ps
CPU time 4.82 seconds
Started Jun 10 05:51:32 PM PDT 24
Finished Jun 10 05:51:38 PM PDT 24
Peak memory 216636 kb
Host smart-76a30fc5-5439-4390-bd9b-9b2618f92d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940914743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.3940914743
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.2757156428
Short name T351
Test name
Test status
Simulation time 388683766 ps
CPU time 2.59 seconds
Started Jun 10 05:51:16 PM PDT 24
Finished Jun 10 05:51:19 PM PDT 24
Peak memory 216616 kb
Host smart-df00d1fb-7151-4ba9-9232-1a7a0ef7840b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757156428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2757156428
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.2148645806
Short name T429
Test name
Test status
Simulation time 325835025 ps
CPU time 2.45 seconds
Started Jun 10 05:51:06 PM PDT 24
Finished Jun 10 05:51:08 PM PDT 24
Peak memory 216560 kb
Host smart-4486aa22-4b02-4537-944d-19b12dc9f265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148645806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2148645806
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.3546050318
Short name T627
Test name
Test status
Simulation time 10863948 ps
CPU time 0.72 seconds
Started Jun 10 05:51:17 PM PDT 24
Finished Jun 10 05:51:18 PM PDT 24
Peak memory 205940 kb
Host smart-c095d523-49d0-4bbd-929c-163d01c80589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546050318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3546050318
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.1238145897
Short name T951
Test name
Test status
Simulation time 2804976668 ps
CPU time 8.92 seconds
Started Jun 10 05:51:10 PM PDT 24
Finished Jun 10 05:51:20 PM PDT 24
Peak memory 234104 kb
Host smart-a8cc82a1-6bea-442f-883d-b68896ed532d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238145897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.1238145897
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.876503650
Short name T948
Test name
Test status
Simulation time 16325849 ps
CPU time 0.77 seconds
Started Jun 10 05:51:15 PM PDT 24
Finished Jun 10 05:51:16 PM PDT 24
Peak memory 205084 kb
Host smart-6fa4444e-7851-4690-961e-0df7e509f781
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876503650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.876503650
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.2295523198
Short name T658
Test name
Test status
Simulation time 90260392 ps
CPU time 3.21 seconds
Started Jun 10 05:51:10 PM PDT 24
Finished Jun 10 05:51:14 PM PDT 24
Peak memory 233076 kb
Host smart-abd53423-7cd4-4374-b761-9fe4ed138f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2295523198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2295523198
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.2844293201
Short name T663
Test name
Test status
Simulation time 64593484 ps
CPU time 0.76 seconds
Started Jun 10 05:51:13 PM PDT 24
Finished Jun 10 05:51:14 PM PDT 24
Peak memory 206920 kb
Host smart-df32c8ad-3a07-4955-8d49-84e0bea04679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844293201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2844293201
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.794333607
Short name T583
Test name
Test status
Simulation time 500316586 ps
CPU time 6.61 seconds
Started Jun 10 05:51:18 PM PDT 24
Finished Jun 10 05:51:25 PM PDT 24
Peak memory 218024 kb
Host smart-cf62c83f-88ea-4c33-b296-e423d7dcbe2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794333607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.794333607
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.68469594
Short name T698
Test name
Test status
Simulation time 10924236803 ps
CPU time 64.13 seconds
Started Jun 10 05:51:12 PM PDT 24
Finished Jun 10 05:52:17 PM PDT 24
Peak memory 240436 kb
Host smart-35cdb340-13b6-4a5a-9ae4-0867af1e3f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68469594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.68469594
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.1983682184
Short name T480
Test name
Test status
Simulation time 94205687 ps
CPU time 2.59 seconds
Started Jun 10 05:51:13 PM PDT 24
Finished Jun 10 05:51:16 PM PDT 24
Peak memory 224788 kb
Host smart-b1119385-cb5a-40fe-8008-a9395e848398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983682184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.1983682184
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.1980366463
Short name T437
Test name
Test status
Simulation time 6741584997 ps
CPU time 11.99 seconds
Started Jun 10 05:51:12 PM PDT 24
Finished Jun 10 05:51:24 PM PDT 24
Peak memory 224892 kb
Host smart-3ce97f13-2bec-472c-a86a-fc35e4e1edad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980366463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.1980366463
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.1262712880
Short name T184
Test name
Test status
Simulation time 9689336312 ps
CPU time 110.92 seconds
Started Jun 10 05:51:11 PM PDT 24
Finished Jun 10 05:53:02 PM PDT 24
Peak memory 239568 kb
Host smart-c63c29e1-eb84-4bd6-9b7d-37d65de3c602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262712880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1262712880
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.1777839843
Short name T897
Test name
Test status
Simulation time 195789058 ps
CPU time 2.91 seconds
Started Jun 10 05:51:10 PM PDT 24
Finished Jun 10 05:51:13 PM PDT 24
Peak memory 224776 kb
Host smart-54436246-6990-4582-b4b3-7ddcf127af89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777839843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.1777839843
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.478904404
Short name T447
Test name
Test status
Simulation time 55599896365 ps
CPU time 25.85 seconds
Started Jun 10 05:51:10 PM PDT 24
Finished Jun 10 05:51:36 PM PDT 24
Peak memory 234508 kb
Host smart-dc7f055c-41b6-4bd9-b6da-0591c9f15101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478904404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.478904404
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.1337725174
Short name T419
Test name
Test status
Simulation time 533064859 ps
CPU time 8.89 seconds
Started Jun 10 05:51:20 PM PDT 24
Finished Jun 10 05:51:29 PM PDT 24
Peak memory 222860 kb
Host smart-6851a8f0-1388-4754-a9cb-be135238af50
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1337725174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.1337725174
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.3220531277
Short name T153
Test name
Test status
Simulation time 5454872518 ps
CPU time 35.88 seconds
Started Jun 10 05:51:16 PM PDT 24
Finished Jun 10 05:51:52 PM PDT 24
Peak memory 249408 kb
Host smart-b605dc7a-c186-4fb8-92cb-784021172aff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220531277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.3220531277
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.1481481244
Short name T548
Test name
Test status
Simulation time 1034202756 ps
CPU time 9.28 seconds
Started Jun 10 05:51:07 PM PDT 24
Finished Jun 10 05:51:17 PM PDT 24
Peak memory 216544 kb
Host smart-930284bd-15f4-4a75-9098-7dbf8be131fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481481244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.1481481244
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.1828905471
Short name T801
Test name
Test status
Simulation time 4236125744 ps
CPU time 6.89 seconds
Started Jun 10 05:51:10 PM PDT 24
Finished Jun 10 05:51:17 PM PDT 24
Peak memory 216768 kb
Host smart-3403740c-ba87-4e68-bfc7-fac2ea88dfcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828905471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.1828905471
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.1747181968
Short name T374
Test name
Test status
Simulation time 16207700 ps
CPU time 0.83 seconds
Started Jun 10 05:51:14 PM PDT 24
Finished Jun 10 05:51:15 PM PDT 24
Peak memory 206204 kb
Host smart-3fbb5043-6497-4cbd-a4ad-c14b8c1d7b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747181968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.1747181968
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.2010685264
Short name T668
Test name
Test status
Simulation time 58056854 ps
CPU time 0.71 seconds
Started Jun 10 05:51:12 PM PDT 24
Finished Jun 10 05:51:13 PM PDT 24
Peak memory 206128 kb
Host smart-f320a23f-9910-42fc-ac73-b1c1d9b85b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010685264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.2010685264
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.731861917
Short name T280
Test name
Test status
Simulation time 5933928038 ps
CPU time 14.09 seconds
Started Jun 10 05:51:17 PM PDT 24
Finished Jun 10 05:51:32 PM PDT 24
Peak memory 249476 kb
Host smart-facd6a4b-3fd2-490b-b66c-1f17bb289c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731861917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.731861917
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.2463463705
Short name T387
Test name
Test status
Simulation time 18851331 ps
CPU time 0.8 seconds
Started Jun 10 05:51:21 PM PDT 24
Finished Jun 10 05:51:22 PM PDT 24
Peak memory 206100 kb
Host smart-7c15b1ad-f2df-411a-8bc5-5d78f34057c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463463705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2
463463705
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.1865436368
Short name T938
Test name
Test status
Simulation time 48165768 ps
CPU time 2.59 seconds
Started Jun 10 05:51:14 PM PDT 24
Finished Jun 10 05:51:17 PM PDT 24
Peak memory 232972 kb
Host smart-653ceee7-1495-4245-8f63-8bbf0cc57433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865436368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.1865436368
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.2706192623
Short name T702
Test name
Test status
Simulation time 179169514 ps
CPU time 0.75 seconds
Started Jun 10 05:51:19 PM PDT 24
Finished Jun 10 05:51:20 PM PDT 24
Peak memory 207248 kb
Host smart-c415414d-3127-4d83-bcaf-4e7146dc7ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706192623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.2706192623
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.1456941878
Short name T282
Test name
Test status
Simulation time 1081307451 ps
CPU time 14.57 seconds
Started Jun 10 05:51:16 PM PDT 24
Finished Jun 10 05:51:31 PM PDT 24
Peak memory 233040 kb
Host smart-1082278d-42df-4f2d-8bb9-7d85cbc6b67b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456941878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.1456941878
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.3306464032
Short name T572
Test name
Test status
Simulation time 7963363898 ps
CPU time 38.45 seconds
Started Jun 10 05:51:21 PM PDT 24
Finished Jun 10 05:52:00 PM PDT 24
Peak memory 249348 kb
Host smart-1c0c74ba-49b4-4a40-8fcc-7506c924297d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306464032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.3306464032
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.1590918435
Short name T172
Test name
Test status
Simulation time 3885352570 ps
CPU time 54.18 seconds
Started Jun 10 05:51:20 PM PDT 24
Finished Jun 10 05:52:15 PM PDT 24
Peak memory 250972 kb
Host smart-2be8f664-d1d1-41b3-afcd-79a957c42ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590918435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.1590918435
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.935880181
Short name T307
Test name
Test status
Simulation time 1503066917 ps
CPU time 12.4 seconds
Started Jun 10 05:51:18 PM PDT 24
Finished Jun 10 05:51:31 PM PDT 24
Peak memory 232996 kb
Host smart-45b246df-5bf9-4ec9-902f-d528951501da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935880181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.935880181
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.1698075963
Short name T593
Test name
Test status
Simulation time 1910701211 ps
CPU time 9.63 seconds
Started Jun 10 05:51:13 PM PDT 24
Finished Jun 10 05:51:23 PM PDT 24
Peak memory 232952 kb
Host smart-6954036f-3714-47ae-b550-54a3bd652c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698075963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.1698075963
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2145120347
Short name T284
Test name
Test status
Simulation time 2851031039 ps
CPU time 11.28 seconds
Started Jun 10 05:51:12 PM PDT 24
Finished Jun 10 05:51:24 PM PDT 24
Peak memory 233164 kb
Host smart-01e4723a-a9be-4576-ae23-23ae06ffe66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145120347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2145120347
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.569024703
Short name T205
Test name
Test status
Simulation time 42663667619 ps
CPU time 15.54 seconds
Started Jun 10 05:51:32 PM PDT 24
Finished Jun 10 05:51:48 PM PDT 24
Peak memory 241100 kb
Host smart-b3498144-216f-43a2-b2fb-e069148f7cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569024703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.569024703
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.2470371016
Short name T366
Test name
Test status
Simulation time 318643514 ps
CPU time 3.99 seconds
Started Jun 10 05:51:17 PM PDT 24
Finished Jun 10 05:51:22 PM PDT 24
Peak memory 223264 kb
Host smart-37164bb6-b894-4260-9a57-ff6936fab130
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2470371016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.2470371016
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.499641814
Short name T955
Test name
Test status
Simulation time 71794189 ps
CPU time 0.74 seconds
Started Jun 10 05:51:19 PM PDT 24
Finished Jun 10 05:51:20 PM PDT 24
Peak memory 205968 kb
Host smart-267963f6-6269-4de8-9433-3c3a057c0c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499641814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.499641814
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.958383898
Short name T440
Test name
Test status
Simulation time 13963271239 ps
CPU time 11.31 seconds
Started Jun 10 05:51:15 PM PDT 24
Finished Jun 10 05:51:26 PM PDT 24
Peak memory 216900 kb
Host smart-2e304cb4-2f21-44bd-add8-6c6cc546a084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958383898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.958383898
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.1647195938
Short name T632
Test name
Test status
Simulation time 329153051 ps
CPU time 2.99 seconds
Started Jun 10 05:51:18 PM PDT 24
Finished Jun 10 05:51:21 PM PDT 24
Peak memory 216620 kb
Host smart-c8c3b64e-4451-4eb7-86cc-f3b49951c3cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647195938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1647195938
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.446361688
Short name T643
Test name
Test status
Simulation time 104869603 ps
CPU time 0.83 seconds
Started Jun 10 05:51:21 PM PDT 24
Finished Jun 10 05:51:22 PM PDT 24
Peak memory 206196 kb
Host smart-794ac9ea-2391-4fd6-a576-5932547fb7db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446361688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.446361688
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.3985293876
Short name T585
Test name
Test status
Simulation time 1909993748 ps
CPU time 5.46 seconds
Started Jun 10 05:51:21 PM PDT 24
Finished Jun 10 05:51:27 PM PDT 24
Peak memory 224844 kb
Host smart-fe79af39-ab1d-4079-92ad-ea6c8b24ed3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985293876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.3985293876
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.3492285974
Short name T370
Test name
Test status
Simulation time 12703152 ps
CPU time 0.72 seconds
Started Jun 10 05:51:28 PM PDT 24
Finished Jun 10 05:51:29 PM PDT 24
Peak memory 205116 kb
Host smart-385f11b0-ffd0-4934-8b98-cd2c1249a90b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492285974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.3
492285974
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.1486738443
Short name T364
Test name
Test status
Simulation time 146155760 ps
CPU time 2.23 seconds
Started Jun 10 05:51:16 PM PDT 24
Finished Jun 10 05:51:18 PM PDT 24
Peak memory 224344 kb
Host smart-a6ca8166-7c53-4b4e-a7b5-8093419cb1a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486738443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.1486738443
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.3031903127
Short name T657
Test name
Test status
Simulation time 15776762 ps
CPU time 0.76 seconds
Started Jun 10 05:51:20 PM PDT 24
Finished Jun 10 05:51:21 PM PDT 24
Peak memory 207176 kb
Host smart-97a0dbee-9ff7-4548-99d7-5edb3dc838a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031903127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.3031903127
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.2210240077
Short name T542
Test name
Test status
Simulation time 67982268 ps
CPU time 0.77 seconds
Started Jun 10 05:51:17 PM PDT 24
Finished Jun 10 05:51:18 PM PDT 24
Peak memory 216124 kb
Host smart-1cd92227-3a4b-48d4-8fe5-d9a3eeb97e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2210240077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.2210240077
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.481847285
Short name T834
Test name
Test status
Simulation time 2417711046 ps
CPU time 17.26 seconds
Started Jun 10 05:51:17 PM PDT 24
Finished Jun 10 05:51:34 PM PDT 24
Peak memory 217796 kb
Host smart-f81ca927-92dd-4686-a01a-286b7d43ac1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481847285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.481847285
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.1040736541
Short name T701
Test name
Test status
Simulation time 72928102926 ps
CPU time 207.19 seconds
Started Jun 10 05:51:21 PM PDT 24
Finished Jun 10 05:54:49 PM PDT 24
Peak memory 257760 kb
Host smart-ce7842b4-6336-45b5-9743-e92f10ddaa56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040736541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.1040736541
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.3060108148
Short name T386
Test name
Test status
Simulation time 219348437 ps
CPU time 3.25 seconds
Started Jun 10 05:51:27 PM PDT 24
Finished Jun 10 05:51:30 PM PDT 24
Peak memory 232928 kb
Host smart-9d84c83d-6693-4162-81df-2d42d08c2adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060108148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3060108148
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.3493254433
Short name T551
Test name
Test status
Simulation time 31470995 ps
CPU time 2.19 seconds
Started Jun 10 05:51:16 PM PDT 24
Finished Jun 10 05:51:18 PM PDT 24
Peak memory 232624 kb
Host smart-2f76d8f9-180e-429c-8f75-5cdbe9c340df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493254433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.3493254433
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.2980647747
Short name T305
Test name
Test status
Simulation time 222641213 ps
CPU time 7.41 seconds
Started Jun 10 05:51:33 PM PDT 24
Finished Jun 10 05:51:41 PM PDT 24
Peak memory 233004 kb
Host smart-820157f4-215c-4b37-9779-8b2ec33554e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980647747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.2980647747
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.4185109224
Short name T300
Test name
Test status
Simulation time 9701467397 ps
CPU time 14.26 seconds
Started Jun 10 05:51:20 PM PDT 24
Finished Jun 10 05:51:35 PM PDT 24
Peak memory 224812 kb
Host smart-22cf487d-3fbd-423c-9222-915071b1121e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185109224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.4185109224
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.4008425746
Short name T722
Test name
Test status
Simulation time 316524314 ps
CPU time 6.03 seconds
Started Jun 10 05:51:16 PM PDT 24
Finished Jun 10 05:51:22 PM PDT 24
Peak memory 233040 kb
Host smart-01660167-49e1-4c3e-a59e-d3c417bc0420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008425746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.4008425746
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.892161085
Short name T23
Test name
Test status
Simulation time 3264358811 ps
CPU time 6.72 seconds
Started Jun 10 05:51:25 PM PDT 24
Finished Jun 10 05:51:32 PM PDT 24
Peak memory 223340 kb
Host smart-cd177886-cfa6-499f-9dfc-e81a11efb48b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=892161085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direc
t.892161085
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.791670960
Short name T933
Test name
Test status
Simulation time 11926199875 ps
CPU time 14.59 seconds
Started Jun 10 05:51:21 PM PDT 24
Finished Jun 10 05:51:36 PM PDT 24
Peak memory 216960 kb
Host smart-045471a2-be25-4ed3-9018-110d596864fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791670960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.791670960
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2714096821
Short name T711
Test name
Test status
Simulation time 2475358180 ps
CPU time 10.02 seconds
Started Jun 10 05:51:14 PM PDT 24
Finished Jun 10 05:51:25 PM PDT 24
Peak memory 216736 kb
Host smart-60d4a400-152e-4e8b-b475-d360b52300e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714096821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2714096821
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.1152638351
Short name T644
Test name
Test status
Simulation time 514602552 ps
CPU time 7.07 seconds
Started Jun 10 05:51:18 PM PDT 24
Finished Jun 10 05:51:25 PM PDT 24
Peak memory 216500 kb
Host smart-ff2b02a6-1279-4dbd-a21b-31f52e7fed65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152638351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.1152638351
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.659099199
Short name T790
Test name
Test status
Simulation time 48037376 ps
CPU time 0.77 seconds
Started Jun 10 05:51:20 PM PDT 24
Finished Jun 10 05:51:22 PM PDT 24
Peak memory 206136 kb
Host smart-dd4d0448-e7fb-47da-aea1-44fdf8279812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659099199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.659099199
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.1744476530
Short name T185
Test name
Test status
Simulation time 10246495262 ps
CPU time 11.52 seconds
Started Jun 10 05:51:28 PM PDT 24
Finished Jun 10 05:51:40 PM PDT 24
Peak memory 233084 kb
Host smart-609e5ad6-5119-45bc-b374-bad782942034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744476530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1744476530
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.420141306
Short name T562
Test name
Test status
Simulation time 22524949 ps
CPU time 0.74 seconds
Started Jun 10 05:51:22 PM PDT 24
Finished Jun 10 05:51:23 PM PDT 24
Peak memory 205196 kb
Host smart-4f432ac2-9f93-40af-8adc-81a15ba182aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420141306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.420141306
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.3518703485
Short name T721
Test name
Test status
Simulation time 640610188 ps
CPU time 4.56 seconds
Started Jun 10 05:51:18 PM PDT 24
Finished Jun 10 05:51:23 PM PDT 24
Peak memory 233000 kb
Host smart-ba82c1be-55a7-469f-b073-1b84256b2c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518703485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.3518703485
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.1653520572
Short name T920
Test name
Test status
Simulation time 28433992 ps
CPU time 0.75 seconds
Started Jun 10 05:51:16 PM PDT 24
Finished Jun 10 05:51:17 PM PDT 24
Peak memory 206840 kb
Host smart-d63b5e2e-4ade-4c5b-a3ba-7fb83479d80d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653520572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1653520572
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.9104909
Short name T784
Test name
Test status
Simulation time 49616795013 ps
CPU time 346.49 seconds
Started Jun 10 05:51:18 PM PDT 24
Finished Jun 10 05:57:04 PM PDT 24
Peak memory 252496 kb
Host smart-27e1e8fc-1c0e-4642-886e-025e8a3341f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9104909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.9104909
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.2705897307
Short name T731
Test name
Test status
Simulation time 11916342269 ps
CPU time 41.26 seconds
Started Jun 10 05:51:28 PM PDT 24
Finished Jun 10 05:52:10 PM PDT 24
Peak memory 249512 kb
Host smart-0b76ec09-4c48-4251-b01f-2a0c54b93809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705897307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.2705897307
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.2550470442
Short name T730
Test name
Test status
Simulation time 171303752745 ps
CPU time 184.53 seconds
Started Jun 10 05:51:31 PM PDT 24
Finished Jun 10 05:54:37 PM PDT 24
Peak memory 249596 kb
Host smart-e7794b74-638b-46cb-917e-bf79e4d71edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550470442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.2550470442
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.2130749608
Short name T881
Test name
Test status
Simulation time 775176414 ps
CPU time 7.89 seconds
Started Jun 10 05:51:28 PM PDT 24
Finished Jun 10 05:51:36 PM PDT 24
Peak memory 224796 kb
Host smart-621a3f80-df05-45b1-b267-0f2a53591a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130749608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.2130749608
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.2755154247
Short name T279
Test name
Test status
Simulation time 2586139374 ps
CPU time 20.15 seconds
Started Jun 10 05:51:26 PM PDT 24
Finished Jun 10 05:51:46 PM PDT 24
Peak memory 224884 kb
Host smart-313e4c39-2148-4da4-aa3e-5a6064ae05a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755154247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2755154247
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.2387969424
Short name T36
Test name
Test status
Simulation time 473009677 ps
CPU time 6.63 seconds
Started Jun 10 05:51:18 PM PDT 24
Finished Jun 10 05:51:25 PM PDT 24
Peak memory 232960 kb
Host smart-9368fe13-08fc-4b38-96f7-3d7b8e9c2700
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387969424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.2387969424
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.2559366957
Short name T887
Test name
Test status
Simulation time 15805268196 ps
CPU time 7.32 seconds
Started Jun 10 05:51:20 PM PDT 24
Finished Jun 10 05:51:28 PM PDT 24
Peak memory 224944 kb
Host smart-b6e215cf-b5ef-4286-828e-f29225546332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559366957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.2559366957
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.3842653302
Short name T939
Test name
Test status
Simulation time 252595386 ps
CPU time 5.03 seconds
Started Jun 10 05:51:18 PM PDT 24
Finished Jun 10 05:51:24 PM PDT 24
Peak memory 224244 kb
Host smart-1326198f-556b-4b37-9beb-0703a63fc897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842653302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.3842653302
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.500693869
Short name T827
Test name
Test status
Simulation time 978958662 ps
CPU time 7.69 seconds
Started Jun 10 05:51:16 PM PDT 24
Finished Jun 10 05:51:24 PM PDT 24
Peak memory 220624 kb
Host smart-a471112c-33fc-4b31-a360-d81b4b557309
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=500693869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direc
t.500693869
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.768824757
Short name T547
Test name
Test status
Simulation time 4766607837 ps
CPU time 94.27 seconds
Started Jun 10 05:51:19 PM PDT 24
Finished Jun 10 05:52:53 PM PDT 24
Peak memory 256492 kb
Host smart-105ccbab-13d9-4304-9e4a-19e854a9b5c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768824757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress
_all.768824757
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.610604104
Short name T380
Test name
Test status
Simulation time 19985434967 ps
CPU time 31.16 seconds
Started Jun 10 05:51:18 PM PDT 24
Finished Jun 10 05:51:50 PM PDT 24
Peak memory 216780 kb
Host smart-fd421fbc-5767-4eb8-b63a-e940636ba63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610604104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.610604104
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.3278607532
Short name T732
Test name
Test status
Simulation time 475570473 ps
CPU time 3.12 seconds
Started Jun 10 05:51:16 PM PDT 24
Finished Jun 10 05:51:20 PM PDT 24
Peak memory 216620 kb
Host smart-c0761a00-7bfe-4bbd-a10d-dcc1242f127f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278607532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.3278607532
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.27499422
Short name T942
Test name
Test status
Simulation time 38930644 ps
CPU time 1.1 seconds
Started Jun 10 05:51:29 PM PDT 24
Finished Jun 10 05:51:30 PM PDT 24
Peak memory 207672 kb
Host smart-ef568ada-f92d-4971-9865-9371ab5384a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27499422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.27499422
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1413527514
Short name T450
Test name
Test status
Simulation time 141487994 ps
CPU time 0.95 seconds
Started Jun 10 05:51:35 PM PDT 24
Finished Jun 10 05:51:36 PM PDT 24
Peak memory 207184 kb
Host smart-0d0868f0-e0d7-45f8-b185-c999860c8c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413527514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1413527514
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.4242988774
Short name T707
Test name
Test status
Simulation time 335700059 ps
CPU time 4.67 seconds
Started Jun 10 05:51:28 PM PDT 24
Finished Jun 10 05:51:33 PM PDT 24
Peak memory 240448 kb
Host smart-1edeed19-f5b3-478a-996b-0463986462a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242988774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.4242988774
Directory /workspace/9.spi_device_upload/latest
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