Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2467400	1			T1	1		T2	30662		T3	1
all_values[1]	2467400	1			T1	1		T2	30662		T3	1
all_values[2]	2467400	1			T1	1		T2	30662		T3	1
all_values[3]	2467400	1			T1	1		T2	30662		T3	1
all_values[4]	2467400	1			T1	1		T2	30662		T3	1
all_values[5]	2467400	1			T1	1		T2	30662		T3	1
all_values[6]	2467400	1			T1	1		T2	30662		T3	1
all_values[7]	2467400	1			T1	1		T2	30662		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19217979

1

T1

8

T2

245296

T3

8

auto[1]

521221

1

T16

125

T35

59

T17

74

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19716691

1

T1

8

T2

245002

T3

8

auto[1]

22509

1

T2

294

T5

4

T6

14

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2410874	1			T1	1		T2	30484		T3	1
all_values[0]	auto[0]	auto[1]	11518	1			T2	178		T6	10		T11	76
all_values[0]	auto[1]	auto[0]	44561	1			T16	9		T35	1		T17	9
all_values[0]	auto[1]	auto[1]	447	1			T16	6		T35	4		T17	1
all_values[1]	auto[0]	auto[0]	2390971	1			T1	1		T2	30603		T3	1
all_values[1]	auto[0]	auto[1]	5671	1			T2	59		T6	2		T16	6
all_values[1]	auto[1]	auto[0]	70470	1			T16	9		T35	9		T17	5
all_values[1]	auto[1]	auto[1]	288	1			T16	4		T35	2		T17	3
all_values[2]	auto[0]	auto[0]	2390796	1			T1	1		T2	30605		T3	1
all_values[2]	auto[0]	auto[1]	2209	1			T2	57		T6	2		T16	10
all_values[2]	auto[1]	auto[0]	74132	1			T16	5		T35	5		T17	5
all_values[2]	auto[1]	auto[1]	263	1			T16	8		T17	5		T21	4
all_values[3]	auto[0]	auto[0]	2420447	1			T1	1		T2	30662		T3	1
all_values[3]	auto[0]	auto[1]	205	1			T16	6		T35	4		T17	1
all_values[3]	auto[1]	auto[0]	46562	1			T16	7		T35	3		T17	5
all_values[3]	auto[1]	auto[1]	186	1			T16	11		T35	3		T17	3
all_values[4]	auto[0]	auto[0]	2397808	1			T1	1		T2	30662		T3	1
all_values[4]	auto[0]	auto[1]	212	1			T16	7		T17	6		T20	2
all_values[4]	auto[1]	auto[0]	69200	1			T16	5		T35	3		T17	3
all_values[4]	auto[1]	auto[1]	180	1			T16	9		T35	3		T17	4
all_values[5]	auto[0]	auto[0]	2424982	1			T1	1		T2	30662		T3	1
all_values[5]	auto[0]	auto[1]	297	1			T5	4		T7	2		T16	6
all_values[5]	auto[1]	auto[0]	41934	1			T16	11		T35	7		T17	3
all_values[5]	auto[1]	auto[1]	187	1			T16	7		T35	4		T17	7
all_values[6]	auto[0]	auto[0]	2374831	1			T1	1		T2	30662		T3	1
all_values[6]	auto[0]	auto[1]	211	1			T16	2		T35	2		T17	3
all_values[6]	auto[1]	auto[0]	92154	1			T16	15		T35	4		T17	6
all_values[6]	auto[1]	auto[1]	204	1			T16	4		T35	1		T17	8
all_values[7]	auto[0]	auto[0]	2386713	1			T1	1		T2	30662		T3	1
all_values[7]	auto[0]	auto[1]	234	1			T16	7		T35	1		T17	6
all_values[7]	auto[1]	auto[0]	80256	1			T16	8		T35	7		T17	5
all_values[7]	auto[1]	auto[1]	197	1			T16	7		T35	3		T17	2