Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	30024	1			T1	6		T2	95		T3	2
auto[SpiFlashAddrCfg]	6330	1			T2	31		T3	6		T6	40
auto[SpiFlashAddr3b]	7964	1			T1	4		T2	55		T3	6
auto[SpiFlashAddr4b]	6386	1			T1	2		T2	29		T3	6

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

28631

1

T2

116

T6

177

T8

3

auto[1]

22073

1

T1

12

T2

94

T3

20

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27214

1

T1

4

T2

119

T3

6

auto[1]

23490

1

T1

8

T2

91

T3

14

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	33973	1			T1	6		T2	117		T3	2
values[1]	892	1			T2	1		T6	2		T11	3
values[2]	1179	1			T2	9		T3	2		T6	17
values[3]	1251	1			T2	6		T6	6		T11	2
values[4]	1264	1			T2	9		T3	8		T6	6
values[5]	1290	1			T2	5		T3	2		T6	3
values[6]	1247	1			T2	12		T3	4		T6	6
values[7]	1255	1			T2	2		T6	5		T11	4
values[8]	8353	1			T1	6		T2	49		T3	2

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26634

1

T1

12

T2

210

T3

20

auto[1]

24070

1

T6

308

T8

3

T11

110

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

48859

1

T1

12

T2

199

T3

20

write

1845

1

T2

11

T6

6

T8

1

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

16896

1

T1

2

T2

103

T3

12

valids[0x1]

33808

1

T1

10

T2

107

T3

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1317	1			T1	2		T2	3		T6	9
internal_process_ops[0x5a]	1400	1			T2	5		T6	9		T11	4
internal_process_ops[0x05]	18053	1			T2	33		T3	2		T6	139
internal_process_ops[0x35]	1360	1			T2	5		T6	9		T11	5
internal_process_ops[0x15]	1389	1			T1	2		T2	6		T6	6
internal_process_ops[0x03]	847	1			T1	2		T2	4		T3	6
internal_process_ops[0x0b]	960	1			T2	6		T6	3		T8	1
internal_process_ops[0x3b]	938	1			T2	9		T3	2		T6	1
internal_process_ops[0x6b]	906	1			T2	7		T6	1		T8	2
internal_process_ops[0xbb]	921	1			T1	2		T2	4		T11	5
internal_process_ops[0xeb]	914	1			T2	4		T3	4		T6	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49755

1

T1

12

T2

208

T3

20

auto[1]

949

1

T2

2

T6

1

T12

6

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48918

1

T1

12

T2

198

T3

20

auto[1]

1786

1

T2

12

T6

11

T11

4

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9135

1

T2

49

T15

12

T25

6

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5584

1

T1

6

T2

43

T3

2

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1748

1

T2

17

T15

1

T27

20

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1594

1

T2

14

T3

6

T12

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2354

1

T2

31

T15

3

T27

33

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1955

1

T1

4

T2

18

T3

6

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1812

1

T2

15

T15

5

T27

27

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1579

1

T1

2

T2

12

T3

6

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

60

1

T39

1

T20

2

T38

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

43

1

T41

2

T29

1

T156

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

62

1

T2

2

T39

2

T38

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

67

1

T2

1

T12

6

T37

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

73

1

T27

2

T39

2

T37

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

51

1

T27

1

T39

2

T20

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

35

1

T27

1

T46

1

T37

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

63

1

T15

1

T37

3

T21

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

54

1

T2

4

T27

1

T46

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

59

1

T38

3

T29

2

T157

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

40

1

T2

1

T39

1

T37

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

66

1

T2

1

T36

4

T39

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

61

1

T37

1

T38

2

T158

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

57

1

T39

1

T21

2

T157

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

52

1

T2

2

T46

1

T39

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

30

1

T27

1

T38

1

T21

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8374

1

T6

128

T11

24

T26

3

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6423

1

T6

77

T11

21

T26

3

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1286

1

T6

18

T8

2

T11

9

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1233

1

T6

20

T11

11

T26

1

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1604

1

T6

18

T11

4

T26

3

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1597

1

T6

13

T11

11

T26

2

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1361

1

T6

11

T11

20

T26

2

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1220

1

T6

17

T11

8

T26

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

65

1

T35

1

T45

1

T76

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

67

1

T26

2

T76

2

T77

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

65

1

T35

6

T159

1

T20

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

79

1

T35

2

T17

2

T76

4

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

72

1

T6

2

T8

1

T35

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

70

1

T35

2

T77

6

T159

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

39

1

T35

1

T76

2

T77

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

66

1

T35

1

T17

2

T45

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

53

1

T26

1

T35

2

T45

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

66

1

T35

4

T45

1

T76

5

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

63

1

T6

3

T11

2

T35

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

53

1

T6

1

T35

3

T17

4

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

50

1

T35

2

T160

1

T33

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

56

1

T35

6

T76

4

T77

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

52

1

T35

2

T76

1

T77

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

56

1

T35

3

T17

1

T83

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3637	1			T2	39		T12	4		T15	7
auto[0]	values[0]	valids[0x1]	13410	1			T1	6		T2	78		T3	2
auto[0]	values[1]	valids[0x1]	428	1			T2	1		T27	7		T46	5
auto[0]	values[2]	valids[0x0]	451	1			T2	9		T3	2		T15	2
auto[0]	values[2]	valids[0x1]	229	1			T15	1		T27	4		T46	4
auto[0]	values[3]	valids[0x0]	483	1			T2	5		T12	4		T27	2
auto[0]	values[3]	valids[0x1]	247	1			T2	1		T12	2		T27	1
auto[0]	values[4]	valids[0x0]	439	1			T2	3		T3	2		T27	8
auto[0]	values[4]	valids[0x1]	324	1			T2	6		T3	6		T15	4
auto[0]	values[5]	valids[0x0]	451	1			T2	5		T3	2		T27	3
auto[0]	values[5]	valids[0x1]	291	1			T27	2		T152	4		T161	3
auto[0]	values[6]	valids[0x0]	474	1			T2	5		T3	4		T27	11
auto[0]	values[6]	valids[0x1]	235	1			T2	7		T27	1		T153	4
auto[0]	values[7]	valids[0x0]	458	1			T2	1		T15	1		T27	13
auto[0]	values[7]	valids[0x1]	272	1			T2	1		T27	1		T46	1
auto[0]	values[8]	valids[0x0]	2987	1			T1	2		T2	36		T3	2
auto[0]	values[8]	valids[0x1]	1818	1			T1	4		T2	13		T10	2
auto[1]	values[0]	valids[0x0]	3581	1			T6	44		T11	21		T26	3
auto[1]	values[0]	valids[0x1]	13345	1			T6	186		T8	1		T11	30
auto[1]	values[1]	valids[0x1]	464	1			T6	2		T11	3		T26	1
auto[1]	values[2]	valids[0x0]	276	1			T6	10		T11	2		T35	5
auto[1]	values[2]	valids[0x1]	223	1			T6	7		T11	2		T35	7
auto[1]	values[3]	valids[0x0]	308	1			T6	2		T26	2		T35	7
auto[1]	values[3]	valids[0x1]	213	1			T6	4		T11	2		T35	2
auto[1]	values[4]	valids[0x0]	296	1			T6	3		T11	9		T35	15
auto[1]	values[4]	valids[0x1]	205	1			T6	3		T11	1		T35	10
auto[1]	values[5]	valids[0x0]	314	1			T6	1		T11	4		T26	1
auto[1]	values[5]	valids[0x1]	234	1			T6	2		T35	9		T83	1
auto[1]	values[6]	valids[0x0]	329	1			T6	2		T8	2		T11	6
auto[1]	values[6]	valids[0x1]	209	1			T6	4		T11	3		T35	12
auto[1]	values[7]	valids[0x0]	304	1			T11	3		T35	8		T17	7
auto[1]	values[7]	valids[0x1]	221	1			T6	5		T11	1		T26	1
auto[1]	values[8]	valids[0x0]	2108	1			T6	21		T11	10		T26	5
auto[1]	values[8]	valids[0x1]	1440	1			T6	12		T11	13		T26	2