Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3005658

1

T1

1

T2

7160

T3

1

auto[1]

16646

1

T2

30

T6

128

T11

10

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

934147

1

T1

1

T2

54

T3

1

auto[1]

2088157

1

T2

7136

T6

9419

T11

4996

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	559224	1			T1	1		T2	8		T3	1
auto[524288:1048575]	305512	1			T2	2		T6	145		T15	8
auto[1048576:1572863]	369901	1			T2	10		T6	2469		T25	1762
auto[1572864:2097151]	410088	1			T2	1297		T6	273		T8	6522
auto[2097152:2621439]	382696	1			T2	522		T6	774		T8	5519
auto[2621440:3145727]	333047	1			T2	3434		T6	789		T25	1299
auto[3145728:3670015]	354884	1			T2	5		T6	521		T8	52
auto[3670016:4194303]	306952	1			T2	1912		T6	4165		T11	2

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2106906

1

T1

1

T2

7188

T3

1

auto[1]

915398

1

T2

2

T6

3

T8

12601

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2641271

1

T1

1

T2

5898

T3

1

auto[1]

381033

1

T2

1292

T6

3086

T11

2931

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	213551	1			T1	1		T2	2		T3	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	296479	1			T2	1		T6	3		T11	263
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	67126	1			T2	2		T6	1		T15	1
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	189892	1			T6	143		T15	1		T26	512
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	110136	1			T2	4		T6	7		T25	1762
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	207645	1			T2	2		T6	2415		T27	525
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	126756	1			T2	5		T6	1		T8	6522
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	222913	1			T2	4		T6	263		T11	512
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	122398	1			T2	4		T6	6		T8	5519
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	201569	1			T2	514		T6	767		T11	772
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	109344	1			T2	11		T6	7		T25	1299
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	187765	1			T2	3409		T6	514		T27	387
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	94807	1			T2	1		T6	2		T8	52
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	215630	1			T2	4		T6	7		T11	525
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	85270	1			T2	9		T6	5		T15	1
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	176625	1			T2	1896		T6	2181		T11	2
auto[0]	auto[1]	auto[0:524287]	auto[0]	217	1			T2	1		T6	8		T11	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	46066	1			T6	263		T27	2904		T35	1
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	235	1			T6	1		T35	2		T17	4
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	46205	1			T35	2		T17	770		T76	2787
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	257	1			T27	1		T35	9		T17	4
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	49531	1			T35	1122		T17	2		T45	616
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	1339	1			T2	2		T6	2		T35	2
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	57210	1			T2	1285		T6	1		T11	209
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	227	1			T11	6		T26	2		T17	6
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	56695	1			T11	2705		T26	1		T27	131
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	212	1			T2	1		T6	2		T35	3
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	33830	1			T6	256		T35	9		T77	129
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	222	1			T11	1		T27	2		T35	4
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	42532	1			T6	512		T11	2		T35	1149
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	260	1			T35	6		T83	1		T39	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	42714	1			T2	3		T6	1977		T39	1
auto[1]	auto[0]	auto[0:524287]	auto[0]	252	1			T2	1		T6	1		T15	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	2271	1			T2	3		T6	3		T35	21
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	145	1			T15	1		T27	1		T35	5
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1377	1			T15	5		T35	11		T20	17
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	190	1			T2	2		T6	3		T35	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1492	1			T2	2		T6	44		T35	8
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	154	1			T2	1		T35	1		T45	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1366	1			T35	1		T45	19		T77	56
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	176	1			T2	2		T6	1		T11	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1313	1			T2	2		T11	2		T35	3
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	181	1			T2	5		T6	1		T35	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1242	1			T2	8		T6	9		T35	20
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	170	1			T27	3		T35	3		T17	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1295	1			T27	30		T35	9		T17	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	164	1			T2	1		T6	1		T35	6
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1577	1			T2	3		T6	1		T35	44
auto[1]	auto[1]	auto[0:524287]	auto[0]	44	1			T6	3		T35	1		T20	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	344	1			T6	55		T35	6		T20	1
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	56	1			T76	1		T39	1		T181	3
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	476	1			T76	8		T39	9		T181	29
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	62	1			T35	5		T17	2		T45	4
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	588	1			T35	25		T45	57		T83	13
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	34	1			T6	1		T17	1		T21	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	316	1			T6	5		T21	46		T41	5
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	43	1			T11	3		T26	1		T17	2
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	275	1			T11	4		T26	1		T17	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	48	1			T35	1		T77	1		T39	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	425	1			T77	5		T37	14		T38	4
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	36	1			T159	1		T20	1		T40	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	192	1			T20	4		T29	7		T168	11
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	35	1			T39	1		T21	2		T29	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	307	1			T39	6		T21	92		T29	9

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1714102	1			T1	1		T2	5867		T3	1
auto[0]	auto[0]	auto[1]	913804	1			T2	1		T6	1		T8	12601
auto[0]	auto[1]	auto[0]	376527	1			T2	1292		T6	3021		T11	2924
auto[0]	auto[1]	auto[1]	1225	1			T6	1		T35	2		T45	2
auto[1]	auto[0]	auto[0]	13065	1			T2	29		T6	63		T11	3
auto[1]	auto[0]	auto[1]	300	1			T2	1		T6	1		T27	1
auto[1]	auto[1]	auto[0]	3212	1			T6	64		T11	7		T26	2
auto[1]	auto[1]	auto[1]	69	1			T35	1		T45	2		T83	2