Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15507

1

T2

116

T15

21

T25

6

auto[1]

11127

1

T1

12

T2

94

T3

20

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4062	1			T1	12		T2	27		T12	20
values[1]	3046	1			T10	4		T27	20		T162	4
values[2]	3310	1			T2	40		T27	20		T72	20
values[3]	3599	1			T2	49		T27	20		T46	20
values[4]	3241	1			T2	24		T27	36		T194	8
values[5]	3098	1			T2	30		T31	2		T46	20
values[6]	3156	1			T2	40		T3	20		T15	27
values[7]	3122	1			T15	20		T25	6		T27	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3311	1			T2	30		T25	6		T27	37
values[1]	3675	1			T2	40		T27	36		T43	2
values[2]	3205	1			T15	27		T27	41		T162	4
values[3]	3567	1			T2	29		T3	20		T10	4
values[4]	3131	1			T1	12		T2	40		T27	20
values[5]	3112	1			T2	71		T12	20		T27	40
values[6]	2815	1			T15	20		T27	20		T92	8
values[7]	3818	1			T27	20		T46	20		T93	12

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	335	1			T37	8		T197	4		T183	15
auto[0]	values[0]	values[1]	494	1			T37	15		T38	22		T181	12
auto[0]	values[0]	values[2]	320	1			T161	5		T38	15		T178	126
auto[0]	values[0]	values[3]	202	1			T27	8		T29	16		T157	10
auto[0]	values[0]	values[4]	283	1			T153	12		T157	12		T280	6
auto[0]	values[0]	values[5]	332	1			T2	9		T37	14		T21	12
auto[0]	values[0]	values[6]	81	1			T38	7		T29	13		T145	10
auto[0]	values[0]	values[7]	371	1			T20	9		T181	16		T199	12
auto[0]	values[1]	values[0]	122	1			T161	15		T39	14		T181	8
auto[0]	values[1]	values[1]	236	1			T43	2		T46	10		T157	15
auto[0]	values[1]	values[2]	297	1			T162	4		T21	20		T156	16
auto[0]	values[1]	values[3]	243	1			T38	14		T29	6		T172	39
auto[0]	values[1]	values[4]	166	1			T37	14		T21	32		T156	10
auto[0]	values[1]	values[5]	362	1			T27	16		T181	10		T29	104
auto[0]	values[1]	values[6]	150	1			T92	8		T181	7		T157	9
auto[0]	values[1]	values[7]	217	1			T181	17		T281	14		T188	24
auto[0]	values[2]	values[0]	402	1			T37	32		T38	11		T157	10
auto[0]	values[2]	values[1]	316	1			T2	10		T72	20		T39	13
auto[0]	values[2]	values[2]	256	1			T21	17		T29	20		T172	15
auto[0]	values[2]	values[3]	166	1			T176	27		T174	17		T282	4
auto[0]	values[2]	values[4]	274	1			T2	14		T37	12		T21	29
auto[0]	values[2]	values[5]	212	1			T27	13		T161	14		T38	17
auto[0]	values[2]	values[6]	120	1			T46	14		T29	9		T283	8
auto[0]	values[2]	values[7]	334	1			T93	12		T41	6		T181	10
auto[0]	values[3]	values[0]	256	1			T195	2		T125	2		T41	20
auto[0]	values[3]	values[1]	160	1			T37	20		T20	8		T29	10
auto[0]	values[3]	values[2]	296	1			T164	18		T123	16		T173	18
auto[0]	values[3]	values[3]	358	1			T2	18		T40	15		T157	27
auto[0]	values[3]	values[4]	196	1			T2	13		T40	13		T284	2
auto[0]	values[3]	values[5]	242	1			T46	12		T172	22		T168	15
auto[0]	values[3]	values[6]	431	1			T27	8		T39	19		T38	19
auto[0]	values[3]	values[7]	248	1			T163	6		T181	10		T29	10
auto[0]	values[4]	values[0]	218	1			T39	6		T37	10		T174	77
auto[0]	values[4]	values[1]	360	1			T27	31		T41	30		T29	16
auto[0]	values[4]	values[2]	128	1			T181	16		T156	13		T285	10
auto[0]	values[4]	values[3]	329	1			T275	8		T176	9		T172	17
auto[0]	values[4]	values[4]	247	1			T20	9		T86	10		T156	15
auto[0]	values[4]	values[5]	191	1			T2	18		T21	13		T41	19
auto[0]	values[4]	values[6]	222	1			T21	95		T41	14		T174	9
auto[0]	values[4]	values[7]	246	1			T37	10		T157	13		T174	8
auto[0]	values[5]	values[0]	367	1			T2	12		T37	10		T29	19
auto[0]	values[5]	values[1]	161	1			T165	14		T172	14		T174	31
auto[0]	values[5]	values[2]	110	1			T39	17		T174	22		T146	14
auto[0]	values[5]	values[3]	183	1			T41	21		T157	15		T180	8
auto[0]	values[5]	values[4]	167	1			T20	10		T29	29		T184	14
auto[0]	values[5]	values[5]	174	1			T31	2		T39	9		T170	19
auto[0]	values[5]	values[6]	155	1			T202	4		T198	8		T87	18
auto[0]	values[5]	values[7]	362	1			T46	9		T201	16		T38	10
auto[0]	values[6]	values[0]	341	1			T27	16		T75	19		T157	11
auto[0]	values[6]	values[1]	201	1			T2	9		T39	17		T156	13
auto[0]	values[6]	values[2]	255	1			T15	11		T27	24		T39	24
auto[0]	values[6]	values[3]	180	1			T27	16		T171	4		T276	17
auto[0]	values[6]	values[4]	214	1			T38	13		T286	44		T204	14
auto[0]	values[6]	values[5]	207	1			T2	13		T20	33		T85	6
auto[0]	values[6]	values[6]	157	1			T21	14		T41	7		T29	8
auto[0]	values[6]	values[7]	156	1			T27	11		T37	13		T124	16
auto[0]	values[7]	values[0]	165	1			T25	6		T205	8		T157	14
auto[0]	values[7]	values[1]	243	1			T40	12		T157	20		T185	6
auto[0]	values[7]	values[2]	130	1			T84	8		T157	14		T287	2
auto[0]	values[7]	values[3]	222	1			T38	21		T181	62		T29	12
auto[0]	values[7]	values[4]	234	1			T27	13		T122	11		T187	8
auto[0]	values[7]	values[5]	257	1			T39	13		T29	11		T156	10
auto[0]	values[7]	values[6]	204	1			T15	10		T38	14		T288	14
auto[0]	values[7]	values[7]	243	1			T21	13		T29	14		T174	10
auto[1]	values[0]	values[0]	192	1			T37	71		T183	5		T204	37
auto[1]	values[0]	values[1]	274	1			T37	5		T38	18		T181	25
auto[1]	values[0]	values[2]	107	1			T161	15		T38	14		T178	8
auto[1]	values[0]	values[3]	189	1			T27	12		T29	9		T157	10
auto[1]	values[0]	values[4]	221	1			T1	12		T157	8		T156	67
auto[1]	values[0]	values[5]	317	1			T2	18		T12	20		T37	6
auto[1]	values[0]	values[6]	78	1			T38	17		T29	9		T145	10
auto[1]	values[0]	values[7]	266	1			T182	16		T20	11		T181	10
auto[1]	values[1]	values[0]	103	1			T161	5		T39	6		T181	12
auto[1]	values[1]	values[1]	171	1			T46	14		T157	24		T217	6
auto[1]	values[1]	values[2]	219	1			T21	20		T156	11		T178	11
auto[1]	values[1]	values[3]	286	1			T10	4		T38	6		T29	14
auto[1]	values[1]	values[4]	112	1			T37	6		T21	13		T156	10
auto[1]	values[1]	values[5]	44	1			T27	4		T181	10		T29	6
auto[1]	values[1]	values[6]	106	1			T181	18		T157	11		T240	10
auto[1]	values[1]	values[7]	212	1			T181	10		T156	8		T217	42
auto[1]	values[2]	values[0]	117	1			T37	7		T38	9		T157	10
auto[1]	values[2]	values[1]	133	1			T2	10		T39	20		T21	12
auto[1]	values[2]	values[2]	166	1			T21	8		T29	22		T172	5
auto[1]	values[2]	values[3]	82	1			T176	10		T174	10		T47	6
auto[1]	values[2]	values[4]	317	1			T2	6		T37	8		T21	8
auto[1]	values[2]	values[5]	146	1			T27	7		T161	6		T38	7
auto[1]	values[2]	values[6]	136	1			T46	6		T29	16		T177	9
auto[1]	values[2]	values[7]	133	1			T41	28		T181	10		T178	12
auto[1]	values[3]	values[0]	64	1			T41	6		T146	7		T55	11
auto[1]	values[3]	values[1]	354	1			T37	35		T20	70		T29	10
auto[1]	values[3]	values[2]	160	1			T145	14		T204	8		T219	4
auto[1]	values[3]	values[3]	230	1			T2	11		T40	6		T157	34
auto[1]	values[3]	values[4]	151	1			T2	7		T40	18		T180	5
auto[1]	values[3]	values[5]	73	1			T46	8		T172	9		T168	5
auto[1]	values[3]	values[6]	232	1			T27	12		T39	1		T38	4
auto[1]	values[3]	values[7]	148	1			T181	10		T29	18		T176	6
auto[1]	values[4]	values[0]	120	1			T152	22		T39	14		T37	10
auto[1]	values[4]	values[1]	91	1			T27	5		T41	8		T29	5
auto[1]	values[4]	values[2]	287	1			T194	8		T181	19		T156	149
auto[1]	values[4]	values[3]	228	1			T176	11		T172	3		T168	53
auto[1]	values[4]	values[4]	138	1			T20	11		T156	5		T289	6
auto[1]	values[4]	values[5]	79	1			T2	6		T21	7		T41	1
auto[1]	values[4]	values[6]	154	1			T21	14		T41	6		T261	14
auto[1]	values[4]	values[7]	203	1			T37	59		T157	7		T174	12
auto[1]	values[5]	values[0]	163	1			T2	18		T37	11		T29	9
auto[1]	values[5]	values[1]	78	1			T172	6		T174	8		T290	16
auto[1]	values[5]	values[2]	137	1			T36	12		T39	10		T174	18
auto[1]	values[5]	values[3]	385	1			T41	21		T157	187		T291	18
auto[1]	values[5]	values[4]	138	1			T20	10		T29	43		T156	9
auto[1]	values[5]	values[5]	220	1			T39	11		T37	15		T41	7
auto[1]	values[5]	values[6]	80	1			T174	10		T222	28		T47	19
auto[1]	values[5]	values[7]	218	1			T46	11		T38	10		T29	24
auto[1]	values[6]	values[0]	176	1			T27	21		T157	9		T174	11
auto[1]	values[6]	values[1]	196	1			T2	11		T39	5		T203	24
auto[1]	values[6]	values[2]	197	1			T15	16		T27	17		T39	17
auto[1]	values[6]	values[3]	124	1			T3	20		T27	4		T276	9
auto[1]	values[6]	values[4]	151	1			T38	9		T204	10		T219	33
auto[1]	values[6]	values[5]	103	1			T2	7		T151	2		T20	11
auto[1]	values[6]	values[6]	357	1			T21	198		T41	66		T29	12
auto[1]	values[6]	values[7]	141	1			T27	9		T37	11		T29	14
auto[1]	values[7]	values[0]	170	1			T157	6		T156	8		T177	7
auto[1]	values[7]	values[1]	207	1			T40	8		T157	12		T176	4
auto[1]	values[7]	values[2]	140	1			T157	52		T179	11		T180	22
auto[1]	values[7]	values[3]	160	1			T38	8		T181	7		T29	21
auto[1]	values[7]	values[4]	122	1			T27	7		T122	15		T181	13
auto[1]	values[7]	values[5]	153	1			T39	10		T29	9		T156	13
auto[1]	values[7]	values[6]	152	1			T15	10		T38	6		T176	11
auto[1]	values[7]	values[7]	320	1			T21	19		T29	10		T174	14