Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2467400	1			T1	1		T2	30662		T3	1
all_pins[1]	2467400	1			T1	1		T2	30662		T3	1
all_pins[2]	2467400	1			T1	1		T2	30662		T3	1
all_pins[3]	2467400	1			T1	1		T2	30662		T3	1
all_pins[4]	2467400	1			T1	1		T2	30662		T3	1
all_pins[5]	2467400	1			T1	1		T2	30662		T3	1
all_pins[6]	2467400	1			T1	1		T2	30662		T3	1
all_pins[7]	2467400	1			T1	1		T2	30662		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	19644418	1			T1	8		T2	245296		T3	8
values[0x1]	94782	1			T16	56		T35	20		T17	33
transitions[0x0=>0x1]	93577	1			T16	41		T35	13		T17	24
transitions[0x1=>0x0]	93591	1			T16	42		T35	13		T17	24

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2466912	1			T1	1		T2	30662		T3	1
all_pins[0]	values[0x1]	488	1			T16	6		T35	4		T17	1
all_pins[0]	transitions[0x0=>0x1]	438	1			T16	6		T35	2		T17	1
all_pins[0]	transitions[0x1=>0x0]	253	1			T16	4		T17	3		T19	3
all_pins[1]	values[0x0]	2467097	1			T1	1		T2	30662		T3	1
all_pins[1]	values[0x1]	303	1			T16	4		T35	2		T17	3
all_pins[1]	transitions[0x0=>0x1]	186	1			T16	4		T35	2		T17	2
all_pins[1]	transitions[0x1=>0x0]	156	1			T16	8		T17	4		T20	1
all_pins[2]	values[0x0]	2467127	1			T1	1		T2	30662		T3	1
all_pins[2]	values[0x1]	273	1			T16	8		T17	5		T20	1
all_pins[2]	transitions[0x0=>0x1]	233	1			T16	4		T17	4		T20	1
all_pins[2]	transitions[0x1=>0x0]	146	1			T16	7		T35	3		T17	2
all_pins[3]	values[0x0]	2467214	1			T1	1		T2	30662		T3	1
all_pins[3]	values[0x1]	186	1			T16	11		T35	3		T17	3
all_pins[3]	transitions[0x0=>0x1]	141	1			T16	7		T35	2		T17	3
all_pins[3]	transitions[0x1=>0x0]	135	1			T16	5		T35	2		T17	4
all_pins[4]	values[0x0]	2467220	1			T1	1		T2	30662		T3	1
all_pins[4]	values[0x1]	180	1			T16	9		T35	3		T17	4
all_pins[4]	transitions[0x0=>0x1]	135	1			T16	7		T35	2		T17	2
all_pins[4]	transitions[0x1=>0x0]	1626	1			T16	5		T35	3		T17	5
all_pins[5]	values[0x0]	2465729	1			T1	1		T2	30662		T3	1
all_pins[5]	values[0x1]	1671	1			T16	7		T35	4		T17	7
all_pins[5]	transitions[0x0=>0x1]	880	1			T16	7		T35	3		T17	3
all_pins[5]	transitions[0x1=>0x0]	90693	1			T16	4		T17	4		T19	1
all_pins[6]	values[0x0]	2375916	1			T1	1		T2	30662		T3	1
all_pins[6]	values[0x1]	91484	1			T16	4		T35	1		T17	8
all_pins[6]	transitions[0x0=>0x1]	91429	1			T16	2		T17	8		T20	7861
all_pins[6]	transitions[0x1=>0x0]	142	1			T16	5		T35	2		T17	2
all_pins[7]	values[0x0]	2467203	1			T1	1		T2	30662		T3	1
all_pins[7]	values[0x1]	197	1			T16	7		T35	3		T17	2
all_pins[7]	transitions[0x0=>0x1]	135	1			T16	4		T35	2		T17	1
all_pins[7]	transitions[0x1=>0x0]	440	1			T16	4		T35	3		T21	9