Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	340	1			T2	2		T15	2		T27	2
auto[ReadAddrCrossIntoMailbox]	248	1			T2	1		T15	1		T27	4
auto[ReadAddrCrossOutOfMailbox]	298	1			T2	4		T15	6		T27	4
auto[ReadAddrCrossAllMailbox]	161	1			T2	1		T15	1		T27	1
auto[ReadAddrOutsideMailbox]	3042	1			T1	4		T2	26		T3	12

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1992

1

T1

2

T2

17

T3

6

auto[1]

2097

1

T1

2

T2

17

T3

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	633	1			T1	2		T2	4		T3	6
read_ops[0x0b]	718	1			T2	6		T12	2		T15	3
read_ops[0x3b]	694	1			T2	9		T3	2		T27	11
read_ops[0x6b]	691	1			T2	7		T15	2		T27	8
read_ops[0xbb]	683	1			T1	2		T2	4		T12	4
read_ops[0xeb]	670	1			T2	4		T3	4		T15	3

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	20	1			T29	2		T157	1		T197	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	29	1			T15	1		T38	2		T181	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	14	1			T46	1		T38	1		T29	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T38	1		T181	1		T29	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	19	1			T15	1		T38	1		T41	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T15	2		T38	2		T181	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T39	1		T20	1		T199	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T27	1		T29	2		T199	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	212	1			T1	1		T2	2		T3	3
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	258	1			T1	1		T2	2		T3	3
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	31	1			T27	1		T46	1		T164	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T2	1		T164	1		T41	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	21	1			T29	1		T166	2		T292	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	13	1			T29	1		T178	1		T244	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	31	1			T39	1		T37	1		T20	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	21	1			T15	2		T29	3		T174	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T92	1		T181	1		T293	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T2	1		T92	1		T41	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	260	1			T2	1		T12	1		T27	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	276	1			T2	3		T12	1		T15	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	31	1			T38	1		T41	1		T181	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T161	1		T41	2		T157	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T27	1		T39	1		T181	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	23	1			T27	1		T39	1		T41	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T29	1		T172	2		T173	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T2	1		T27	1		T161	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	8	1			T29	1		T172	1		T174	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T38	1		T183	1		T219	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	246	1			T2	5		T3	1		T27	3
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	274	1			T2	3		T3	1		T27	5
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	26	1			T27	1		T161	2		T39	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T46	1		T37	1		T41	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	16	1			T38	2		T29	1		T174	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	14	1			T181	1		T183	2		T216	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	32	1			T27	1		T20	2		T173	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	33	1			T2	1		T27	1		T29	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T181	1		T173	1		T167	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	9	1			T39	1		T172	1		T173	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	270	1			T2	4		T15	2		T27	4
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	250	1			T2	2		T27	1		T46	3
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	31	1			T15	1		T164	2		T20	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	25	1			T2	1		T164	2		T39	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T39	1		T38	1		T216	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T27	1		T161	1		T39	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T2	1		T38	1		T40	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	19	1			T181	1		T29	1		T199	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	10	1			T38	1		T199	1		T204	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T181	1		T172	1		T199	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	249	1			T1	1		T2	2		T12	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	265	1			T1	1		T12	2		T27	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	20	1			T164	1		T37	2		T29	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	37	1			T164	1		T39	2		T38	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T92	2		T157	1		T172	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	31	1			T2	1		T15	1		T27	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T27	1		T172	1		T174	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	22	1			T2	1		T15	1		T39	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T15	1		T20	1		T174	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T181	1		T156	2		T217	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	247	1			T2	2		T3	2		T27	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	235	1			T3	2		T27	3		T194	1