Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1782

1

T2

4

T4

6

T6

1

auto[1]

1748

1

T2

1

T4

4

T6

1

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1948

1

T2

3

T6

2

T11

14

auto[1]

1582

1

T2

2

T4

10

T35

3

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2803

1

T2

4

T4

10

T6

1

auto[1]

727

1

T2

1

T6

1

T11

1

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	660	1			T2	2		T4	1		T11	4
valid[1]	746	1			T2	1		T4	4		T11	2
valid[2]	708	1			T2	1		T4	2		T6	1
valid[3]	706	1			T4	1		T24	1		T26	3
valid[4]	710	1			T2	1		T4	2		T6	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	112	1			T2	1		T26	1		T35	5
auto[0]	auto[0]	valid[0]	auto[1]	154	1			T2	1		T71	1		T74	1
auto[0]	auto[0]	valid[1]	auto[0]	134	1			T11	1		T24	1		T26	1
auto[0]	auto[0]	valid[1]	auto[1]	151	1			T4	3		T35	1		T71	1
auto[0]	auto[0]	valid[2]	auto[0]	121	1			T2	1		T11	4		T24	1
auto[0]	auto[0]	valid[2]	auto[1]	173	1			T4	1		T74	3		T46	1
auto[0]	auto[0]	valid[3]	auto[0]	118	1			T24	1		T35	2		T73	1
auto[0]	auto[0]	valid[3]	auto[1]	157	1			T4	1		T74	1		T150	2
auto[0]	auto[0]	valid[4]	auto[0]	133	1			T11	1		T26	1		T35	1
auto[0]	auto[0]	valid[4]	auto[1]	160	1			T4	1		T74	4		T150	1
auto[0]	auto[1]	valid[0]	auto[0]	88	1			T11	3		T35	2		T17	1
auto[0]	auto[1]	valid[0]	auto[1]	158	1			T4	1		T35	1		T74	2
auto[0]	auto[1]	valid[1]	auto[0]	135	1			T11	1		T26	1		T27	1
auto[0]	auto[1]	valid[1]	auto[1]	175	1			T4	1		T71	1		T74	1
auto[0]	auto[1]	valid[2]	auto[0]	115	1			T6	1		T11	1		T26	2
auto[0]	auto[1]	valid[2]	auto[1]	150	1			T4	1		T150	4		T316	1
auto[0]	auto[1]	valid[3]	auto[0]	133	1			T26	3		T35	1		T17	4
auto[0]	auto[1]	valid[3]	auto[1]	162	1			T74	4		T150	1		T316	1
auto[0]	auto[1]	valid[4]	auto[0]	132	1			T11	2		T24	1		T17	3
auto[0]	auto[1]	valid[4]	auto[1]	142	1			T2	1		T4	1		T35	1
auto[1]	auto[0]	valid[0]	auto[0]	76	1			T11	1		T15	1		T35	2
auto[1]	auto[0]	valid[1]	auto[0]	71	1			T2	1		T35	3		T73	1
auto[1]	auto[0]	valid[2]	auto[0]	85	1			T24	1		T35	1		T17	1
auto[1]	auto[0]	valid[3]	auto[0]	69	1			T35	1		T17	2		T71	1
auto[1]	auto[0]	valid[4]	auto[0]	68	1			T6	1		T26	1		T17	4
auto[1]	auto[1]	valid[0]	auto[0]	72	1			T24	1		T26	1		T35	2
auto[1]	auto[1]	valid[1]	auto[0]	80	1			T35	3		T71	1		T311	1
auto[1]	auto[1]	valid[2]	auto[0]	64	1			T38	1		T160	2		T309	2
auto[1]	auto[1]	valid[3]	auto[0]	67	1			T35	1		T71	1		T20	1
auto[1]	auto[1]	valid[4]	auto[0]	75	1			T35	1		T17	1		T71	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal