Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	825	1			T16	24		T35	10		T17	14
all_values[1]	825	1			T16	24		T35	10		T17	14
all_values[2]	825	1			T16	24		T35	10		T17	14
all_values[3]	825	1			T16	24		T35	10		T17	14
all_values[4]	825	1			T16	24		T35	10		T17	14
all_values[5]	825	1			T16	24		T35	10		T17	14
all_values[6]	825	1			T16	24		T35	10		T17	14
all_values[7]	825	1			T16	24		T35	10		T17	14

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3533

1

T16

97

T35

23

T17

60

auto[1]

3067

1

T16

95

T35

57

T17

52

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2568

1

T16

63

T35

40

T17

37

auto[1]

4032

1

T16

129

T35

40

T17

75

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3743

1

T16

96

T35

49

T17

61

auto[1]

2857

1

T16

96

T35

31

T17

51

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	155	1			T16	4		T17	4		T19	1
all_values[0]	auto[0]	auto[0]	auto[1]	90	1			T16	3		T35	1		T17	1
all_values[0]	auto[0]	auto[1]	auto[0]	137	1			T16	2		T17	5		T19	3
all_values[0]	auto[0]	auto[1]	auto[1]	78	1			T16	3		T35	1		T21	4
all_values[0]	auto[1]	auto[0]	auto[1]	215	1			T16	7		T35	4		T17	2
all_values[0]	auto[1]	auto[1]	auto[1]	150	1			T16	5		T35	4		T17	2
all_values[1]	auto[0]	auto[0]	auto[0]	161	1			T16	7		T17	4		T19	2
all_values[1]	auto[0]	auto[0]	auto[1]	95	1			T16	1		T35	1		T17	3
all_values[1]	auto[0]	auto[1]	auto[0]	137	1			T16	4		T35	6		T17	1
all_values[1]	auto[0]	auto[1]	auto[1]	80	1			T17	1		T19	2		T21	3
all_values[1]	auto[1]	auto[0]	auto[1]	191	1			T16	6		T17	2		T20	1
all_values[1]	auto[1]	auto[1]	auto[1]	161	1			T16	6		T35	3		T17	3
all_values[2]	auto[0]	auto[0]	auto[0]	183	1			T16	4		T35	4		T17	1
all_values[2]	auto[0]	auto[0]	auto[1]	86	1			T16	5		T17	3		T19	2
all_values[2]	auto[0]	auto[1]	auto[0]	135	1			T35	4		T17	3		T20	2
all_values[2]	auto[0]	auto[1]	auto[1]	80	1			T16	2		T17	1		T21	2
all_values[2]	auto[1]	auto[0]	auto[1]	177	1			T16	8		T35	1		T17	2
all_values[2]	auto[1]	auto[1]	auto[1]	164	1			T16	5		T35	1		T17	4
all_values[3]	auto[0]	auto[0]	auto[0]	174	1			T16	2		T17	6		T19	4
all_values[3]	auto[0]	auto[0]	auto[1]	87	1			T16	3		T35	1		T20	1
all_values[3]	auto[0]	auto[1]	auto[0]	125	1			T16	3		T35	1		T17	1
all_values[3]	auto[0]	auto[1]	auto[1]	72	1			T16	2		T35	1		T17	1
all_values[3]	auto[1]	auto[0]	auto[1]	189	1			T16	4		T35	1		T17	4
all_values[3]	auto[1]	auto[1]	auto[1]	178	1			T16	10		T35	6		T17	2
all_values[4]	auto[0]	auto[0]	auto[0]	162	1			T16	3		T35	3		T19	4
all_values[4]	auto[0]	auto[0]	auto[1]	87	1			T16	3		T17	3		T20	1
all_values[4]	auto[0]	auto[1]	auto[0]	163	1			T16	2		T35	3		T17	1
all_values[4]	auto[0]	auto[1]	auto[1]	77	1			T16	4		T35	2		T17	3
all_values[4]	auto[1]	auto[0]	auto[1]	173	1			T16	5		T17	4		T20	2
all_values[4]	auto[1]	auto[1]	auto[1]	163	1			T16	7		T35	2		T17	3
all_values[5]	auto[0]	auto[0]	auto[0]	256	1			T16	4		T35	2		T17	3
all_values[5]	auto[0]	auto[1]	auto[0]	207	1			T16	7		T35	4		T17	1
all_values[5]	auto[1]	auto[0]	auto[1]	183	1			T16	7		T17	4		T19	2
all_values[5]	auto[1]	auto[1]	auto[1]	179	1			T16	6		T35	4		T17	6
all_values[6]	auto[0]	auto[0]	auto[0]	137	1			T16	5		T35	1		T17	1
all_values[6]	auto[0]	auto[0]	auto[1]	92	1			T16	1		T35	1		T17	1
all_values[6]	auto[0]	auto[1]	auto[0]	157	1			T16	9		T35	6		T17	1
all_values[6]	auto[0]	auto[1]	auto[1]	79	1			T16	1		T17	3		T22	1
all_values[6]	auto[1]	auto[0]	auto[1]	189	1			T16	2		T35	1		T17	4
all_values[6]	auto[1]	auto[1]	auto[1]	171	1			T16	6		T35	1		T17	4
all_values[7]	auto[0]	auto[0]	auto[0]	151	1			T16	3		T35	1		T17	1
all_values[7]	auto[0]	auto[0]	auto[1]	96	1			T16	2		T17	3		T20	1
all_values[7]	auto[0]	auto[1]	auto[0]	128	1			T16	4		T35	5		T17	4
all_values[7]	auto[0]	auto[1]	auto[1]	76	1			T16	3		T35	1		T17	1
all_values[7]	auto[1]	auto[0]	auto[1]	204	1			T16	8		T35	1		T17	4
all_values[7]	auto[1]	auto[1]	auto[1]	170	1			T16	4		T35	2		T17	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal