Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47559

1

T2

207

T5

9

T6

101

auto[1]

16085

1

T2

63

T4

139

T6

8

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46189

1

T2

187

T4

139

T5

3

auto[1]

17455

1

T2

83

T5

6

T6

32

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	32689	1			T2	136		T4	75		T5	3
others[1]	5508	1			T2	22		T4	13		T5	1
others[2]	5305	1			T2	26		T4	11		T6	12
others[3]	6054	1			T2	30		T4	2		T5	1
interest[1]	3501	1			T2	8		T4	5		T5	1
interest[4]	21260	1			T2	83		T4	52		T5	2
interest[64]	10587	1			T2	48		T4	33		T5	3

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15558	1			T2	63		T5	1		T6	33
auto[0]	auto[0]	others[1]	2589	1			T2	12		T5	1		T6	5
auto[0]	auto[0]	others[2]	2473	1			T2	12		T6	5		T7	1
auto[0]	auto[0]	others[3]	2819	1			T2	15		T6	7		T11	22
auto[0]	auto[0]	interest[1]	1671	1			T2	4		T5	1		T6	5
auto[0]	auto[0]	interest[4]	10001	1			T2	39		T5	1		T6	22
auto[0]	auto[0]	interest[64]	4994	1			T2	18		T6	14		T11	55
auto[0]	auto[1]	others[0]	8275	1			T2	30		T4	75		T6	4
auto[0]	auto[1]	others[1]	1371	1			T2	6		T4	13		T6	1
auto[0]	auto[1]	others[2]	1356	1			T2	6		T4	11		T6	2
auto[0]	auto[1]	others[3]	1520	1			T2	6		T4	2		T15	1
auto[0]	auto[1]	interest[1]	877	1			T2	2		T4	5		T6	1
auto[0]	auto[1]	interest[4]	5539	1			T2	16		T4	52		T6	3
auto[0]	auto[1]	interest[64]	2686	1			T2	13		T4	33		T15	5
auto[1]	auto[0]	others[0]	8856	1			T2	43		T5	2		T6	15
auto[1]	auto[0]	others[1]	1548	1			T2	4		T6	4		T11	6
auto[1]	auto[0]	others[2]	1476	1			T2	8		T6	5		T7	1
auto[1]	auto[0]	others[3]	1715	1			T2	9		T5	1		T6	3
auto[1]	auto[0]	interest[1]	953	1			T2	2		T6	1		T11	4
auto[1]	auto[0]	interest[4]	5720	1			T2	28		T5	1		T6	10
auto[1]	auto[0]	interest[64]	2907	1			T2	17		T5	3		T6	4

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal