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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.00 98.30 93.94 98.62 89.36 97.14 95.45 99.20


Total test records in report: 1081
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T1006 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1553602752 Jun 11 12:39:48 PM PDT 24 Jun 11 12:39:53 PM PDT 24 116366802 ps
T1007 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2902079499 Jun 11 12:39:25 PM PDT 24 Jun 11 12:39:28 PM PDT 24 228301951 ps
T80 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2402177051 Jun 11 12:39:19 PM PDT 24 Jun 11 12:39:22 PM PDT 24 21174045 ps
T1008 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3817004441 Jun 11 12:39:55 PM PDT 24 Jun 11 12:39:57 PM PDT 24 28477543 ps
T1009 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1639704776 Jun 11 12:39:12 PM PDT 24 Jun 11 12:39:14 PM PDT 24 41644747 ps
T1010 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1108272936 Jun 11 12:39:43 PM PDT 24 Jun 11 12:39:48 PM PDT 24 48205215 ps
T1011 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.318679689 Jun 11 12:39:24 PM PDT 24 Jun 11 12:39:49 PM PDT 24 2470048597 ps
T1012 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3876626194 Jun 11 12:39:24 PM PDT 24 Jun 11 12:39:26 PM PDT 24 98509925 ps
T247 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.186710700 Jun 11 12:39:24 PM PDT 24 Jun 11 12:39:31 PM PDT 24 80893911 ps
T1013 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2677120862 Jun 11 12:39:41 PM PDT 24 Jun 11 12:39:59 PM PDT 24 2591650671 ps
T1014 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1753377760 Jun 11 12:39:49 PM PDT 24 Jun 11 12:39:51 PM PDT 24 18789667 ps
T1015 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2925643268 Jun 11 12:39:10 PM PDT 24 Jun 11 12:39:18 PM PDT 24 3874465112 ps
T1016 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.4216654176 Jun 11 12:39:31 PM PDT 24 Jun 11 12:39:32 PM PDT 24 45422653 ps
T1017 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2041499778 Jun 11 12:39:41 PM PDT 24 Jun 11 12:39:46 PM PDT 24 585559045 ps
T1018 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2560652574 Jun 11 12:39:25 PM PDT 24 Jun 11 12:39:28 PM PDT 24 251722101 ps
T1019 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.524632737 Jun 11 12:39:40 PM PDT 24 Jun 11 12:39:45 PM PDT 24 153649191 ps
T1020 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1379939389 Jun 11 12:39:22 PM PDT 24 Jun 11 12:39:26 PM PDT 24 76448425 ps
T1021 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2181996343 Jun 11 12:39:24 PM PDT 24 Jun 11 12:39:25 PM PDT 24 41458035 ps
T1022 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2929975173 Jun 11 12:39:45 PM PDT 24 Jun 11 12:39:49 PM PDT 24 69189873 ps
T1023 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.767234200 Jun 11 12:39:19 PM PDT 24 Jun 11 12:39:23 PM PDT 24 488764562 ps
T1024 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3951182466 Jun 11 12:39:49 PM PDT 24 Jun 11 12:39:51 PM PDT 24 12738549 ps
T1025 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.203117248 Jun 11 12:39:43 PM PDT 24 Jun 11 12:39:48 PM PDT 24 172100119 ps
T1026 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2234995389 Jun 11 12:39:42 PM PDT 24 Jun 11 12:39:45 PM PDT 24 19074907 ps
T1027 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2467704809 Jun 11 12:39:41 PM PDT 24 Jun 11 12:39:44 PM PDT 24 15284669 ps
T249 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3965935716 Jun 11 12:39:40 PM PDT 24 Jun 11 12:40:01 PM PDT 24 597126126 ps
T1028 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.4246216190 Jun 11 12:39:40 PM PDT 24 Jun 11 12:39:44 PM PDT 24 43030251 ps
T1029 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.582120269 Jun 11 12:39:09 PM PDT 24 Jun 11 12:39:10 PM PDT 24 13276917 ps
T1030 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.4188802685 Jun 11 12:39:42 PM PDT 24 Jun 11 12:39:51 PM PDT 24 108834652 ps
T1031 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.23296625 Jun 11 12:39:41 PM PDT 24 Jun 11 12:39:43 PM PDT 24 32415396 ps
T1032 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.938528656 Jun 11 12:39:42 PM PDT 24 Jun 11 12:39:46 PM PDT 24 262535155 ps
T1033 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.10213073 Jun 11 12:39:22 PM PDT 24 Jun 11 12:39:35 PM PDT 24 183321319 ps
T1034 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1648792766 Jun 11 12:39:18 PM PDT 24 Jun 11 12:39:42 PM PDT 24 357378645 ps
T1035 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2791649824 Jun 11 12:39:40 PM PDT 24 Jun 11 12:39:44 PM PDT 24 127302947 ps
T1036 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2888915737 Jun 11 12:39:42 PM PDT 24 Jun 11 12:39:45 PM PDT 24 16352904 ps
T1037 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3914086651 Jun 11 12:39:19 PM PDT 24 Jun 11 12:39:44 PM PDT 24 4818137354 ps
T1038 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2283200464 Jun 11 12:39:07 PM PDT 24 Jun 11 12:39:08 PM PDT 24 52676545 ps
T1039 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1559839319 Jun 11 12:39:41 PM PDT 24 Jun 11 12:39:58 PM PDT 24 548276516 ps
T1040 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3077277802 Jun 11 12:39:20 PM PDT 24 Jun 11 12:39:24 PM PDT 24 112421781 ps
T1041 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.281707966 Jun 11 12:39:42 PM PDT 24 Jun 11 12:39:46 PM PDT 24 107785589 ps
T1042 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.299665831 Jun 11 12:39:51 PM PDT 24 Jun 11 12:39:53 PM PDT 24 11940640 ps
T1043 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1444340515 Jun 11 12:39:40 PM PDT 24 Jun 11 12:39:42 PM PDT 24 12590194 ps
T1044 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3749595482 Jun 11 12:39:48 PM PDT 24 Jun 11 12:39:51 PM PDT 24 113627890 ps
T81 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.911427 Jun 11 12:39:10 PM PDT 24 Jun 11 12:39:12 PM PDT 24 79226728 ps
T248 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3959563861 Jun 11 12:39:40 PM PDT 24 Jun 11 12:39:46 PM PDT 24 3015988302 ps
T1045 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2135810725 Jun 11 12:39:25 PM PDT 24 Jun 11 12:39:26 PM PDT 24 35099536 ps
T1046 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1894879016 Jun 11 12:39:51 PM PDT 24 Jun 11 12:39:53 PM PDT 24 13332247 ps
T1047 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1013001422 Jun 11 12:39:29 PM PDT 24 Jun 11 12:39:32 PM PDT 24 227579619 ps
T1048 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3393280153 Jun 11 12:39:19 PM PDT 24 Jun 11 12:39:20 PM PDT 24 11114025 ps
T1049 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.105283785 Jun 11 12:39:11 PM PDT 24 Jun 11 12:39:15 PM PDT 24 109015262 ps
T1050 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1099095533 Jun 11 12:39:44 PM PDT 24 Jun 11 12:39:55 PM PDT 24 1464842507 ps
T1051 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.4217093659 Jun 11 12:39:12 PM PDT 24 Jun 11 12:39:14 PM PDT 24 33785798 ps
T1052 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.4274565849 Jun 11 12:39:52 PM PDT 24 Jun 11 12:39:54 PM PDT 24 17235146 ps
T1053 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1973557017 Jun 11 12:39:44 PM PDT 24 Jun 11 12:39:49 PM PDT 24 219369381 ps
T1054 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1224800310 Jun 11 12:39:11 PM PDT 24 Jun 11 12:39:15 PM PDT 24 91302997 ps
T1055 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.4212467361 Jun 11 12:39:45 PM PDT 24 Jun 11 12:39:51 PM PDT 24 151005610 ps
T1056 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.780111761 Jun 11 12:39:29 PM PDT 24 Jun 11 12:39:32 PM PDT 24 109088255 ps
T1057 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1423243790 Jun 11 12:39:19 PM PDT 24 Jun 11 12:39:22 PM PDT 24 142054845 ps
T1058 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1018188866 Jun 11 12:39:12 PM PDT 24 Jun 11 12:39:14 PM PDT 24 134329319 ps
T1059 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1165334542 Jun 11 12:39:31 PM PDT 24 Jun 11 12:39:34 PM PDT 24 189805178 ps
T1060 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2260057333 Jun 11 12:39:10 PM PDT 24 Jun 11 12:39:11 PM PDT 24 12091482 ps
T1061 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2597408841 Jun 11 12:39:29 PM PDT 24 Jun 11 12:39:31 PM PDT 24 144107301 ps
T1062 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.863471371 Jun 11 12:39:27 PM PDT 24 Jun 11 12:39:29 PM PDT 24 13488746 ps
T1063 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2363045309 Jun 11 12:39:54 PM PDT 24 Jun 11 12:39:56 PM PDT 24 39544558 ps
T1064 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.661341463 Jun 11 12:39:46 PM PDT 24 Jun 11 12:39:49 PM PDT 24 18906913 ps
T1065 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.4073222168 Jun 11 12:39:41 PM PDT 24 Jun 11 12:39:48 PM PDT 24 569027444 ps
T1066 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3219454904 Jun 11 12:39:00 PM PDT 24 Jun 11 12:39:03 PM PDT 24 35551642 ps
T1067 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3060490219 Jun 11 12:39:41 PM PDT 24 Jun 11 12:39:46 PM PDT 24 118936258 ps
T1068 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1989065780 Jun 11 12:39:29 PM PDT 24 Jun 11 12:39:33 PM PDT 24 131277504 ps
T1069 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1895757986 Jun 11 12:39:40 PM PDT 24 Jun 11 12:39:44 PM PDT 24 48906816 ps
T1070 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3496273801 Jun 11 12:39:41 PM PDT 24 Jun 11 12:39:44 PM PDT 24 20335358 ps
T1071 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3765337239 Jun 11 12:39:19 PM PDT 24 Jun 11 12:39:33 PM PDT 24 208547383 ps
T1072 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3861021582 Jun 11 12:39:39 PM PDT 24 Jun 11 12:39:41 PM PDT 24 66314391 ps
T1073 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.525148262 Jun 11 12:39:13 PM PDT 24 Jun 11 12:39:16 PM PDT 24 69377707 ps
T1074 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1007554218 Jun 11 12:39:09 PM PDT 24 Jun 11 12:39:23 PM PDT 24 214521552 ps
T1075 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3306792318 Jun 11 12:39:13 PM PDT 24 Jun 11 12:39:15 PM PDT 24 141721515 ps
T1076 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1316430983 Jun 11 12:39:54 PM PDT 24 Jun 11 12:39:57 PM PDT 24 18334676 ps
T1077 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1464399031 Jun 11 12:39:17 PM PDT 24 Jun 11 12:39:51 PM PDT 24 2568319144 ps
T1078 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3422486472 Jun 11 12:39:47 PM PDT 24 Jun 11 12:39:50 PM PDT 24 214947477 ps
T1079 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1527208124 Jun 11 12:39:28 PM PDT 24 Jun 11 12:39:32 PM PDT 24 78029573 ps
T1080 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2800122010 Jun 11 12:39:11 PM PDT 24 Jun 11 12:39:14 PM PDT 24 197535364 ps
T1081 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1796647372 Jun 11 12:39:22 PM PDT 24 Jun 11 12:39:24 PM PDT 24 38195317 ps

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.224428241
Short name T2
Test name
Test status
Simulation time 25692473308 ps
CPU time 281.79 seconds
Started Jun 11 12:45:49 PM PDT 24
Finished Jun 11 12:50:34 PM PDT 24
Peak memory 266040 kb
Host smart-5260361c-84c2-4ae8-b1f8-1432c942a75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224428241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.224428241
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.1977749738
Short name T35
Test name
Test status
Simulation time 27819070429 ps
CPU time 344.51 seconds
Started Jun 11 12:46:55 PM PDT 24
Finished Jun 11 12:52:41 PM PDT 24
Peak memory 267448 kb
Host smart-b78fe39e-99e2-4767-8197-250e66fa5be7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977749738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.1977749738
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.1718094154
Short name T15
Test name
Test status
Simulation time 3397869074 ps
CPU time 22.94 seconds
Started Jun 11 12:46:02 PM PDT 24
Finished Jun 11 12:46:27 PM PDT 24
Peak memory 241412 kb
Host smart-9dc71e14-fe14-4f09-893b-d201e262349d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718094154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.1718094154
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.155152693
Short name T29
Test name
Test status
Simulation time 18576311982 ps
CPU time 241.14 seconds
Started Jun 11 12:46:18 PM PDT 24
Finished Jun 11 12:50:23 PM PDT 24
Peak memory 284808 kb
Host smart-1df16253-bb0e-4f78-8935-28b4df9cb714
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155152693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stres
s_all.155152693
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.619364211
Short name T91
Test name
Test status
Simulation time 2178105226 ps
CPU time 23.42 seconds
Started Jun 11 12:39:49 PM PDT 24
Finished Jun 11 12:40:14 PM PDT 24
Peak memory 215672 kb
Host smart-ebcf28a0-206f-4c09-8e14-37bc00f70f0c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619364211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device
_tl_intg_err.619364211
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.3927893980
Short name T64
Test name
Test status
Simulation time 32750177 ps
CPU time 0.74 seconds
Started Jun 11 12:45:22 PM PDT 24
Finished Jun 11 12:45:26 PM PDT 24
Peak memory 216432 kb
Host smart-afbd2101-3892-4d5e-bfd5-4e1d098062da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927893980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.3927893980
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.1248511867
Short name T39
Test name
Test status
Simulation time 39829327068 ps
CPU time 150.7 seconds
Started Jun 11 12:46:29 PM PDT 24
Finished Jun 11 12:49:02 PM PDT 24
Peak memory 265964 kb
Host smart-134c3aa1-da72-4ed3-bd66-16fcc0f15df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248511867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.1248511867
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.3650926288
Short name T47
Test name
Test status
Simulation time 277997830052 ps
CPU time 1257.87 seconds
Started Jun 11 12:47:08 PM PDT 24
Finished Jun 11 01:08:09 PM PDT 24
Peak memory 282356 kb
Host smart-728d5cef-35a2-40ef-bfd1-8fb490c6f1bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650926288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.3650926288
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.4105674944
Short name T20
Test name
Test status
Simulation time 118068139362 ps
CPU time 559 seconds
Started Jun 11 12:46:58 PM PDT 24
Finished Jun 11 12:56:20 PM PDT 24
Peak memory 274060 kb
Host smart-fceed01b-a73e-4013-8b4f-0d099d2a5419
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105674944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.4105674944
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.96954915
Short name T178
Test name
Test status
Simulation time 71476513422 ps
CPU time 143.35 seconds
Started Jun 11 12:47:03 PM PDT 24
Finished Jun 11 12:49:30 PM PDT 24
Peak memory 257524 kb
Host smart-fac38f15-c019-413a-a6f0-a8407ff40ba0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96954915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stress
_all.96954915
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.1944016322
Short name T18
Test name
Test status
Simulation time 83475605 ps
CPU time 1.23 seconds
Started Jun 11 12:45:38 PM PDT 24
Finished Jun 11 12:45:43 PM PDT 24
Peak memory 235376 kb
Host smart-68aadb2c-61cd-447a-abbb-cde5bf9bf170
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944016322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.1944016322
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.4009327240
Short name T90
Test name
Test status
Simulation time 152803409 ps
CPU time 3.83 seconds
Started Jun 11 12:39:46 PM PDT 24
Finished Jun 11 12:39:52 PM PDT 24
Peak memory 215144 kb
Host smart-c7026f76-354b-4bca-b453-32bae4a5aee9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009327240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
4009327240
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.349704546
Short name T14
Test name
Test status
Simulation time 236523473 ps
CPU time 3.87 seconds
Started Jun 11 12:46:09 PM PDT 24
Finished Jun 11 12:46:15 PM PDT 24
Peak memory 220768 kb
Host smart-bd6df1da-3924-4bd8-89f8-05b3ac60b9b8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=349704546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dire
ct.349704546
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.1318772369
Short name T38
Test name
Test status
Simulation time 84945870489 ps
CPU time 787.34 seconds
Started Jun 11 12:46:29 PM PDT 24
Finished Jun 11 12:59:38 PM PDT 24
Peak memory 273092 kb
Host smart-a9f7f574-1843-4cf4-ad1f-b577e50a7950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318772369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.1318772369
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.3821896059
Short name T240
Test name
Test status
Simulation time 15464790437 ps
CPU time 120.69 seconds
Started Jun 11 12:45:56 PM PDT 24
Finished Jun 11 12:47:59 PM PDT 24
Peak memory 253120 kb
Host smart-57a7074f-99fd-4dac-8799-9bb568557088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821896059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.3821896059
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1035811860
Short name T108
Test name
Test status
Simulation time 55558689 ps
CPU time 1.78 seconds
Started Jun 11 12:39:17 PM PDT 24
Finished Jun 11 12:39:20 PM PDT 24
Peak memory 215004 kb
Host smart-e3a3d680-a386-4a1e-9b26-f1cb3f194548
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035811860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1
035811860
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.3144352033
Short name T156
Test name
Test status
Simulation time 25224158915 ps
CPU time 148.15 seconds
Started Jun 11 12:46:15 PM PDT 24
Finished Jun 11 12:48:46 PM PDT 24
Peak memory 265756 kb
Host smart-2c10d763-b388-49fe-83c9-19e2babe953f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144352033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.3144352033
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.13608580
Short name T210
Test name
Test status
Simulation time 288894837600 ps
CPU time 252.83 seconds
Started Jun 11 12:46:57 PM PDT 24
Finished Jun 11 12:51:13 PM PDT 24
Peak memory 257396 kb
Host smart-5714837b-9937-4ff9-9f1d-a7a47f75b3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13608580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.13608580
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.545003813
Short name T174
Test name
Test status
Simulation time 34563174286 ps
CPU time 368.29 seconds
Started Jun 11 12:46:19 PM PDT 24
Finished Jun 11 12:52:31 PM PDT 24
Peak memory 265304 kb
Host smart-4fe8da75-211d-4190-9bf3-0347d29b78ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545003813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stres
s_all.545003813
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.3421529725
Short name T146
Test name
Test status
Simulation time 81348324510 ps
CPU time 801.43 seconds
Started Jun 11 12:46:13 PM PDT 24
Finished Jun 11 12:59:38 PM PDT 24
Peak memory 273704 kb
Host smart-1b25ccc8-4990-445a-b19c-31c4c767cce0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421529725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.3421529725
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.613074152
Short name T168
Test name
Test status
Simulation time 8423813901 ps
CPU time 132.21 seconds
Started Jun 11 12:46:56 PM PDT 24
Finished Jun 11 12:49:11 PM PDT 24
Peak memory 266520 kb
Host smart-98dac903-9673-4d1b-832f-26fffaeb4764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613074152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.613074152
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.1457945345
Short name T208
Test name
Test status
Simulation time 582490079977 ps
CPU time 583.1 seconds
Started Jun 11 12:46:02 PM PDT 24
Finished Jun 11 12:55:52 PM PDT 24
Peak memory 283832 kb
Host smart-d016eba5-f3a1-4d58-b0b1-18aa33009c94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457945345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.1457945345
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.2409484114
Short name T295
Test name
Test status
Simulation time 713190803 ps
CPU time 20.47 seconds
Started Jun 11 12:47:02 PM PDT 24
Finished Jun 11 12:47:26 PM PDT 24
Peak memory 241164 kb
Host smart-1202480f-f6e3-47ee-918d-4823756890d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409484114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.2409484114
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.1641771648
Short name T32
Test name
Test status
Simulation time 14744542 ps
CPU time 0.72 seconds
Started Jun 11 12:45:24 PM PDT 24
Finished Jun 11 12:45:26 PM PDT 24
Peak memory 205128 kb
Host smart-4f36006e-53dc-498a-9bd2-b954e4a2b885
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641771648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.1
641771648
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.93601412
Short name T157
Test name
Test status
Simulation time 50623592006 ps
CPU time 161.63 seconds
Started Jun 11 12:47:25 PM PDT 24
Finished Jun 11 12:50:10 PM PDT 24
Peak memory 255852 kb
Host smart-244e0674-6ed7-4ff4-9a81-53d7599153c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93601412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.93601412
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.1340168330
Short name T8
Test name
Test status
Simulation time 9717273408 ps
CPU time 36.85 seconds
Started Jun 11 12:46:18 PM PDT 24
Finished Jun 11 12:46:59 PM PDT 24
Peak memory 244704 kb
Host smart-6803c4a6-071e-4168-b358-0a2762ad7fbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1340168330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.1340168330
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3959563861
Short name T248
Test name
Test status
Simulation time 3015988302 ps
CPU time 4.35 seconds
Started Jun 11 12:39:40 PM PDT 24
Finished Jun 11 12:39:46 PM PDT 24
Peak memory 215436 kb
Host smart-3a4f2e9f-f38f-4a06-a82e-7474a62b5caf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959563861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
3959563861
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.3632113550
Short name T4
Test name
Test status
Simulation time 1137919053 ps
CPU time 5 seconds
Started Jun 11 12:46:25 PM PDT 24
Finished Jun 11 12:46:32 PM PDT 24
Peak memory 216460 kb
Host smart-e870414d-d294-4bf9-b347-9d2cd446477e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632113550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.3632113550
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.3965935716
Short name T249
Test name
Test status
Simulation time 597126126 ps
CPU time 18.98 seconds
Started Jun 11 12:39:40 PM PDT 24
Finished Jun 11 12:40:01 PM PDT 24
Peak memory 215112 kb
Host smart-c3ad4205-43c5-45bb-87a5-967a6ed11493
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965935716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.3965935716
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.3299450285
Short name T221
Test name
Test status
Simulation time 94097532667 ps
CPU time 201.53 seconds
Started Jun 11 12:47:12 PM PDT 24
Finished Jun 11 12:50:37 PM PDT 24
Peak memory 249648 kb
Host smart-5c3e8b88-0d86-4847-b30d-2413cd52be43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299450285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.3299450285
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.2224093770
Short name T172
Test name
Test status
Simulation time 28292948080 ps
CPU time 120.45 seconds
Started Jun 11 12:46:19 PM PDT 24
Finished Jun 11 12:48:24 PM PDT 24
Peak memory 257656 kb
Host smart-ed156bc6-5acb-45a7-be82-4b71df2f6fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224093770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.2224093770
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.1432319913
Short name T183
Test name
Test status
Simulation time 34165163785 ps
CPU time 159.49 seconds
Started Jun 11 12:46:24 PM PDT 24
Finished Jun 11 12:49:06 PM PDT 24
Peak memory 249480 kb
Host smart-5ca4e406-7a38-4eb2-bdac-f11fa6a07631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432319913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.1432319913
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.3601997105
Short name T219
Test name
Test status
Simulation time 22786841790 ps
CPU time 115.19 seconds
Started Jun 11 12:45:49 PM PDT 24
Finished Jun 11 12:47:47 PM PDT 24
Peak memory 255564 kb
Host smart-64eb9db4-5a0c-4ac5-99a4-64923f497535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601997105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.3601997105
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.2604666822
Short name T256
Test name
Test status
Simulation time 9674171236 ps
CPU time 23.95 seconds
Started Jun 11 12:45:38 PM PDT 24
Finished Jun 11 12:46:06 PM PDT 24
Peak memory 238740 kb
Host smart-7a3c1493-dcf9-422b-963a-ddfa76b9c7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604666822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.2604666822
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.1380762340
Short name T177
Test name
Test status
Simulation time 27209411243 ps
CPU time 169.48 seconds
Started Jun 11 12:46:25 PM PDT 24
Finished Jun 11 12:49:17 PM PDT 24
Peak memory 255200 kb
Host smart-33b63a57-11e4-457d-92cb-a009c8d3e513
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380762340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.1380762340
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.1124495519
Short name T181
Test name
Test status
Simulation time 47916632726 ps
CPU time 336.49 seconds
Started Jun 11 12:46:48 PM PDT 24
Finished Jun 11 12:52:27 PM PDT 24
Peak memory 249496 kb
Host smart-12d92c75-837c-45f4-85d8-38068cfe0eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124495519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.1124495519
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.3756007127
Short name T299
Test name
Test status
Simulation time 2607470363 ps
CPU time 15.24 seconds
Started Jun 11 12:45:41 PM PDT 24
Finished Jun 11 12:46:01 PM PDT 24
Peak memory 233116 kb
Host smart-d1c4c081-5774-45d1-ac9e-837f9d826673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756007127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.3756007127
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.1524302472
Short name T229
Test name
Test status
Simulation time 1873599377 ps
CPU time 34.63 seconds
Started Jun 11 12:45:54 PM PDT 24
Finished Jun 11 12:46:30 PM PDT 24
Peak memory 241224 kb
Host smart-16ce3db7-19b6-4225-bc7f-4d172650b264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524302472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.1524302472
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.1588670955
Short name T3
Test name
Test status
Simulation time 21248644898 ps
CPU time 18.13 seconds
Started Jun 11 12:46:45 PM PDT 24
Finished Jun 11 12:47:06 PM PDT 24
Peak memory 230072 kb
Host smart-9650ded3-946f-4751-89b1-4f36ee786d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588670955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.1588670955
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.520175427
Short name T100
Test name
Test status
Simulation time 1150466239 ps
CPU time 18.48 seconds
Started Jun 11 12:39:41 PM PDT 24
Finished Jun 11 12:40:02 PM PDT 24
Peak memory 215064 kb
Host smart-0baccaad-0ec7-43db-9e4c-6c5d3459d6ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520175427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device
_tl_intg_err.520175427
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.1310398048
Short name T251
Test name
Test status
Simulation time 1492973423 ps
CPU time 7.42 seconds
Started Jun 11 12:39:18 PM PDT 24
Finished Jun 11 12:39:26 PM PDT 24
Peak memory 215080 kb
Host smart-91470f14-08ff-4a43-8937-c94f67e31c5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310398048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.1310398048
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.820858697
Short name T220
Test name
Test status
Simulation time 78142247296 ps
CPU time 435.94 seconds
Started Jun 11 12:45:25 PM PDT 24
Finished Jun 11 12:52:43 PM PDT 24
Peak memory 254724 kb
Host smart-4d746d47-a3c2-494f-a85f-1190a0d73ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820858697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.820858697
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.2333626287
Short name T231
Test name
Test status
Simulation time 289246374765 ps
CPU time 621.81 seconds
Started Jun 11 12:46:05 PM PDT 24
Finished Jun 11 12:56:29 PM PDT 24
Peak memory 265820 kb
Host smart-a739553c-4b72-46ab-92c5-cf87eb2626b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333626287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.2333626287
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.894963697
Short name T218
Test name
Test status
Simulation time 64536552066 ps
CPU time 225.35 seconds
Started Jun 11 12:46:04 PM PDT 24
Finished Jun 11 12:49:52 PM PDT 24
Peak memory 251956 kb
Host smart-d61f38c7-2452-4777-893c-e4ffd328e8fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894963697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.894963697
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.2651563650
Short name T5
Test name
Test status
Simulation time 77271448 ps
CPU time 2.54 seconds
Started Jun 11 12:46:13 PM PDT 24
Finished Jun 11 12:46:18 PM PDT 24
Peak memory 216452 kb
Host smart-202544c9-5e8e-43df-bae0-4db8dea058f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651563650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2651563650
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.713532465
Short name T36
Test name
Test status
Simulation time 7697280345 ps
CPU time 9.84 seconds
Started Jun 11 12:45:28 PM PDT 24
Finished Jun 11 12:45:39 PM PDT 24
Peak memory 233140 kb
Host smart-8b28901e-a746-46bf-94f9-53b7893c5937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713532465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.
713532465
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.607273730
Short name T242
Test name
Test status
Simulation time 11414866587 ps
CPU time 74.75 seconds
Started Jun 11 12:46:29 PM PDT 24
Finished Jun 11 12:47:46 PM PDT 24
Peak memory 249420 kb
Host smart-8cf35fe5-c094-42bd-8b28-f0e4ccfbea4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607273730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.607273730
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.3737020141
Short name T273
Test name
Test status
Simulation time 92550743228 ps
CPU time 454.89 seconds
Started Jun 11 12:45:42 PM PDT 24
Finished Jun 11 12:53:21 PM PDT 24
Peak memory 267292 kb
Host smart-26277183-c025-4e4d-8117-c3ebf6312f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737020141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.3737020141
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.910444694
Short name T223
Test name
Test status
Simulation time 10795422759 ps
CPU time 109 seconds
Started Jun 11 12:46:32 PM PDT 24
Finished Jun 11 12:48:24 PM PDT 24
Peak memory 265364 kb
Host smart-139ed699-4a7c-473f-a86d-fdf993d7bde0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910444694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stres
s_all.910444694
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.4273456004
Short name T232
Test name
Test status
Simulation time 44961139378 ps
CPU time 454.8 seconds
Started Jun 11 12:47:20 PM PDT 24
Finished Jun 11 12:54:59 PM PDT 24
Peak memory 265820 kb
Host smart-066619cc-c113-492b-b686-b9495a420e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273456004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.4273456004
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2402177051
Short name T80
Test name
Test status
Simulation time 21174045 ps
CPU time 1.3 seconds
Started Jun 11 12:39:19 PM PDT 24
Finished Jun 11 12:39:22 PM PDT 24
Peak memory 216172 kb
Host smart-25cd2f7e-ea5f-4d22-85e1-1d95604f55e6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402177051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.2402177051
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.4054824382
Short name T98
Test name
Test status
Simulation time 634439233 ps
CPU time 4.16 seconds
Started Jun 11 12:39:41 PM PDT 24
Finished Jun 11 12:39:47 PM PDT 24
Peak memory 215360 kb
Host smart-be8c5fc1-8fee-4e09-acae-7ca37af34492
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054824382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
4054824382
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1007554218
Short name T1074
Test name
Test status
Simulation time 214521552 ps
CPU time 13.32 seconds
Started Jun 11 12:39:09 PM PDT 24
Finished Jun 11 12:39:23 PM PDT 24
Peak memory 206832 kb
Host smart-f1e033c1-917d-4dcc-98fe-08fcbbdc5e96
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007554218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.1007554218
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1464399031
Short name T1077
Test name
Test status
Simulation time 2568319144 ps
CPU time 33.89 seconds
Started Jun 11 12:39:17 PM PDT 24
Finished Jun 11 12:39:51 PM PDT 24
Peak memory 206936 kb
Host smart-431e55cf-1fb9-4541-bdab-34c2861b2d8c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464399031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.1464399031
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2850855938
Short name T980
Test name
Test status
Simulation time 62341980 ps
CPU time 4.22 seconds
Started Jun 11 12:39:20 PM PDT 24
Finished Jun 11 12:39:25 PM PDT 24
Peak memory 218236 kb
Host smart-226e61af-80a8-4b49-913c-08f8b591dd94
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850855938 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2850855938
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1224800310
Short name T1054
Test name
Test status
Simulation time 91302997 ps
CPU time 2.53 seconds
Started Jun 11 12:39:11 PM PDT 24
Finished Jun 11 12:39:15 PM PDT 24
Peak memory 215152 kb
Host smart-45897f69-cd82-4411-8bca-c6d563914bf1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224800310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.1
224800310
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2283200464
Short name T1038
Test name
Test status
Simulation time 52676545 ps
CPU time 0.72 seconds
Started Jun 11 12:39:07 PM PDT 24
Finished Jun 11 12:39:08 PM PDT 24
Peak memory 203488 kb
Host smart-7a4c4ee6-0d11-4679-9ca6-4b36acffeb37
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283200464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
283200464
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3306792318
Short name T1075
Test name
Test status
Simulation time 141721515 ps
CPU time 1.38 seconds
Started Jun 11 12:39:13 PM PDT 24
Finished Jun 11 12:39:15 PM PDT 24
Peak memory 215108 kb
Host smart-dd5e4d46-0566-4924-bec1-c30cd8ee5bfe
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306792318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.3306792318
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1639704776
Short name T1009
Test name
Test status
Simulation time 41644747 ps
CPU time 0.65 seconds
Started Jun 11 12:39:12 PM PDT 24
Finished Jun 11 12:39:14 PM PDT 24
Peak memory 203684 kb
Host smart-4b57f02c-e144-4b86-b4fa-c1e338c701f4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639704776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.1639704776
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2800122010
Short name T1080
Test name
Test status
Simulation time 197535364 ps
CPU time 1.82 seconds
Started Jun 11 12:39:11 PM PDT 24
Finished Jun 11 12:39:14 PM PDT 24
Peak memory 215052 kb
Host smart-89e0dc6b-4e73-4025-aa70-db46a329e31d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800122010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.2800122010
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3219454904
Short name T1066
Test name
Test status
Simulation time 35551642 ps
CPU time 2.39 seconds
Started Jun 11 12:39:00 PM PDT 24
Finished Jun 11 12:39:03 PM PDT 24
Peak memory 215380 kb
Host smart-121ce120-ecd3-4893-ad60-a11e4d35fba9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219454904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.3
219454904
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1168897845
Short name T106
Test name
Test status
Simulation time 212344461 ps
CPU time 6.91 seconds
Started Jun 11 12:39:06 PM PDT 24
Finished Jun 11 12:39:13 PM PDT 24
Peak memory 215128 kb
Host smart-aedbd3ef-4b00-4eff-9a89-fec550ae9a89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168897845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.1168897845
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2925643268
Short name T1015
Test name
Test status
Simulation time 3874465112 ps
CPU time 8.05 seconds
Started Jun 11 12:39:10 PM PDT 24
Finished Jun 11 12:39:18 PM PDT 24
Peak memory 215020 kb
Host smart-6ff1eb85-5caf-4a3e-90d9-041976ba9038
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925643268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.2925643268
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2116509554
Short name T113
Test name
Test status
Simulation time 722293270 ps
CPU time 21.16 seconds
Started Jun 11 12:39:09 PM PDT 24
Finished Jun 11 12:39:31 PM PDT 24
Peak memory 206772 kb
Host smart-1a9de400-b087-433f-9bca-7127a0b35808
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116509554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.2116509554
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.4217093659
Short name T1051
Test name
Test status
Simulation time 33785798 ps
CPU time 1.23 seconds
Started Jun 11 12:39:12 PM PDT 24
Finished Jun 11 12:39:14 PM PDT 24
Peak memory 216372 kb
Host smart-565f0b3e-ccdd-458f-980f-2af0c530f9db
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217093659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.4217093659
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3489149546
Short name T991
Test name
Test status
Simulation time 245053785 ps
CPU time 1.6 seconds
Started Jun 11 12:39:09 PM PDT 24
Finished Jun 11 12:39:11 PM PDT 24
Peak memory 216156 kb
Host smart-99bd473f-feed-45a4-89aa-69b3b1fde0b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489149546 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.3489149546
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.184726833
Short name T992
Test name
Test status
Simulation time 79817871 ps
CPU time 0.68 seconds
Started Jun 11 12:39:11 PM PDT 24
Finished Jun 11 12:39:12 PM PDT 24
Peak memory 203392 kb
Host smart-6ec13328-939d-48bf-a8d7-342399a53003
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184726833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.184726833
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.1018188866
Short name T1058
Test name
Test status
Simulation time 134329319 ps
CPU time 1.35 seconds
Started Jun 11 12:39:12 PM PDT 24
Finished Jun 11 12:39:14 PM PDT 24
Peak memory 215072 kb
Host smart-59d0b8c9-ba19-4b06-b3a9-31b93b09841b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018188866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.1018188866
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3007876095
Short name T971
Test name
Test status
Simulation time 15949857 ps
CPU time 0.63 seconds
Started Jun 11 12:39:11 PM PDT 24
Finished Jun 11 12:39:12 PM PDT 24
Peak memory 203296 kb
Host smart-296a817d-a05e-48b0-86bf-64d0d239e931
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007876095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.3007876095
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1837203744
Short name T1005
Test name
Test status
Simulation time 72538526 ps
CPU time 1.83 seconds
Started Jun 11 12:39:11 PM PDT 24
Finished Jun 11 12:39:14 PM PDT 24
Peak memory 215172 kb
Host smart-21b6018d-61f9-45e5-8c35-440f0bc5f5ff
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837203744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.1837203744
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.525148262
Short name T1073
Test name
Test status
Simulation time 69377707 ps
CPU time 1.75 seconds
Started Jun 11 12:39:13 PM PDT 24
Finished Jun 11 12:39:16 PM PDT 24
Peak memory 215192 kb
Host smart-386d3290-6eda-494b-9fad-cb16de8e2424
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525148262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.525148262
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3120147374
Short name T142
Test name
Test status
Simulation time 5115921648 ps
CPU time 23.94 seconds
Started Jun 11 12:39:19 PM PDT 24
Finished Jun 11 12:39:44 PM PDT 24
Peak memory 215348 kb
Host smart-c85fd301-2ead-4488-8163-24eb5b268415
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120147374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.3120147374
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3422486472
Short name T1078
Test name
Test status
Simulation time 214947477 ps
CPU time 1.62 seconds
Started Jun 11 12:39:47 PM PDT 24
Finished Jun 11 12:39:50 PM PDT 24
Peak memory 215200 kb
Host smart-89f41473-d8f0-4bd0-991d-5aa2254b541a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422486472 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.3422486472
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.524632737
Short name T1019
Test name
Test status
Simulation time 153649191 ps
CPU time 2.73 seconds
Started Jun 11 12:39:40 PM PDT 24
Finished Jun 11 12:39:45 PM PDT 24
Peak memory 215120 kb
Host smart-3a3e4b2c-198d-40a6-a633-e3214a58fb23
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524632737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.524632737
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2467704809
Short name T1027
Test name
Test status
Simulation time 15284669 ps
CPU time 0.75 seconds
Started Jun 11 12:39:41 PM PDT 24
Finished Jun 11 12:39:44 PM PDT 24
Peak memory 203492 kb
Host smart-69f169ff-1327-42e7-a732-2395dad2397c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467704809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
2467704809
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.50185857
Short name T128
Test name
Test status
Simulation time 372113073 ps
CPU time 4.21 seconds
Started Jun 11 12:39:51 PM PDT 24
Finished Jun 11 12:39:56 PM PDT 24
Peak memory 215136 kb
Host smart-731bcf0f-9346-43bf-992b-a8dd3719c550
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50185857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sp
i_device_same_csr_outstanding.50185857
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2502322323
Short name T1002
Test name
Test status
Simulation time 44405953 ps
CPU time 2.82 seconds
Started Jun 11 12:39:44 PM PDT 24
Finished Jun 11 12:39:48 PM PDT 24
Peak memory 216156 kb
Host smart-911827b0-bc0f-4e71-9ad7-cc5132997829
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502322323 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.2502322323
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3563918731
Short name T107
Test name
Test status
Simulation time 53691754 ps
CPU time 1.75 seconds
Started Jun 11 12:39:42 PM PDT 24
Finished Jun 11 12:39:46 PM PDT 24
Peak memory 215128 kb
Host smart-52ea2075-783d-4d30-b6a5-231cec0e2d90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563918731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
3563918731
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1753377760
Short name T1014
Test name
Test status
Simulation time 18789667 ps
CPU time 0.79 seconds
Started Jun 11 12:39:49 PM PDT 24
Finished Jun 11 12:39:51 PM PDT 24
Peak memory 203776 kb
Host smart-8cde2c13-9e9c-4174-bc67-0b630c25e71d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1753377760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1753377760
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1895757986
Short name T1069
Test name
Test status
Simulation time 48906816 ps
CPU time 2.84 seconds
Started Jun 11 12:39:40 PM PDT 24
Finished Jun 11 12:39:44 PM PDT 24
Peak memory 215060 kb
Host smart-565c5bd4-d153-4f9d-9c98-837e7aeca156
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895757986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.1895757986
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.4020483984
Short name T95
Test name
Test status
Simulation time 167934341 ps
CPU time 3.21 seconds
Started Jun 11 12:39:40 PM PDT 24
Finished Jun 11 12:39:46 PM PDT 24
Peak memory 215412 kb
Host smart-6a68271c-6b97-4a5d-b29d-b7b5e177681a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020483984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
4020483984
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.4051202377
Short name T143
Test name
Test status
Simulation time 1418174894 ps
CPU time 7.41 seconds
Started Jun 11 12:39:39 PM PDT 24
Finished Jun 11 12:39:47 PM PDT 24
Peak memory 215144 kb
Host smart-5b883f32-f2aa-4b50-bdb7-39429becbcd2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051202377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.4051202377
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3432081047
Short name T104
Test name
Test status
Simulation time 44594128 ps
CPU time 2.9 seconds
Started Jun 11 12:39:40 PM PDT 24
Finished Jun 11 12:39:44 PM PDT 24
Peak memory 216320 kb
Host smart-6288d286-2249-4430-a0d5-49b70bb05254
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432081047 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3432081047
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.3273142676
Short name T120
Test name
Test status
Simulation time 216212192 ps
CPU time 2.61 seconds
Started Jun 11 12:39:39 PM PDT 24
Finished Jun 11 12:39:43 PM PDT 24
Peak memory 215096 kb
Host smart-2460b8fe-a2f1-4434-9d83-ce342794d3b1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273142676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
3273142676
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2226725232
Short name T973
Test name
Test status
Simulation time 14040067 ps
CPU time 0.67 seconds
Started Jun 11 12:39:41 PM PDT 24
Finished Jun 11 12:39:45 PM PDT 24
Peak memory 203792 kb
Host smart-2ff356ea-f518-440d-9e61-9cbd82923c8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226725232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
2226725232
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1553602752
Short name T1006
Test name
Test status
Simulation time 116366802 ps
CPU time 3.19 seconds
Started Jun 11 12:39:48 PM PDT 24
Finished Jun 11 12:39:53 PM PDT 24
Peak memory 215200 kb
Host smart-54291e86-8d25-4791-b0a3-9a492f919230
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553602752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.1553602752
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.329382620
Short name T61
Test name
Test status
Simulation time 73744964 ps
CPU time 2.09 seconds
Started Jun 11 12:39:42 PM PDT 24
Finished Jun 11 12:39:46 PM PDT 24
Peak memory 216108 kb
Host smart-eb7c4258-64fb-4ac8-b9ec-994296ca74dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329382620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.329382620
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2013706557
Short name T88
Test name
Test status
Simulation time 430070365 ps
CPU time 11.93 seconds
Started Jun 11 12:39:42 PM PDT 24
Finished Jun 11 12:39:56 PM PDT 24
Peak memory 215168 kb
Host smart-627c101c-d4df-4823-aa52-f56bf1d81027
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013706557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.2013706557
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.4111536499
Short name T996
Test name
Test status
Simulation time 311166739 ps
CPU time 2.62 seconds
Started Jun 11 12:39:48 PM PDT 24
Finished Jun 11 12:39:52 PM PDT 24
Peak memory 218168 kb
Host smart-e1bfcf63-14cf-4f42-a264-a9d7c0bad682
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111536499 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.4111536499
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3060490219
Short name T1067
Test name
Test status
Simulation time 118936258 ps
CPU time 2.6 seconds
Started Jun 11 12:39:41 PM PDT 24
Finished Jun 11 12:39:46 PM PDT 24
Peak memory 215040 kb
Host smart-76268d83-05ac-4c31-bf78-c72b81df10c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060490219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
3060490219
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3906983363
Short name T1000
Test name
Test status
Simulation time 13492821 ps
CPU time 0.73 seconds
Started Jun 11 12:39:40 PM PDT 24
Finished Jun 11 12:39:41 PM PDT 24
Peak memory 203492 kb
Host smart-f917f3ed-5334-4fc0-9152-f7fc9987a274
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906983363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3906983363
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2550538884
Short name T130
Test name
Test status
Simulation time 108979506 ps
CPU time 2.72 seconds
Started Jun 11 12:39:41 PM PDT 24
Finished Jun 11 12:39:46 PM PDT 24
Peak memory 215132 kb
Host smart-7577e3fe-12e3-4b2b-b0f6-6b0b76af9085
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550538884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.2550538884
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.1181560915
Short name T97
Test name
Test status
Simulation time 59259932 ps
CPU time 3.56 seconds
Started Jun 11 12:39:40 PM PDT 24
Finished Jun 11 12:39:44 PM PDT 24
Peak memory 215164 kb
Host smart-915fb295-e7e6-49c9-9a31-fad5c67c718b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181560915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
1181560915
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1608685901
Short name T141
Test name
Test status
Simulation time 2522083973 ps
CPU time 14.57 seconds
Started Jun 11 12:39:40 PM PDT 24
Finished Jun 11 12:39:56 PM PDT 24
Peak memory 215244 kb
Host smart-3a34a608-a96a-4d03-ad51-f187b0054a0b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608685901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.1608685901
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2097050826
Short name T990
Test name
Test status
Simulation time 167362265 ps
CPU time 2.31 seconds
Started Jun 11 12:39:43 PM PDT 24
Finished Jun 11 12:39:47 PM PDT 24
Peak memory 215232 kb
Host smart-b738ab81-bc5f-41fe-9797-927755650ce7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097050826 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2097050826
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3861021582
Short name T1072
Test name
Test status
Simulation time 66314391 ps
CPU time 2.26 seconds
Started Jun 11 12:39:39 PM PDT 24
Finished Jun 11 12:39:41 PM PDT 24
Peak memory 215088 kb
Host smart-7350eddc-1294-47e1-878f-642a47a49cf7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861021582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
3861021582
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2562285818
Short name T966
Test name
Test status
Simulation time 13608662 ps
CPU time 0.72 seconds
Started Jun 11 12:39:47 PM PDT 24
Finished Jun 11 12:39:49 PM PDT 24
Peak memory 203504 kb
Host smart-b0789ccb-153c-447a-83e6-76671eb56fa3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562285818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2562285818
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.938528656
Short name T1032
Test name
Test status
Simulation time 262535155 ps
CPU time 1.93 seconds
Started Jun 11 12:39:42 PM PDT 24
Finished Jun 11 12:39:46 PM PDT 24
Peak memory 215232 kb
Host smart-2df17a1c-141c-472a-9663-5e7048449527
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938528656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.938528656
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.3182849089
Short name T63
Test name
Test status
Simulation time 243896933 ps
CPU time 2.45 seconds
Started Jun 11 12:39:49 PM PDT 24
Finished Jun 11 12:39:53 PM PDT 24
Peak memory 215200 kb
Host smart-76ccda60-36b8-4ade-a518-1860fb5d9fed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182849089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
3182849089
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3497324805
Short name T986
Test name
Test status
Simulation time 179337409 ps
CPU time 2.82 seconds
Started Jun 11 12:39:42 PM PDT 24
Finished Jun 11 12:39:47 PM PDT 24
Peak memory 216768 kb
Host smart-3761ea23-367a-49c1-86c9-112a2e550c37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497324805 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.3497324805
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.539370582
Short name T119
Test name
Test status
Simulation time 79501115 ps
CPU time 2.26 seconds
Started Jun 11 12:39:47 PM PDT 24
Finished Jun 11 12:39:50 PM PDT 24
Peak memory 214984 kb
Host smart-bd331a4c-09b4-4b74-978d-0f6ab8fff16e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539370582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.539370582
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2847845955
Short name T982
Test name
Test status
Simulation time 40543958 ps
CPU time 0.72 seconds
Started Jun 11 12:39:40 PM PDT 24
Finished Jun 11 12:39:43 PM PDT 24
Peak memory 203852 kb
Host smart-f79b3073-d977-43ea-b547-2e83597af034
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847845955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
2847845955
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2041499778
Short name T1017
Test name
Test status
Simulation time 585559045 ps
CPU time 3.82 seconds
Started Jun 11 12:39:41 PM PDT 24
Finished Jun 11 12:39:46 PM PDT 24
Peak memory 215140 kb
Host smart-fe04786f-2766-4fe4-9a53-b737badc9d8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041499778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.2041499778
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1559839319
Short name T1039
Test name
Test status
Simulation time 548276516 ps
CPU time 15.25 seconds
Started Jun 11 12:39:41 PM PDT 24
Finished Jun 11 12:39:58 PM PDT 24
Peak memory 216364 kb
Host smart-84e9e6e6-8737-440a-89fa-21a2b2a3e0fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559839319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1559839319
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3628783230
Short name T105
Test name
Test status
Simulation time 608771398 ps
CPU time 3.82 seconds
Started Jun 11 12:39:44 PM PDT 24
Finished Jun 11 12:39:50 PM PDT 24
Peak memory 218396 kb
Host smart-5244365f-ac4b-4e83-97fd-f4e8b0047b1d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628783230 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3628783230
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2791649824
Short name T1035
Test name
Test status
Simulation time 127302947 ps
CPU time 1.91 seconds
Started Jun 11 12:39:40 PM PDT 24
Finished Jun 11 12:39:44 PM PDT 24
Peak memory 215096 kb
Host smart-f9bb6cb6-a0b7-454c-80bd-162bbe3c7bf3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791649824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
2791649824
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.23296625
Short name T1031
Test name
Test status
Simulation time 32415396 ps
CPU time 0.71 seconds
Started Jun 11 12:39:41 PM PDT 24
Finished Jun 11 12:39:43 PM PDT 24
Peak memory 203476 kb
Host smart-740e7629-a081-4ef4-ab3a-a7c79c59cfe9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23296625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.23296625
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.203117248
Short name T1025
Test name
Test status
Simulation time 172100119 ps
CPU time 3.01 seconds
Started Jun 11 12:39:43 PM PDT 24
Finished Jun 11 12:39:48 PM PDT 24
Peak memory 215028 kb
Host smart-b577cfcf-4ece-45c3-8331-82d31c453b4a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203117248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.s
pi_device_same_csr_outstanding.203117248
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.4073222168
Short name T1065
Test name
Test status
Simulation time 569027444 ps
CPU time 3.91 seconds
Started Jun 11 12:39:41 PM PDT 24
Finished Jun 11 12:39:48 PM PDT 24
Peak memory 215280 kb
Host smart-248193de-67ab-4dc1-a4d0-f0fc4f41cecb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073222168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
4073222168
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.2677120862
Short name T1013
Test name
Test status
Simulation time 2591650671 ps
CPU time 15.26 seconds
Started Jun 11 12:39:41 PM PDT 24
Finished Jun 11 12:39:59 PM PDT 24
Peak memory 223312 kb
Host smart-1f51bbd1-2143-4c5d-893a-d64cbcc9b51e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677120862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.2677120862
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3113475236
Short name T62
Test name
Test status
Simulation time 274204676 ps
CPU time 3.65 seconds
Started Jun 11 12:39:46 PM PDT 24
Finished Jun 11 12:39:51 PM PDT 24
Peak memory 216984 kb
Host smart-7a2670ba-4382-4479-93ac-f9aaf0dd035d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113475236 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.3113475236
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.393127333
Short name T109
Test name
Test status
Simulation time 145940520 ps
CPU time 2.64 seconds
Started Jun 11 12:39:41 PM PDT 24
Finished Jun 11 12:39:46 PM PDT 24
Peak memory 206792 kb
Host smart-3239319d-c02c-437b-be5f-579a91e55147
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393127333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.393127333
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3496273801
Short name T1070
Test name
Test status
Simulation time 20335358 ps
CPU time 0.83 seconds
Started Jun 11 12:39:41 PM PDT 24
Finished Jun 11 12:39:44 PM PDT 24
Peak memory 203512 kb
Host smart-c8bc26fa-e20c-419f-914b-8da2610b1a1e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496273801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
3496273801
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.4246216190
Short name T1028
Test name
Test status
Simulation time 43030251 ps
CPU time 2.45 seconds
Started Jun 11 12:39:40 PM PDT 24
Finished Jun 11 12:39:44 PM PDT 24
Peak memory 215156 kb
Host smart-4ddeb55a-267f-4f7d-aa76-a55aa3087559
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246216190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.4246216190
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1108272936
Short name T1010
Test name
Test status
Simulation time 48205215 ps
CPU time 2.92 seconds
Started Jun 11 12:39:43 PM PDT 24
Finished Jun 11 12:39:48 PM PDT 24
Peak memory 215400 kb
Host smart-a7f2f6a5-4fc1-4a41-a18b-0de4f3ce62f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1108272936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
1108272936
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.411234948
Short name T999
Test name
Test status
Simulation time 95152473 ps
CPU time 1.86 seconds
Started Jun 11 12:39:44 PM PDT 24
Finished Jun 11 12:39:48 PM PDT 24
Peak memory 215572 kb
Host smart-50d7b492-b629-4dc5-b4f1-6afc243391f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411234948 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.411234948
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.281707966
Short name T1041
Test name
Test status
Simulation time 107785589 ps
CPU time 1.8 seconds
Started Jun 11 12:39:42 PM PDT 24
Finished Jun 11 12:39:46 PM PDT 24
Peak memory 206804 kb
Host smart-126c1dd3-2f88-4cfa-a346-7988cbbeab37
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281707966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.281707966
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2234995389
Short name T1026
Test name
Test status
Simulation time 19074907 ps
CPU time 0.73 seconds
Started Jun 11 12:39:42 PM PDT 24
Finished Jun 11 12:39:45 PM PDT 24
Peak memory 203540 kb
Host smart-c9643132-ca56-4821-904e-74a86f2a5034
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234995389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
2234995389
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.479195899
Short name T1004
Test name
Test status
Simulation time 105284087 ps
CPU time 1.8 seconds
Started Jun 11 12:39:48 PM PDT 24
Finished Jun 11 12:39:51 PM PDT 24
Peak memory 215092 kb
Host smart-ad6a1875-2544-452e-beb3-0fe50325615d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479195899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.s
pi_device_same_csr_outstanding.479195899
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1973557017
Short name T1053
Test name
Test status
Simulation time 219369381 ps
CPU time 3.1 seconds
Started Jun 11 12:39:44 PM PDT 24
Finished Jun 11 12:39:49 PM PDT 24
Peak memory 215368 kb
Host smart-ea59a595-7da0-4151-9e73-de3ae3a2df03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973557017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1973557017
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.4188802685
Short name T1030
Test name
Test status
Simulation time 108834652 ps
CPU time 6.51 seconds
Started Jun 11 12:39:42 PM PDT 24
Finished Jun 11 12:39:51 PM PDT 24
Peak memory 215644 kb
Host smart-37f1324a-69ce-47b6-88e3-a763ae700248
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188802685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.4188802685
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.709100479
Short name T977
Test name
Test status
Simulation time 149830928 ps
CPU time 3.14 seconds
Started Jun 11 12:39:49 PM PDT 24
Finished Jun 11 12:39:53 PM PDT 24
Peak memory 216852 kb
Host smart-c23709d0-1128-4147-b6e7-7b16f791f65b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709100479 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.709100479
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3076640264
Short name T1003
Test name
Test status
Simulation time 85465872 ps
CPU time 2.37 seconds
Started Jun 11 12:39:43 PM PDT 24
Finished Jun 11 12:39:48 PM PDT 24
Peak memory 206860 kb
Host smart-a4fd9bcb-3d9c-4ae7-883a-4b3052244362
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076640264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
3076640264
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1444340515
Short name T1043
Test name
Test status
Simulation time 12590194 ps
CPU time 0.68 seconds
Started Jun 11 12:39:40 PM PDT 24
Finished Jun 11 12:39:42 PM PDT 24
Peak memory 203496 kb
Host smart-dfc36689-da02-42b5-9359-9b133e58c04f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444340515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1444340515
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3749595482
Short name T1044
Test name
Test status
Simulation time 113627890 ps
CPU time 1.73 seconds
Started Jun 11 12:39:48 PM PDT 24
Finished Jun 11 12:39:51 PM PDT 24
Peak memory 215640 kb
Host smart-5950c7de-13e5-483c-bfc3-992a4f3e03c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749595482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.3749595482
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2459819795
Short name T252
Test name
Test status
Simulation time 462251155 ps
CPU time 7.64 seconds
Started Jun 11 12:39:45 PM PDT 24
Finished Jun 11 12:39:55 PM PDT 24
Peak memory 221880 kb
Host smart-fa462681-195a-4b9b-95f2-5717e07f683e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459819795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.2459819795
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.4017372407
Short name T114
Test name
Test status
Simulation time 5885037728 ps
CPU time 19.61 seconds
Started Jun 11 12:39:07 PM PDT 24
Finished Jun 11 12:39:27 PM PDT 24
Peak memory 206924 kb
Host smart-dfc519c6-a7cf-459a-b851-11f8e4bed538
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017372407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.4017372407
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.1648792766
Short name T1034
Test name
Test status
Simulation time 357378645 ps
CPU time 22.46 seconds
Started Jun 11 12:39:18 PM PDT 24
Finished Jun 11 12:39:42 PM PDT 24
Peak memory 206948 kb
Host smart-50f0c1a0-5d97-42a2-af07-b022ec779ce0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648792766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.1648792766
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.911427
Short name T81
Test name
Test status
Simulation time 79226728 ps
CPU time 1.32 seconds
Started Jun 11 12:39:10 PM PDT 24
Finished Jun 11 12:39:12 PM PDT 24
Peak memory 206656 kb
Host smart-c17616d9-6ae8-4227-b903-b659e9081b0b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_hw
_reset.911427
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.767234200
Short name T1023
Test name
Test status
Simulation time 488764562 ps
CPU time 3.58 seconds
Started Jun 11 12:39:19 PM PDT 24
Finished Jun 11 12:39:23 PM PDT 24
Peak memory 216848 kb
Host smart-93eb667d-50cb-43e6-afa6-14b7618362ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767234200 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.767234200
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2568885425
Short name T115
Test name
Test status
Simulation time 103382091 ps
CPU time 1.9 seconds
Started Jun 11 12:39:08 PM PDT 24
Finished Jun 11 12:39:11 PM PDT 24
Peak memory 206876 kb
Host smart-6f0a29a7-0ffe-4624-b315-b8a8ab2ed278
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568885425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2
568885425
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1752485900
Short name T961
Test name
Test status
Simulation time 41401983 ps
CPU time 0.7 seconds
Started Jun 11 12:39:08 PM PDT 24
Finished Jun 11 12:39:09 PM PDT 24
Peak memory 203512 kb
Host smart-a337fdf1-9eb5-4b52-95a8-50878b1c6d04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752485900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1
752485900
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2830457098
Short name T112
Test name
Test status
Simulation time 51728001 ps
CPU time 1.28 seconds
Started Jun 11 12:39:13 PM PDT 24
Finished Jun 11 12:39:15 PM PDT 24
Peak memory 215068 kb
Host smart-2489f86b-2adc-410a-9aa1-3078fb906f74
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830457098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.2830457098
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.582120269
Short name T1029
Test name
Test status
Simulation time 13276917 ps
CPU time 0.7 seconds
Started Jun 11 12:39:09 PM PDT 24
Finished Jun 11 12:39:10 PM PDT 24
Peak memory 203404 kb
Host smart-ae27682f-0cfe-42c2-b604-69791f812539
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582120269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem
_walk.582120269
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1423243790
Short name T1057
Test name
Test status
Simulation time 142054845 ps
CPU time 1.83 seconds
Started Jun 11 12:39:19 PM PDT 24
Finished Jun 11 12:39:22 PM PDT 24
Peak memory 206852 kb
Host smart-96feb364-f487-41bd-b785-87df209e1f48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423243790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1423243790
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.585029672
Short name T96
Test name
Test status
Simulation time 186180960 ps
CPU time 3.06 seconds
Started Jun 11 12:39:12 PM PDT 24
Finished Jun 11 12:39:16 PM PDT 24
Peak memory 215252 kb
Host smart-7bd19e6a-375c-4fa8-8241-4daf040dfd0c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585029672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.585029672
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1779695415
Short name T984
Test name
Test status
Simulation time 1177065988 ps
CPU time 7.08 seconds
Started Jun 11 12:39:11 PM PDT 24
Finished Jun 11 12:39:19 PM PDT 24
Peak memory 215712 kb
Host smart-9f774450-292f-4a40-bce2-a9426b6b8b0f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779695415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1779695415
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.661341463
Short name T1064
Test name
Test status
Simulation time 18906913 ps
CPU time 0.73 seconds
Started Jun 11 12:39:46 PM PDT 24
Finished Jun 11 12:39:49 PM PDT 24
Peak memory 203468 kb
Host smart-7301599f-423e-4877-996d-0a21487c38b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661341463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.661341463
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2979500296
Short name T970
Test name
Test status
Simulation time 16601985 ps
CPU time 0.72 seconds
Started Jun 11 12:39:46 PM PDT 24
Finished Jun 11 12:39:48 PM PDT 24
Peak memory 203508 kb
Host smart-44003f1a-b9ed-44b5-8c48-43f67f132d8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979500296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
2979500296
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2888915737
Short name T1036
Test name
Test status
Simulation time 16352904 ps
CPU time 0.73 seconds
Started Jun 11 12:39:42 PM PDT 24
Finished Jun 11 12:39:45 PM PDT 24
Peak memory 203500 kb
Host smart-2d49ba83-35f9-43e8-90ba-6fd43eda49b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888915737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
2888915737
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.3662574549
Short name T963
Test name
Test status
Simulation time 16995013 ps
CPU time 0.73 seconds
Started Jun 11 12:39:52 PM PDT 24
Finished Jun 11 12:39:54 PM PDT 24
Peak memory 203504 kb
Host smart-052fb23d-bf89-43cb-8c3f-7e8473230a61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662574549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
3662574549
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1675836629
Short name T983
Test name
Test status
Simulation time 34065590 ps
CPU time 0.77 seconds
Started Jun 11 12:39:53 PM PDT 24
Finished Jun 11 12:39:56 PM PDT 24
Peak memory 203820 kb
Host smart-8bb6ae58-242e-44b6-8ae9-f1e489d06306
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675836629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1675836629
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3410039925
Short name T968
Test name
Test status
Simulation time 22441595 ps
CPU time 0.68 seconds
Started Jun 11 12:39:54 PM PDT 24
Finished Jun 11 12:39:56 PM PDT 24
Peak memory 203708 kb
Host smart-f283bbac-c7f6-4e45-93de-d43f2ec0ee1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410039925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
3410039925
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2977006985
Short name T979
Test name
Test status
Simulation time 82195199 ps
CPU time 0.68 seconds
Started Jun 11 12:39:57 PM PDT 24
Finished Jun 11 12:40:00 PM PDT 24
Peak memory 203492 kb
Host smart-94d056b1-ff6d-4343-bd18-1cda18b844c4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977006985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2977006985
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.319994240
Short name T958
Test name
Test status
Simulation time 62292900 ps
CPU time 0.69 seconds
Started Jun 11 12:39:56 PM PDT 24
Finished Jun 11 12:39:59 PM PDT 24
Peak memory 203452 kb
Host smart-01508583-d8ec-4f50-9a0c-8762a06b56bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319994240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.319994240
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.767943259
Short name T962
Test name
Test status
Simulation time 17588267 ps
CPU time 0.83 seconds
Started Jun 11 12:39:52 PM PDT 24
Finished Jun 11 12:39:54 PM PDT 24
Peak memory 203460 kb
Host smart-9a8a8019-72c7-4434-a7ff-064eee375aaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767943259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.767943259
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1840418945
Short name T976
Test name
Test status
Simulation time 42009002 ps
CPU time 0.74 seconds
Started Jun 11 12:39:55 PM PDT 24
Finished Jun 11 12:39:57 PM PDT 24
Peak memory 203488 kb
Host smart-fb981d8d-2b30-4901-86b2-d0e0ff97d37a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840418945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
1840418945
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2960897865
Short name T116
Test name
Test status
Simulation time 1192492066 ps
CPU time 22.77 seconds
Started Jun 11 12:39:26 PM PDT 24
Finished Jun 11 12:39:50 PM PDT 24
Peak memory 215116 kb
Host smart-68187586-6ccf-415f-8301-d0ca999dab20
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960897865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.2960897865
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3914086651
Short name T1037
Test name
Test status
Simulation time 4818137354 ps
CPU time 24.28 seconds
Started Jun 11 12:39:19 PM PDT 24
Finished Jun 11 12:39:44 PM PDT 24
Peak memory 206932 kb
Host smart-45c8dcb0-2dcf-4a49-bc53-81c36a9db3a0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914086651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3914086651
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.332007469
Short name T79
Test name
Test status
Simulation time 381123441 ps
CPU time 1.33 seconds
Started Jun 11 12:39:12 PM PDT 24
Finished Jun 11 12:39:14 PM PDT 24
Peak memory 206860 kb
Host smart-df54b236-ba31-4c3f-9848-d2f706ec672f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332007469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_hw_reset.332007469
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2902079499
Short name T1007
Test name
Test status
Simulation time 228301951 ps
CPU time 2.12 seconds
Started Jun 11 12:39:25 PM PDT 24
Finished Jun 11 12:39:28 PM PDT 24
Peak memory 215192 kb
Host smart-f74c0c7e-8f8b-45cb-939f-0eceb735e2a3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902079499 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2902079499
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2714988690
Short name T132
Test name
Test status
Simulation time 1388851344 ps
CPU time 2.36 seconds
Started Jun 11 12:39:06 PM PDT 24
Finished Jun 11 12:39:09 PM PDT 24
Peak memory 215036 kb
Host smart-7ed8222b-c4d7-4596-885c-13d616997fb9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714988690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2
714988690
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2260057333
Short name T1060
Test name
Test status
Simulation time 12091482 ps
CPU time 0.7 seconds
Started Jun 11 12:39:10 PM PDT 24
Finished Jun 11 12:39:11 PM PDT 24
Peak memory 203712 kb
Host smart-d03caeb4-7981-4396-8a02-928419fb57bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260057333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2
260057333
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2884691782
Short name T110
Test name
Test status
Simulation time 129132066 ps
CPU time 1.23 seconds
Started Jun 11 12:39:19 PM PDT 24
Finished Jun 11 12:39:22 PM PDT 24
Peak memory 215080 kb
Host smart-8f70e0f4-95c8-49a2-89ab-ede505884710
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884691782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.2884691782
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3393280153
Short name T1048
Test name
Test status
Simulation time 11114025 ps
CPU time 0.65 seconds
Started Jun 11 12:39:19 PM PDT 24
Finished Jun 11 12:39:20 PM PDT 24
Peak memory 203428 kb
Host smart-7810bd26-5dfe-417b-8d09-4086a124cb01
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393280153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.3393280153
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1379939389
Short name T1020
Test name
Test status
Simulation time 76448425 ps
CPU time 2.56 seconds
Started Jun 11 12:39:22 PM PDT 24
Finished Jun 11 12:39:26 PM PDT 24
Peak memory 215192 kb
Host smart-6209d0b5-eab4-46fc-a525-651e0364d658
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379939389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.1379939389
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.105283785
Short name T1049
Test name
Test status
Simulation time 109015262 ps
CPU time 3.57 seconds
Started Jun 11 12:39:11 PM PDT 24
Finished Jun 11 12:39:15 PM PDT 24
Peak memory 216240 kb
Host smart-aa4a2739-f5fc-4307-8052-500174737a5b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105283785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.105283785
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.3765337239
Short name T1071
Test name
Test status
Simulation time 208547383 ps
CPU time 12.6 seconds
Started Jun 11 12:39:19 PM PDT 24
Finished Jun 11 12:39:33 PM PDT 24
Peak memory 215140 kb
Host smart-b10a7ec3-3773-4a4b-8a0c-eed2734debcb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765337239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.3765337239
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3778690142
Short name T997
Test name
Test status
Simulation time 20640996 ps
CPU time 0.72 seconds
Started Jun 11 12:39:55 PM PDT 24
Finished Jun 11 12:39:58 PM PDT 24
Peak memory 203784 kb
Host smart-5b05a367-b71e-4bfb-b77a-d98451577163
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778690142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
3778690142
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.408233145
Short name T988
Test name
Test status
Simulation time 70248368 ps
CPU time 0.7 seconds
Started Jun 11 12:39:53 PM PDT 24
Finished Jun 11 12:39:55 PM PDT 24
Peak memory 203816 kb
Host smart-935a799d-c0df-4212-8800-a950f75b484d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408233145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.408233145
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1316430983
Short name T1076
Test name
Test status
Simulation time 18334676 ps
CPU time 0.74 seconds
Started Jun 11 12:39:54 PM PDT 24
Finished Jun 11 12:39:57 PM PDT 24
Peak memory 203524 kb
Host smart-ec3bab24-0386-4c8e-bcda-c5bfee118d82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316430983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
1316430983
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2363045309
Short name T1063
Test name
Test status
Simulation time 39544558 ps
CPU time 0.71 seconds
Started Jun 11 12:39:54 PM PDT 24
Finished Jun 11 12:39:56 PM PDT 24
Peak memory 203524 kb
Host smart-40804efd-6b62-492b-a42c-c012a6c8aaca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363045309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
2363045309
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.4274565849
Short name T1052
Test name
Test status
Simulation time 17235146 ps
CPU time 0.78 seconds
Started Jun 11 12:39:52 PM PDT 24
Finished Jun 11 12:39:54 PM PDT 24
Peak memory 203500 kb
Host smart-06cbb675-2a1a-4880-8520-02106cc626b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274565849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
4274565849
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1552167003
Short name T965
Test name
Test status
Simulation time 17755542 ps
CPU time 0.74 seconds
Started Jun 11 12:39:56 PM PDT 24
Finished Jun 11 12:39:58 PM PDT 24
Peak memory 203792 kb
Host smart-1bb43348-687f-4812-a766-0aac47730a1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552167003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
1552167003
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1238560698
Short name T960
Test name
Test status
Simulation time 16042447 ps
CPU time 0.77 seconds
Started Jun 11 12:39:52 PM PDT 24
Finished Jun 11 12:39:54 PM PDT 24
Peak memory 203540 kb
Host smart-9f5f5c28-8b06-4916-b828-629974c39717
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238560698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
1238560698
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.452739374
Short name T959
Test name
Test status
Simulation time 24158282 ps
CPU time 0.73 seconds
Started Jun 11 12:39:53 PM PDT 24
Finished Jun 11 12:39:55 PM PDT 24
Peak memory 203504 kb
Host smart-bebaf168-7043-460a-9103-43f515a57c72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452739374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.452739374
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2748225574
Short name T972
Test name
Test status
Simulation time 64449462 ps
CPU time 0.8 seconds
Started Jun 11 12:39:58 PM PDT 24
Finished Jun 11 12:40:00 PM PDT 24
Peak memory 203556 kb
Host smart-553e4940-e028-4bb2-babf-206c9d4fae74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748225574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
2748225574
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3951182466
Short name T1024
Test name
Test status
Simulation time 12738549 ps
CPU time 0.68 seconds
Started Jun 11 12:39:49 PM PDT 24
Finished Jun 11 12:39:51 PM PDT 24
Peak memory 203804 kb
Host smart-c4362f53-fa8d-4744-a8e7-0f1d9f43f8bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3951182466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
3951182466
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.318679689
Short name T1011
Test name
Test status
Simulation time 2470048597 ps
CPU time 23.92 seconds
Started Jun 11 12:39:24 PM PDT 24
Finished Jun 11 12:39:49 PM PDT 24
Peak memory 215104 kb
Host smart-6e3b8d98-035d-4c0b-a862-2c2b510f001d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318679689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_aliasing.318679689
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.10213073
Short name T1033
Test name
Test status
Simulation time 183321319 ps
CPU time 11.78 seconds
Started Jun 11 12:39:22 PM PDT 24
Finished Jun 11 12:39:35 PM PDT 24
Peak memory 206952 kb
Host smart-787e035a-1517-409a-a746-d93582afd7aa
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10213073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_
bit_bash.10213073
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1796647372
Short name T1081
Test name
Test status
Simulation time 38195317 ps
CPU time 1.34 seconds
Started Jun 11 12:39:22 PM PDT 24
Finished Jun 11 12:39:24 PM PDT 24
Peak memory 206828 kb
Host smart-820dc19f-3907-4a46-b1c7-9a40e4e6d66c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796647372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.1796647372
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.582127900
Short name T985
Test name
Test status
Simulation time 50146460 ps
CPU time 1.66 seconds
Started Jun 11 12:39:17 PM PDT 24
Finished Jun 11 12:39:20 PM PDT 24
Peak memory 216240 kb
Host smart-7f651f8d-bc87-47f8-b51b-91e0ba1a383e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582127900 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.582127900
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2560652574
Short name T1018
Test name
Test status
Simulation time 251722101 ps
CPU time 1.75 seconds
Started Jun 11 12:39:25 PM PDT 24
Finished Jun 11 12:39:28 PM PDT 24
Peak memory 215084 kb
Host smart-00d706c5-7ddd-42a2-b378-5bcc66e2a25c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560652574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2
560652574
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2135810725
Short name T1045
Test name
Test status
Simulation time 35099536 ps
CPU time 0.86 seconds
Started Jun 11 12:39:25 PM PDT 24
Finished Jun 11 12:39:26 PM PDT 24
Peak memory 203736 kb
Host smart-a76b6392-c7fa-44c6-88bf-2c7d2d8bbc43
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135810725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.2
135810725
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3876626194
Short name T1012
Test name
Test status
Simulation time 98509925 ps
CPU time 1.26 seconds
Started Jun 11 12:39:24 PM PDT 24
Finished Jun 11 12:39:26 PM PDT 24
Peak memory 215044 kb
Host smart-a36fd10b-1f75-40de-8b9f-2cb8e3edfbe4
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876626194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.3876626194
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.2181996343
Short name T1021
Test name
Test status
Simulation time 41458035 ps
CPU time 0.65 seconds
Started Jun 11 12:39:24 PM PDT 24
Finished Jun 11 12:39:25 PM PDT 24
Peak memory 203364 kb
Host smart-912ca848-79f4-45ab-a2b8-fdf6847fdfbe
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181996343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.2181996343
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3077277802
Short name T1040
Test name
Test status
Simulation time 112421781 ps
CPU time 2.93 seconds
Started Jun 11 12:39:20 PM PDT 24
Finished Jun 11 12:39:24 PM PDT 24
Peak memory 215024 kb
Host smart-6dc0b28d-5060-4264-b069-fb44237ee477
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077277802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.3077277802
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2032980985
Short name T101
Test name
Test status
Simulation time 30567207 ps
CPU time 1.97 seconds
Started Jun 11 12:39:21 PM PDT 24
Finished Jun 11 12:39:24 PM PDT 24
Peak memory 215216 kb
Host smart-24361102-f2ed-4b86-8ade-f5336c841b06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032980985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
032980985
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1651007880
Short name T1001
Test name
Test status
Simulation time 24450319 ps
CPU time 0.75 seconds
Started Jun 11 12:39:53 PM PDT 24
Finished Jun 11 12:39:56 PM PDT 24
Peak memory 203532 kb
Host smart-624a3863-186f-4213-ac61-40ae5e1a8482
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651007880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
1651007880
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.1700601182
Short name T964
Test name
Test status
Simulation time 11711269 ps
CPU time 0.82 seconds
Started Jun 11 12:39:52 PM PDT 24
Finished Jun 11 12:39:54 PM PDT 24
Peak memory 203736 kb
Host smart-90a7fb2f-1d53-438e-b644-661019ae3d91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700601182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
1700601182
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.306141263
Short name T978
Test name
Test status
Simulation time 40743622 ps
CPU time 0.72 seconds
Started Jun 11 12:39:56 PM PDT 24
Finished Jun 11 12:39:59 PM PDT 24
Peak memory 203464 kb
Host smart-a8b10fd9-7090-4f34-89ce-4b24dbb33524
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306141263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.306141263
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1894879016
Short name T1046
Test name
Test status
Simulation time 13332247 ps
CPU time 0.78 seconds
Started Jun 11 12:39:51 PM PDT 24
Finished Jun 11 12:39:53 PM PDT 24
Peak memory 203536 kb
Host smart-43baf90b-d274-422c-b819-c0fd9cc62028
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894879016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
1894879016
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.299665831
Short name T1042
Test name
Test status
Simulation time 11940640 ps
CPU time 0.7 seconds
Started Jun 11 12:39:51 PM PDT 24
Finished Jun 11 12:39:53 PM PDT 24
Peak memory 203512 kb
Host smart-b2be9aed-ddcf-417e-84a3-a54efede064f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299665831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.299665831
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.644293459
Short name T967
Test name
Test status
Simulation time 19867254 ps
CPU time 0.78 seconds
Started Jun 11 12:39:52 PM PDT 24
Finished Jun 11 12:39:54 PM PDT 24
Peak memory 203480 kb
Host smart-1c039085-6633-4d90-8dee-cb3536d265ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644293459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.644293459
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2084472669
Short name T981
Test name
Test status
Simulation time 85065541 ps
CPU time 0.73 seconds
Started Jun 11 12:39:54 PM PDT 24
Finished Jun 11 12:39:56 PM PDT 24
Peak memory 203820 kb
Host smart-04d0a026-4518-474e-aec4-2e181c4ad7bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084472669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
2084472669
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.813312285
Short name T993
Test name
Test status
Simulation time 49665416 ps
CPU time 0.71 seconds
Started Jun 11 12:39:54 PM PDT 24
Finished Jun 11 12:39:56 PM PDT 24
Peak memory 203452 kb
Host smart-cba9b87c-6f30-496d-af9c-f8ea77437d03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=813312285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.813312285
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.1562279614
Short name T974
Test name
Test status
Simulation time 32007621 ps
CPU time 0.69 seconds
Started Jun 11 12:39:52 PM PDT 24
Finished Jun 11 12:39:54 PM PDT 24
Peak memory 203820 kb
Host smart-8967d980-fafa-49b2-88bf-8b7802e756b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562279614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
1562279614
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3817004441
Short name T1008
Test name
Test status
Simulation time 28477543 ps
CPU time 0.7 seconds
Started Jun 11 12:39:55 PM PDT 24
Finished Jun 11 12:39:57 PM PDT 24
Peak memory 203372 kb
Host smart-3ce13dcc-1f14-4162-8ce9-5039f22fe7b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817004441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
3817004441
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3068183274
Short name T987
Test name
Test status
Simulation time 86932553 ps
CPU time 2.6 seconds
Started Jun 11 12:39:34 PM PDT 24
Finished Jun 11 12:39:37 PM PDT 24
Peak memory 216208 kb
Host smart-4c406b87-5a1e-4a32-b519-afa9cc4ae6de
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068183274 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.3068183274
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.1013001422
Short name T1047
Test name
Test status
Simulation time 227579619 ps
CPU time 2.16 seconds
Started Jun 11 12:39:29 PM PDT 24
Finished Jun 11 12:39:32 PM PDT 24
Peak memory 215068 kb
Host smart-b7567166-3ef2-4d5c-a17d-45a59c89a58a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013001422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.1
013001422
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.863471371
Short name T1062
Test name
Test status
Simulation time 13488746 ps
CPU time 0.77 seconds
Started Jun 11 12:39:27 PM PDT 24
Finished Jun 11 12:39:29 PM PDT 24
Peak memory 203760 kb
Host smart-9424a94f-64a9-4cab-ab6e-3779082cee81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863471371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.863471371
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.4216641702
Short name T994
Test name
Test status
Simulation time 240681787 ps
CPU time 2.65 seconds
Started Jun 11 12:39:28 PM PDT 24
Finished Jun 11 12:39:32 PM PDT 24
Peak memory 215108 kb
Host smart-d16cafaf-d0ae-4309-bd18-faf8b329ec86
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216641702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.4216641702
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.186710700
Short name T247
Test name
Test status
Simulation time 80893911 ps
CPU time 5.47 seconds
Started Jun 11 12:39:24 PM PDT 24
Finished Jun 11 12:39:31 PM PDT 24
Peak memory 216152 kb
Host smart-2d5a8552-c51b-4eba-97bf-0174e99107b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186710700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.186710700
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1268296617
Short name T250
Test name
Test status
Simulation time 325343309 ps
CPU time 7.55 seconds
Started Jun 11 12:39:45 PM PDT 24
Finished Jun 11 12:39:54 PM PDT 24
Peak memory 215176 kb
Host smart-e98e2893-d940-4c0d-9e49-11d5042096d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268296617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1268296617
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1989065780
Short name T1068
Test name
Test status
Simulation time 131277504 ps
CPU time 3.36 seconds
Started Jun 11 12:39:29 PM PDT 24
Finished Jun 11 12:39:33 PM PDT 24
Peak memory 218284 kb
Host smart-8b39fffc-e0d0-48cf-8cfb-27f5f51e3153
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989065780 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.1989065780
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.1312572807
Short name T111
Test name
Test status
Simulation time 21203173 ps
CPU time 1.17 seconds
Started Jun 11 12:39:29 PM PDT 24
Finished Jun 11 12:39:31 PM PDT 24
Peak memory 206816 kb
Host smart-b997d3f7-20d4-49c6-bb29-6f850dce840f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312572807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.1
312572807
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.4216654176
Short name T1016
Test name
Test status
Simulation time 45422653 ps
CPU time 0.69 seconds
Started Jun 11 12:39:31 PM PDT 24
Finished Jun 11 12:39:32 PM PDT 24
Peak memory 203500 kb
Host smart-41446e61-8279-4758-98cd-91a8d70be8bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216654176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.4
216654176
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2433993789
Short name T129
Test name
Test status
Simulation time 318097560 ps
CPU time 4.24 seconds
Started Jun 11 12:39:45 PM PDT 24
Finished Jun 11 12:39:51 PM PDT 24
Peak memory 214980 kb
Host smart-e7d16b8f-388e-4b96-bde2-71feaef03606
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433993789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.2433993789
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2208417249
Short name T94
Test name
Test status
Simulation time 71091588 ps
CPU time 4.64 seconds
Started Jun 11 12:39:32 PM PDT 24
Finished Jun 11 12:39:38 PM PDT 24
Peak memory 215328 kb
Host smart-b1dcedc7-93dc-4f81-aa42-8e62b631480a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208417249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
208417249
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1813617994
Short name T102
Test name
Test status
Simulation time 306865396 ps
CPU time 19.39 seconds
Started Jun 11 12:39:45 PM PDT 24
Finished Jun 11 12:40:06 PM PDT 24
Peak memory 215000 kb
Host smart-3ed3e321-6505-4b79-be8b-056f6b753b70
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813617994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1813617994
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2929975173
Short name T1022
Test name
Test status
Simulation time 69189873 ps
CPU time 2.09 seconds
Started Jun 11 12:39:45 PM PDT 24
Finished Jun 11 12:39:49 PM PDT 24
Peak memory 216076 kb
Host smart-ea7ded6d-2e48-4f70-893b-45001dc76b31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929975173 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.2929975173
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.2597408841
Short name T1061
Test name
Test status
Simulation time 144107301 ps
CPU time 1.31 seconds
Started Jun 11 12:39:29 PM PDT 24
Finished Jun 11 12:39:31 PM PDT 24
Peak memory 206788 kb
Host smart-da7e51b4-a162-4f2b-b4c0-9e4e2dee47e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597408841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2
597408841
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.1983851759
Short name T969
Test name
Test status
Simulation time 175270208 ps
CPU time 0.69 seconds
Started Jun 11 12:39:31 PM PDT 24
Finished Jun 11 12:39:33 PM PDT 24
Peak memory 203804 kb
Host smart-eb708d33-6ac2-4dc9-952b-22b719e751df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983851759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1
983851759
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1744676292
Short name T131
Test name
Test status
Simulation time 313978983 ps
CPU time 2.13 seconds
Started Jun 11 12:39:45 PM PDT 24
Finished Jun 11 12:39:49 PM PDT 24
Peak memory 215140 kb
Host smart-ddd792c5-d636-4405-a454-6dfe770079a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744676292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1744676292
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.4005599509
Short name T995
Test name
Test status
Simulation time 155306701 ps
CPU time 3.84 seconds
Started Jun 11 12:39:32 PM PDT 24
Finished Jun 11 12:39:37 PM PDT 24
Peak memory 215272 kb
Host smart-5fdd2f36-bcea-4024-83e4-1486c28957a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005599509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.4
005599509
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.1099095533
Short name T1050
Test name
Test status
Simulation time 1464842507 ps
CPU time 8.67 seconds
Started Jun 11 12:39:44 PM PDT 24
Finished Jun 11 12:39:55 PM PDT 24
Peak memory 215120 kb
Host smart-a3607e6c-157a-4cb7-808a-fd818e538542
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099095533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.1099095533
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1165334542
Short name T1059
Test name
Test status
Simulation time 189805178 ps
CPU time 1.73 seconds
Started Jun 11 12:39:31 PM PDT 24
Finished Jun 11 12:39:34 PM PDT 24
Peak memory 215224 kb
Host smart-64a82774-02eb-4c9d-accd-25b701bfe8c5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165334542 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.1165334542
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.4012247383
Short name T118
Test name
Test status
Simulation time 234801967 ps
CPU time 1.85 seconds
Started Jun 11 12:39:44 PM PDT 24
Finished Jun 11 12:39:47 PM PDT 24
Peak memory 206756 kb
Host smart-850de199-0480-42d7-9f48-db59ebadb8fe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012247383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.4
012247383
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.1409284440
Short name T975
Test name
Test status
Simulation time 22908862 ps
CPU time 0.73 seconds
Started Jun 11 12:39:29 PM PDT 24
Finished Jun 11 12:39:30 PM PDT 24
Peak memory 203380 kb
Host smart-6a7b75fd-410d-4008-a000-d297c9fa472d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409284440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.1
409284440
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.4212467361
Short name T1055
Test name
Test status
Simulation time 151005610 ps
CPU time 3.99 seconds
Started Jun 11 12:39:45 PM PDT 24
Finished Jun 11 12:39:51 PM PDT 24
Peak memory 215000 kb
Host smart-0ac96fe2-c30c-46fc-86dc-db3f043f7d35
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212467361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.4212467361
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.4196788362
Short name T99
Test name
Test status
Simulation time 174674266 ps
CPU time 3.57 seconds
Started Jun 11 12:39:29 PM PDT 24
Finished Jun 11 12:39:33 PM PDT 24
Peak memory 215248 kb
Host smart-92dbfac0-dc43-4da8-821e-cd591fd658fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196788362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.4
196788362
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2151788794
Short name T89
Test name
Test status
Simulation time 599307085 ps
CPU time 18.56 seconds
Started Jun 11 12:39:32 PM PDT 24
Finished Jun 11 12:39:51 PM PDT 24
Peak memory 215276 kb
Host smart-9bf4dc79-72c8-4019-9348-5f5080fb987f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151788794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.2151788794
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1527208124
Short name T1079
Test name
Test status
Simulation time 78029573 ps
CPU time 2.73 seconds
Started Jun 11 12:39:28 PM PDT 24
Finished Jun 11 12:39:32 PM PDT 24
Peak memory 216856 kb
Host smart-64960235-80cd-4eec-99eb-0a53e6dc1d86
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527208124 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1527208124
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3309441152
Short name T117
Test name
Test status
Simulation time 143652070 ps
CPU time 1.24 seconds
Started Jun 11 12:39:29 PM PDT 24
Finished Jun 11 12:39:31 PM PDT 24
Peak memory 206688 kb
Host smart-16287b52-f5e0-46c2-8673-9212db115cf8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309441152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3
309441152
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1888365682
Short name T998
Test name
Test status
Simulation time 19609495 ps
CPU time 0.73 seconds
Started Jun 11 12:39:27 PM PDT 24
Finished Jun 11 12:39:29 PM PDT 24
Peak memory 203428 kb
Host smart-508b9f2f-3974-4a6b-9aeb-1649d6627b4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888365682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.1
888365682
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.780111761
Short name T1056
Test name
Test status
Simulation time 109088255 ps
CPU time 1.62 seconds
Started Jun 11 12:39:29 PM PDT 24
Finished Jun 11 12:39:32 PM PDT 24
Peak memory 206936 kb
Host smart-ac002f5c-afb5-47fa-a9d2-e20f502a063a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=780111761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sp
i_device_same_csr_outstanding.780111761
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3616921023
Short name T103
Test name
Test status
Simulation time 131779785 ps
CPU time 4 seconds
Started Jun 11 12:39:45 PM PDT 24
Finished Jun 11 12:39:51 PM PDT 24
Peak memory 215104 kb
Host smart-59e177f3-e9e1-488a-bad8-086ea7d0aafc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616921023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.3
616921023
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.689812882
Short name T989
Test name
Test status
Simulation time 548287851 ps
CPU time 13.37 seconds
Started Jun 11 12:39:27 PM PDT 24
Finished Jun 11 12:39:42 PM PDT 24
Peak memory 215200 kb
Host smart-9c6348c0-48c5-48cb-94d6-f0a476797142
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689812882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_
tl_intg_err.689812882
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.1499761188
Short name T741
Test name
Test status
Simulation time 23777514 ps
CPU time 0.71 seconds
Started Jun 11 12:45:31 PM PDT 24
Finished Jun 11 12:45:34 PM PDT 24
Peak memory 205672 kb
Host smart-8e236863-7742-49e8-9c80-07579ea61996
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499761188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.1
499761188
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.2669878508
Short name T862
Test name
Test status
Simulation time 443687278 ps
CPU time 2.29 seconds
Started Jun 11 12:45:35 PM PDT 24
Finished Jun 11 12:45:40 PM PDT 24
Peak memory 224788 kb
Host smart-2880882f-f080-4fa0-8c84-6e374cdc78e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669878508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.2669878508
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.4240645584
Short name T440
Test name
Test status
Simulation time 19849041 ps
CPU time 0.78 seconds
Started Jun 11 12:45:20 PM PDT 24
Finished Jun 11 12:45:24 PM PDT 24
Peak memory 206856 kb
Host smart-a6df5b21-168b-4861-91fa-1aaf351c46e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240645584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.4240645584
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.1738714177
Short name T700
Test name
Test status
Simulation time 5321619329 ps
CPU time 73.04 seconds
Started Jun 11 12:45:27 PM PDT 24
Finished Jun 11 12:46:41 PM PDT 24
Peak memory 251292 kb
Host smart-f17adfc1-bda4-41cc-a290-1cd94bf3d8ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738714177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.1738714177
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.81334344
Short name T49
Test name
Test status
Simulation time 5494049989 ps
CPU time 40.16 seconds
Started Jun 11 12:45:34 PM PDT 24
Finished Jun 11 12:46:18 PM PDT 24
Peak memory 241340 kb
Host smart-1ed4f6fd-257c-41e0-bee5-a1aa4ee450ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81334344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.81334344
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.3361292508
Short name T940
Test name
Test status
Simulation time 6935523493 ps
CPU time 36.26 seconds
Started Jun 11 12:45:30 PM PDT 24
Finished Jun 11 12:46:08 PM PDT 24
Peak memory 221272 kb
Host smart-bede8a99-d3af-4333-b67e-f0033aa6d1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361292508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.3361292508
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.1344591877
Short name T640
Test name
Test status
Simulation time 111917131 ps
CPU time 3.21 seconds
Started Jun 11 12:45:29 PM PDT 24
Finished Jun 11 12:45:34 PM PDT 24
Peak memory 224644 kb
Host smart-87c781df-43d7-491e-9515-79e870d745e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344591877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1344591877
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.4257418978
Short name T694
Test name
Test status
Simulation time 57144953 ps
CPU time 1.97 seconds
Started Jun 11 12:45:05 PM PDT 24
Finished Jun 11 12:45:09 PM PDT 24
Peak memory 218720 kb
Host smart-ceef9322-24c9-439a-9597-f89a17415fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257418978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.4257418978
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.3377294605
Short name T197
Test name
Test status
Simulation time 3145258093 ps
CPU time 5.93 seconds
Started Jun 11 12:45:24 PM PDT 24
Finished Jun 11 12:45:33 PM PDT 24
Peak memory 241288 kb
Host smart-302c60ac-7be4-40d3-85f1-494b50e08492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377294605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3377294605
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.1185187682
Short name T227
Test name
Test status
Simulation time 2942384542 ps
CPU time 11.21 seconds
Started Jun 11 12:45:35 PM PDT 24
Finished Jun 11 12:45:49 PM PDT 24
Peak memory 233100 kb
Host smart-689b5cad-dac0-4310-940b-75b22306485d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1185187682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.1185187682
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3929817312
Short name T205
Test name
Test status
Simulation time 2162587268 ps
CPU time 8.31 seconds
Started Jun 11 12:45:14 PM PDT 24
Finished Jun 11 12:45:25 PM PDT 24
Peak memory 233116 kb
Host smart-8f12d7b7-65f6-4024-a589-0f7ab7cb520e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929817312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3929817312
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2486733959
Short name T393
Test name
Test status
Simulation time 157682694 ps
CPU time 3.46 seconds
Started Jun 11 12:45:35 PM PDT 24
Finished Jun 11 12:45:42 PM PDT 24
Peak memory 222840 kb
Host smart-0a961a1e-9cbf-4fa4-b61f-53e25972f1da
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2486733959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2486733959
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.3091327909
Short name T65
Test name
Test status
Simulation time 31533404 ps
CPU time 0.93 seconds
Started Jun 11 12:45:26 PM PDT 24
Finished Jun 11 12:45:29 PM PDT 24
Peak memory 235672 kb
Host smart-63ab1583-e5e8-4982-bcc4-760967c282c3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091327909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.3091327909
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.2023852997
Short name T787
Test name
Test status
Simulation time 3465204097 ps
CPU time 66.76 seconds
Started Jun 11 12:45:29 PM PDT 24
Finished Jun 11 12:46:38 PM PDT 24
Peak memory 255284 kb
Host smart-2b819034-b1cd-4c6e-a3e3-644ef07bd796
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023852997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.2023852997
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.3348887315
Short name T377
Test name
Test status
Simulation time 3181332979 ps
CPU time 7.3 seconds
Started Jun 11 12:45:13 PM PDT 24
Finished Jun 11 12:45:23 PM PDT 24
Peak memory 216792 kb
Host smart-765c24fb-6676-48ee-bd94-e618735a5a1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348887315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.3348887315
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3402663086
Short name T947
Test name
Test status
Simulation time 843814478 ps
CPU time 5.01 seconds
Started Jun 11 12:45:11 PM PDT 24
Finished Jun 11 12:45:18 PM PDT 24
Peak memory 216512 kb
Host smart-fd1af4af-a894-4a4c-ad0e-274f1080bec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402663086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3402663086
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2743859037
Short name T878
Test name
Test status
Simulation time 62924793 ps
CPU time 1.29 seconds
Started Jun 11 12:45:15 PM PDT 24
Finished Jun 11 12:45:19 PM PDT 24
Peak memory 208380 kb
Host smart-aa74e3d5-4ce0-459a-be5e-18c620ab2b5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743859037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2743859037
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.2933605832
Short name T560
Test name
Test status
Simulation time 416373535 ps
CPU time 1 seconds
Started Jun 11 12:45:09 PM PDT 24
Finished Jun 11 12:45:13 PM PDT 24
Peak memory 206364 kb
Host smart-dee68751-c870-4e7d-959a-de48efa2716b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933605832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2933605832
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.2130989290
Short name T795
Test name
Test status
Simulation time 183660295 ps
CPU time 2.06 seconds
Started Jun 11 12:45:25 PM PDT 24
Finished Jun 11 12:45:29 PM PDT 24
Peak memory 224732 kb
Host smart-4ca8df09-3bd4-4e9b-a65d-69623a40c05e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2130989290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.2130989290
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.2942088081
Short name T668
Test name
Test status
Simulation time 61158079 ps
CPU time 0.72 seconds
Started Jun 11 12:45:34 PM PDT 24
Finished Jun 11 12:45:38 PM PDT 24
Peak memory 205616 kb
Host smart-7a34ce9e-0786-4cf7-9078-551851c8576a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942088081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.2
942088081
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.324415106
Short name T752
Test name
Test status
Simulation time 34301076 ps
CPU time 2.56 seconds
Started Jun 11 12:45:30 PM PDT 24
Finished Jun 11 12:45:34 PM PDT 24
Peak memory 232968 kb
Host smart-d71d8cea-cecf-41f5-aeeb-b68c068ab498
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324415106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.324415106
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.338934158
Short name T473
Test name
Test status
Simulation time 13265370 ps
CPU time 0.76 seconds
Started Jun 11 12:45:36 PM PDT 24
Finished Jun 11 12:45:41 PM PDT 24
Peak memory 206028 kb
Host smart-da783c9b-389f-4d8a-97e9-94a3d92ce694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338934158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.338934158
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.2334409703
Short name T956
Test name
Test status
Simulation time 3027509460 ps
CPU time 21.85 seconds
Started Jun 11 12:45:33 PM PDT 24
Finished Jun 11 12:45:57 PM PDT 24
Peak memory 233044 kb
Host smart-c9d7c349-2b57-4078-a771-999db3eee1f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334409703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.2334409703
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.244759318
Short name T683
Test name
Test status
Simulation time 132319322 ps
CPU time 0.81 seconds
Started Jun 11 12:45:24 PM PDT 24
Finished Jun 11 12:45:27 PM PDT 24
Peak memory 217660 kb
Host smart-76daaadb-09ed-48ea-bc69-ac056e486d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244759318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.
244759318
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3753376534
Short name T874
Test name
Test status
Simulation time 123817604 ps
CPU time 3.54 seconds
Started Jun 11 12:45:37 PM PDT 24
Finished Jun 11 12:45:44 PM PDT 24
Peak memory 233060 kb
Host smart-007e32ce-dc96-4684-8405-bfcb1f2d08c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753376534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3753376534
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.308972495
Short name T202
Test name
Test status
Simulation time 8340237232 ps
CPU time 6.08 seconds
Started Jun 11 12:45:22 PM PDT 24
Finished Jun 11 12:45:31 PM PDT 24
Peak memory 224876 kb
Host smart-457268ef-07f3-491c-881e-ccc26cab6b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=308972495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.308972495
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.682969704
Short name T386
Test name
Test status
Simulation time 3678317002 ps
CPU time 43.37 seconds
Started Jun 11 12:45:36 PM PDT 24
Finished Jun 11 12:46:33 PM PDT 24
Peak memory 233092 kb
Host smart-101e9a88-c7b2-4054-bf05-c82937d571a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682969704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.682969704
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.39100748
Short name T466
Test name
Test status
Simulation time 5277740256 ps
CPU time 6.61 seconds
Started Jun 11 12:45:31 PM PDT 24
Finished Jun 11 12:45:40 PM PDT 24
Peak memory 233040 kb
Host smart-e5f11e97-27f5-4e95-b2ef-b7aa88848026
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39100748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.39100748
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.2745057934
Short name T347
Test name
Test status
Simulation time 104572571 ps
CPU time 2.24 seconds
Started Jun 11 12:45:35 PM PDT 24
Finished Jun 11 12:45:40 PM PDT 24
Peak memory 223392 kb
Host smart-8f09820b-c8fc-48d7-9c1c-400ab43d8d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745057934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.2745057934
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.1349108901
Short name T887
Test name
Test status
Simulation time 3718647048 ps
CPU time 8.57 seconds
Started Jun 11 12:45:33 PM PDT 24
Finished Jun 11 12:45:44 PM PDT 24
Peak memory 223600 kb
Host smart-61dc023c-df05-49c6-ad30-bef630500dd2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1349108901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.1349108901
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.1515716218
Short name T55
Test name
Test status
Simulation time 53037340835 ps
CPU time 554.66 seconds
Started Jun 11 12:45:33 PM PDT 24
Finished Jun 11 12:54:50 PM PDT 24
Peak memory 265972 kb
Host smart-59adf5c3-c849-4314-82e1-27e9949804b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515716218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.1515716218
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.1726539395
Short name T511
Test name
Test status
Simulation time 59014429618 ps
CPU time 27.89 seconds
Started Jun 11 12:45:29 PM PDT 24
Finished Jun 11 12:45:59 PM PDT 24
Peak memory 216648 kb
Host smart-2534b4a3-49a7-4ee8-a46e-296daeac7767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726539395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.1726539395
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2128111773
Short name T924
Test name
Test status
Simulation time 5878908019 ps
CPU time 16.75 seconds
Started Jun 11 12:45:30 PM PDT 24
Finished Jun 11 12:45:49 PM PDT 24
Peak memory 216676 kb
Host smart-5a73d664-f422-4ad5-856f-0e13e1fb6f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128111773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.2128111773
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.1754523854
Short name T567
Test name
Test status
Simulation time 39615111 ps
CPU time 1.09 seconds
Started Jun 11 12:45:24 PM PDT 24
Finished Jun 11 12:45:27 PM PDT 24
Peak memory 208168 kb
Host smart-14b4fdeb-d831-4144-8808-62c0b0406aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754523854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1754523854
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.2472786068
Short name T388
Test name
Test status
Simulation time 40509287 ps
CPU time 0.72 seconds
Started Jun 11 12:45:24 PM PDT 24
Finished Jun 11 12:45:27 PM PDT 24
Peak memory 206156 kb
Host smart-88d91b4d-fc1d-4fcb-9756-c62dd71e8efd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472786068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2472786068
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.240565507
Short name T810
Test name
Test status
Simulation time 1150578199 ps
CPU time 3.29 seconds
Started Jun 11 12:45:29 PM PDT 24
Finished Jun 11 12:45:34 PM PDT 24
Peak memory 224824 kb
Host smart-c2cb2617-b208-4506-937a-c885b3c467bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240565507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.240565507
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.3680142833
Short name T453
Test name
Test status
Simulation time 10611706 ps
CPU time 0.73 seconds
Started Jun 11 12:45:39 PM PDT 24
Finished Jun 11 12:45:45 PM PDT 24
Peak memory 205180 kb
Host smart-842ae18a-d0e0-4fc7-b73c-4eb3ccb0968c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680142833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
3680142833
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.4100936801
Short name T84
Test name
Test status
Simulation time 181984659 ps
CPU time 2.55 seconds
Started Jun 11 12:45:47 PM PDT 24
Finished Jun 11 12:45:53 PM PDT 24
Peak memory 233016 kb
Host smart-7283f0db-842b-4d5a-a537-ccb0d602f538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100936801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.4100936801
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.3075660185
Short name T369
Test name
Test status
Simulation time 106148610 ps
CPU time 0.74 seconds
Started Jun 11 12:45:37 PM PDT 24
Finished Jun 11 12:45:42 PM PDT 24
Peak memory 207128 kb
Host smart-5fec002e-8837-4880-9461-fddafbde68a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075660185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3075660185
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.337361930
Short name T159
Test name
Test status
Simulation time 5961633683 ps
CPU time 26.92 seconds
Started Jun 11 12:45:41 PM PDT 24
Finished Jun 11 12:46:13 PM PDT 24
Peak memory 249472 kb
Host smart-9ec58453-68cc-464e-bc96-6b2762a626ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337361930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.337361930
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.957928606
Short name T608
Test name
Test status
Simulation time 973005146 ps
CPU time 4.79 seconds
Started Jun 11 12:45:48 PM PDT 24
Finished Jun 11 12:45:56 PM PDT 24
Peak memory 217696 kb
Host smart-2c343a5b-b175-4cc5-a1b0-40b65cdb4aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957928606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.957928606
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.1772288877
Short name T34
Test name
Test status
Simulation time 27464325464 ps
CPU time 263.32 seconds
Started Jun 11 12:45:41 PM PDT 24
Finished Jun 11 12:50:09 PM PDT 24
Peak memory 258360 kb
Host smart-7c977dd1-dada-42d9-816b-cf3b7a6e8d3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772288877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.1772288877
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3529716007
Short name T513
Test name
Test status
Simulation time 205643818 ps
CPU time 5.55 seconds
Started Jun 11 12:46:10 PM PDT 24
Finished Jun 11 12:46:18 PM PDT 24
Peak memory 232900 kb
Host smart-4c5d87f6-b1b9-4a0e-9cfc-a25bf026b261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3529716007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3529716007
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.1869858569
Short name T275
Test name
Test status
Simulation time 336075366 ps
CPU time 5.84 seconds
Started Jun 11 12:45:49 PM PDT 24
Finished Jun 11 12:45:58 PM PDT 24
Peak memory 233008 kb
Host smart-ce1b8896-ae9a-45f1-9075-215c4d22ec75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1869858569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1869858569
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.2214177023
Short name T954
Test name
Test status
Simulation time 1860337256 ps
CPU time 13.85 seconds
Started Jun 11 12:45:43 PM PDT 24
Finished Jun 11 12:46:01 PM PDT 24
Peak memory 233004 kb
Host smart-62b8e7ef-cd8c-49d3-90c2-8893bf2697b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2214177023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.2214177023
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.1734997959
Short name T329
Test name
Test status
Simulation time 625432433 ps
CPU time 2.66 seconds
Started Jun 11 12:46:01 PM PDT 24
Finished Jun 11 12:46:06 PM PDT 24
Peak memory 224660 kb
Host smart-e3d0142c-24d8-4853-aeff-916552c765bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1734997959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.1734997959
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.2573898391
Short name T450
Test name
Test status
Simulation time 111107544 ps
CPU time 3.75 seconds
Started Jun 11 12:45:56 PM PDT 24
Finished Jun 11 12:46:02 PM PDT 24
Peak memory 233004 kb
Host smart-0947cfaa-9de7-4a42-94d1-4a729e1e4975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2573898391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.2573898391
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.3954125059
Short name T461
Test name
Test status
Simulation time 845920028 ps
CPU time 8.56 seconds
Started Jun 11 12:46:02 PM PDT 24
Finished Jun 11 12:46:13 PM PDT 24
Peak memory 220204 kb
Host smart-d1d20e6c-b78f-41d1-9d04-82466bd26c53
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3954125059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.3954125059
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.3638371031
Short name T518
Test name
Test status
Simulation time 24935549369 ps
CPU time 73 seconds
Started Jun 11 12:45:41 PM PDT 24
Finished Jun 11 12:46:58 PM PDT 24
Peak memory 257188 kb
Host smart-f4e792e3-5455-4970-8d0b-52dec14ad1b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638371031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.3638371031
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.1787348139
Short name T469
Test name
Test status
Simulation time 9340190073 ps
CPU time 50.66 seconds
Started Jun 11 12:45:41 PM PDT 24
Finished Jun 11 12:46:36 PM PDT 24
Peak memory 216720 kb
Host smart-8e03bc59-7be8-4148-a30a-d70e8dfb1236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787348139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1787348139
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1351034264
Short name T743
Test name
Test status
Simulation time 2650805717 ps
CPU time 2.63 seconds
Started Jun 11 12:45:39 PM PDT 24
Finished Jun 11 12:45:46 PM PDT 24
Peak memory 207668 kb
Host smart-439d315e-11fd-4674-ab1d-caefd4dea416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351034264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1351034264
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.2758244853
Short name T762
Test name
Test status
Simulation time 64300404 ps
CPU time 1.74 seconds
Started Jun 11 12:45:53 PM PDT 24
Finished Jun 11 12:45:57 PM PDT 24
Peak memory 216604 kb
Host smart-98930fd0-fbe8-416c-88f4-72a33b42960b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758244853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2758244853
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.899862793
Short name T923
Test name
Test status
Simulation time 132568151 ps
CPU time 0.72 seconds
Started Jun 11 12:45:39 PM PDT 24
Finished Jun 11 12:45:44 PM PDT 24
Peak memory 206176 kb
Host smart-b7906290-b2e2-4270-9d5e-a55aaaed526a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899862793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.899862793
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.1067740832
Short name T442
Test name
Test status
Simulation time 1512904721 ps
CPU time 7.44 seconds
Started Jun 11 12:45:40 PM PDT 24
Finished Jun 11 12:45:52 PM PDT 24
Peak memory 239932 kb
Host smart-a96e93c4-80e6-48a2-ae29-9f45af4feec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067740832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.1067740832
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.4239255763
Short name T659
Test name
Test status
Simulation time 18701579 ps
CPU time 0.69 seconds
Started Jun 11 12:45:44 PM PDT 24
Finished Jun 11 12:45:49 PM PDT 24
Peak memory 205644 kb
Host smart-d30ddc36-45b8-4c99-b40b-fec1f599b0d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239255763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
4239255763
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.3516477607
Short name T353
Test name
Test status
Simulation time 461190551 ps
CPU time 6.09 seconds
Started Jun 11 12:46:00 PM PDT 24
Finished Jun 11 12:46:08 PM PDT 24
Peak memory 232844 kb
Host smart-ff737154-3aa1-4168-a082-4ac7c59f8f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516477607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3516477607
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.2580281676
Short name T70
Test name
Test status
Simulation time 67705170 ps
CPU time 0.76 seconds
Started Jun 11 12:45:50 PM PDT 24
Finished Jun 11 12:45:53 PM PDT 24
Peak memory 207180 kb
Host smart-1bcad830-5464-47b2-9650-813530cda7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580281676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.2580281676
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.2826713952
Short name T712
Test name
Test status
Simulation time 2089552023 ps
CPU time 43.51 seconds
Started Jun 11 12:46:00 PM PDT 24
Finished Jun 11 12:46:46 PM PDT 24
Peak memory 249204 kb
Host smart-2fbf3dae-36c7-4c16-a722-a284a2554d80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826713952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.2826713952
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.2990544002
Short name T429
Test name
Test status
Simulation time 2141070869 ps
CPU time 9.95 seconds
Started Jun 11 12:45:48 PM PDT 24
Finished Jun 11 12:46:01 PM PDT 24
Peak memory 217852 kb
Host smart-1a1d1cc6-eace-418b-85e6-cdab124f645e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990544002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2990544002
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.1238548160
Short name T297
Test name
Test status
Simulation time 24646856134 ps
CPU time 19.63 seconds
Started Jun 11 12:45:43 PM PDT 24
Finished Jun 11 12:46:07 PM PDT 24
Peak memory 241228 kb
Host smart-34793565-a44b-46ed-b23a-6e7454a0689b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238548160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1238548160
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.3903027714
Short name T937
Test name
Test status
Simulation time 1469592284 ps
CPU time 17.3 seconds
Started Jun 11 12:46:03 PM PDT 24
Finished Jun 11 12:46:22 PM PDT 24
Peak memory 224716 kb
Host smart-da4d162a-465d-4fbd-bd09-46dc2f8200b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903027714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3903027714
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.1803787983
Short name T917
Test name
Test status
Simulation time 93222107405 ps
CPU time 114.85 seconds
Started Jun 11 12:45:52 PM PDT 24
Finished Jun 11 12:47:49 PM PDT 24
Peak memory 252324 kb
Host smart-c2a4ee6d-00c4-4e54-b6ef-b2c7dc0265d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803787983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1803787983
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2464973725
Short name T590
Test name
Test status
Simulation time 10216343600 ps
CPU time 6.61 seconds
Started Jun 11 12:45:48 PM PDT 24
Finished Jun 11 12:46:07 PM PDT 24
Peak memory 224932 kb
Host smart-ca219954-eec4-498b-9da9-23fb9d679752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464973725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2464973725
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.3325507824
Short name T318
Test name
Test status
Simulation time 36575836 ps
CPU time 2.47 seconds
Started Jun 11 12:46:01 PM PDT 24
Finished Jun 11 12:46:06 PM PDT 24
Peak memory 232796 kb
Host smart-861c8f83-5c6c-48bf-a156-442eba80d513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325507824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3325507824
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.3126838704
Short name T475
Test name
Test status
Simulation time 2659882893 ps
CPU time 4.54 seconds
Started Jun 11 12:45:59 PM PDT 24
Finished Jun 11 12:46:06 PM PDT 24
Peak memory 223380 kb
Host smart-7c656802-2650-4441-b7f7-4c78872c32af
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3126838704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.3126838704
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.2740626775
Short name T558
Test name
Test status
Simulation time 67895883 ps
CPU time 0.9 seconds
Started Jun 11 12:46:06 PM PDT 24
Finished Jun 11 12:46:09 PM PDT 24
Peak memory 206908 kb
Host smart-45644da0-0adc-40f5-9732-501af6f01e7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2740626775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.2740626775
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.4011229948
Short name T559
Test name
Test status
Simulation time 6003329017 ps
CPU time 8.44 seconds
Started Jun 11 12:45:56 PM PDT 24
Finished Jun 11 12:46:06 PM PDT 24
Peak memory 216524 kb
Host smart-3fc136e6-6f34-4095-9930-d8303b782f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011229948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.4011229948
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2134514686
Short name T479
Test name
Test status
Simulation time 14223037953 ps
CPU time 10.79 seconds
Started Jun 11 12:45:53 PM PDT 24
Finished Jun 11 12:46:06 PM PDT 24
Peak memory 216676 kb
Host smart-dd46c453-de30-45c5-ae8b-e89896f0facf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134514686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2134514686
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.124699127
Short name T918
Test name
Test status
Simulation time 21471553 ps
CPU time 0.71 seconds
Started Jun 11 12:45:50 PM PDT 24
Finished Jun 11 12:45:53 PM PDT 24
Peak memory 206108 kb
Host smart-59b754ac-103b-43de-a58f-ed6be85825ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124699127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.124699127
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.2437028607
Short name T531
Test name
Test status
Simulation time 494213134 ps
CPU time 0.99 seconds
Started Jun 11 12:46:03 PM PDT 24
Finished Jun 11 12:46:05 PM PDT 24
Peak memory 207040 kb
Host smart-213297fd-3068-4107-9f23-8f2d6dc01cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437028607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.2437028607
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.1650204431
Short name T746
Test name
Test status
Simulation time 8988455147 ps
CPU time 8.35 seconds
Started Jun 11 12:45:41 PM PDT 24
Finished Jun 11 12:45:54 PM PDT 24
Peak memory 224908 kb
Host smart-518f4369-185d-4851-a03d-e70b5e868321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650204431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.1650204431
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2410947339
Short name T579
Test name
Test status
Simulation time 12971563 ps
CPU time 0.71 seconds
Started Jun 11 12:46:05 PM PDT 24
Finished Jun 11 12:46:08 PM PDT 24
Peak memory 205724 kb
Host smart-6315c8e5-493b-40e9-9bf9-d183f353402d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410947339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2410947339
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.2518337224
Short name T376
Test name
Test status
Simulation time 421970020 ps
CPU time 5.62 seconds
Started Jun 11 12:45:53 PM PDT 24
Finished Jun 11 12:46:01 PM PDT 24
Peak memory 224812 kb
Host smart-48798054-14e5-4075-ae3f-09ec425c01d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518337224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2518337224
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.1243189458
Short name T955
Test name
Test status
Simulation time 56502996 ps
CPU time 0.77 seconds
Started Jun 11 12:45:45 PM PDT 24
Finished Jun 11 12:45:50 PM PDT 24
Peak memory 206740 kb
Host smart-ed30725c-7ad0-448a-abfa-feaf98c31fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243189458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1243189458
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.1033016018
Short name T784
Test name
Test status
Simulation time 5192369597 ps
CPU time 18.73 seconds
Started Jun 11 12:45:57 PM PDT 24
Finished Jun 11 12:46:17 PM PDT 24
Peak memory 237552 kb
Host smart-4aa36e11-b795-4963-98be-ee1dcbbb46e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033016018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.1033016018
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.2711636264
Short name T262
Test name
Test status
Simulation time 25422468073 ps
CPU time 110.54 seconds
Started Jun 11 12:45:58 PM PDT 24
Finished Jun 11 12:47:50 PM PDT 24
Peak memory 249476 kb
Host smart-f5a91b98-c8bb-439b-8e0f-755d6604edc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711636264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.2711636264
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.1404484038
Short name T6
Test name
Test status
Simulation time 21528661119 ps
CPU time 62.26 seconds
Started Jun 11 12:45:48 PM PDT 24
Finished Jun 11 12:46:53 PM PDT 24
Peak memory 254968 kb
Host smart-8e05d194-c6b5-4d4d-adab-2f5832bc0716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404484038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.1404484038
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.2264539827
Short name T776
Test name
Test status
Simulation time 392749053 ps
CPU time 7.27 seconds
Started Jun 11 12:46:00 PM PDT 24
Finished Jun 11 12:46:10 PM PDT 24
Peak memory 224788 kb
Host smart-a30223f5-c71f-41b8-a83b-e3f9200db3fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264539827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.2264539827
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.356739413
Short name T198
Test name
Test status
Simulation time 787085208 ps
CPU time 9.73 seconds
Started Jun 11 12:45:48 PM PDT 24
Finished Jun 11 12:46:01 PM PDT 24
Peak memory 224676 kb
Host smart-87f6a98b-e90c-4c48-8f5b-5456475d3422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356739413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.356739413
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.1667952269
Short name T838
Test name
Test status
Simulation time 855133777 ps
CPU time 12.76 seconds
Started Jun 11 12:45:51 PM PDT 24
Finished Jun 11 12:46:06 PM PDT 24
Peak memory 232868 kb
Host smart-47f68bdf-b2bd-4120-bada-83e017b3a97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667952269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.1667952269
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.9377408
Short name T742
Test name
Test status
Simulation time 12623166965 ps
CPU time 19 seconds
Started Jun 11 12:45:44 PM PDT 24
Finished Jun 11 12:46:07 PM PDT 24
Peak memory 232992 kb
Host smart-53699afd-095e-4886-a58e-bdb824a1baf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9377408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap.9377408
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.3009658029
Short name T190
Test name
Test status
Simulation time 7862330261 ps
CPU time 15.34 seconds
Started Jun 11 12:45:44 PM PDT 24
Finished Jun 11 12:46:04 PM PDT 24
Peak memory 253644 kb
Host smart-112c5c87-0940-4bd6-9329-9debe8eb5860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009658029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.3009658029
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3211874327
Short name T136
Test name
Test status
Simulation time 79497279 ps
CPU time 3.49 seconds
Started Jun 11 12:45:59 PM PDT 24
Finished Jun 11 12:46:09 PM PDT 24
Peak memory 219552 kb
Host smart-f2b5c802-96d0-4680-ade7-edfad85c61ed
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3211874327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3211874327
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.608216518
Short name T797
Test name
Test status
Simulation time 2308581173 ps
CPU time 20.68 seconds
Started Jun 11 12:45:48 PM PDT 24
Finished Jun 11 12:46:12 PM PDT 24
Peak memory 216704 kb
Host smart-b07dfd58-f62e-4b97-82a8-6891eec59fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608216518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.608216518
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.1223544929
Short name T871
Test name
Test status
Simulation time 8220407829 ps
CPU time 13.04 seconds
Started Jun 11 12:45:56 PM PDT 24
Finished Jun 11 12:46:11 PM PDT 24
Peak memory 216508 kb
Host smart-26a48672-108f-4f8b-9ad4-908aed4b7f10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223544929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.1223544929
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.2419666263
Short name T487
Test name
Test status
Simulation time 142738850 ps
CPU time 2.05 seconds
Started Jun 11 12:46:02 PM PDT 24
Finished Jun 11 12:46:06 PM PDT 24
Peak memory 216556 kb
Host smart-2ac2f0cd-4057-4e84-bd9b-03ed6a3ec34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419666263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.2419666263
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.2226531986
Short name T384
Test name
Test status
Simulation time 30421463 ps
CPU time 0.84 seconds
Started Jun 11 12:45:54 PM PDT 24
Finished Jun 11 12:45:56 PM PDT 24
Peak memory 206188 kb
Host smart-99cd0c66-46d8-49f1-8f12-12e886af78d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226531986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2226531986
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.4089730973
Short name T813
Test name
Test status
Simulation time 148555710 ps
CPU time 2.19 seconds
Started Jun 11 12:45:59 PM PDT 24
Finished Jun 11 12:46:03 PM PDT 24
Peak memory 232896 kb
Host smart-831b1d95-2a4c-47d1-84a9-4fca9a714a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089730973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.4089730973
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.1086035536
Short name T436
Test name
Test status
Simulation time 35726126 ps
CPU time 0.72 seconds
Started Jun 11 12:45:59 PM PDT 24
Finished Jun 11 12:46:01 PM PDT 24
Peak memory 206064 kb
Host smart-e925c6ae-c04f-4468-94b7-ce7973465f4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086035536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
1086035536
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.1594260707
Short name T432
Test name
Test status
Simulation time 149426361 ps
CPU time 3.62 seconds
Started Jun 11 12:45:42 PM PDT 24
Finished Jun 11 12:45:50 PM PDT 24
Peak memory 232928 kb
Host smart-cfa8729d-bc04-4cba-a767-d605de338797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594260707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.1594260707
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.1082567687
Short name T403
Test name
Test status
Simulation time 17323604 ps
CPU time 0.73 seconds
Started Jun 11 12:45:41 PM PDT 24
Finished Jun 11 12:45:47 PM PDT 24
Peak memory 206092 kb
Host smart-1b886c4f-f711-4813-9345-7983543509bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082567687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.1082567687
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.3842315092
Short name T655
Test name
Test status
Simulation time 1443428086 ps
CPU time 13.2 seconds
Started Jun 11 12:46:14 PM PDT 24
Finished Jun 11 12:46:31 PM PDT 24
Peak memory 224768 kb
Host smart-ce92d334-4119-412c-842d-26c88eb6b8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842315092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.3842315092
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.2736595952
Short name T854
Test name
Test status
Simulation time 146166587490 ps
CPU time 158.12 seconds
Started Jun 11 12:45:40 PM PDT 24
Finished Jun 11 12:48:22 PM PDT 24
Peak memory 249428 kb
Host smart-1408224f-6a1f-4dd3-9fb9-0d5b6b8215b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736595952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.2736595952
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.1813435461
Short name T314
Test name
Test status
Simulation time 3047647364 ps
CPU time 21.79 seconds
Started Jun 11 12:46:07 PM PDT 24
Finished Jun 11 12:46:31 PM PDT 24
Peak memory 217912 kb
Host smart-02502a50-a4fa-4d56-b981-6bc5616bffd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813435461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.1813435461
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.2866502851
Short name T126
Test name
Test status
Simulation time 3408751538 ps
CPU time 11.22 seconds
Started Jun 11 12:45:44 PM PDT 24
Finished Jun 11 12:45:59 PM PDT 24
Peak memory 249404 kb
Host smart-e0a4e1e2-40c8-4f24-87af-d06420c99480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866502851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.2866502851
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.954040265
Short name T195
Test name
Test status
Simulation time 305864225 ps
CPU time 4.74 seconds
Started Jun 11 12:45:42 PM PDT 24
Finished Jun 11 12:45:52 PM PDT 24
Peak memory 232588 kb
Host smart-2e06c818-08f6-48cd-a2cb-47081698be4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954040265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.954040265
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.505123413
Short name T707
Test name
Test status
Simulation time 150671979 ps
CPU time 2.54 seconds
Started Jun 11 12:45:39 PM PDT 24
Finished Jun 11 12:45:46 PM PDT 24
Peak memory 224660 kb
Host smart-25f36bae-a6bd-4d20-b507-692b4a48f69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505123413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.505123413
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1414733608
Short name T257
Test name
Test status
Simulation time 1738406641 ps
CPU time 8.99 seconds
Started Jun 11 12:45:39 PM PDT 24
Finished Jun 11 12:45:53 PM PDT 24
Peak memory 232956 kb
Host smart-c1cdd90d-fbf2-4f81-8110-a4900a18f3d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414733608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.1414733608
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.356433891
Short name T124
Test name
Test status
Simulation time 309488862 ps
CPU time 3.87 seconds
Started Jun 11 12:46:04 PM PDT 24
Finished Jun 11 12:46:09 PM PDT 24
Peak memory 224688 kb
Host smart-7ff6aff6-cebb-431b-87f9-d0d84c30319f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356433891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.356433891
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.3041657084
Short name T626
Test name
Test status
Simulation time 1833480091 ps
CPU time 7.99 seconds
Started Jun 11 12:45:52 PM PDT 24
Finished Jun 11 12:46:02 PM PDT 24
Peak memory 223252 kb
Host smart-851ce17f-14ca-4eba-a712-04fa0e621423
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3041657084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.3041657084
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.2618433673
Short name T508
Test name
Test status
Simulation time 563484660 ps
CPU time 1 seconds
Started Jun 11 12:46:02 PM PDT 24
Finished Jun 11 12:46:05 PM PDT 24
Peak memory 207860 kb
Host smart-0a7e8b6a-f77b-4d6b-8228-00859d909ff8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618433673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.2618433673
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.3688503155
Short name T534
Test name
Test status
Simulation time 3623367449 ps
CPU time 24.01 seconds
Started Jun 11 12:45:38 PM PDT 24
Finished Jun 11 12:46:06 PM PDT 24
Peak memory 220620 kb
Host smart-7cb01c3a-493c-43e8-9c7d-63d53e88dd33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688503155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3688503155
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.2489916288
Short name T470
Test name
Test status
Simulation time 877299563 ps
CPU time 2.6 seconds
Started Jun 11 12:46:10 PM PDT 24
Finished Jun 11 12:46:16 PM PDT 24
Peak memory 207892 kb
Host smart-5ef9eaa5-faa1-4570-a163-f69ffdb4a8a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489916288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.2489916288
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.4002434831
Short name T539
Test name
Test status
Simulation time 11381726 ps
CPU time 0.68 seconds
Started Jun 11 12:45:59 PM PDT 24
Finished Jun 11 12:46:02 PM PDT 24
Peak memory 205900 kb
Host smart-5ee7e2bb-a699-4069-a2a6-ab483fda928d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002434831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.4002434831
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.3896746751
Short name T858
Test name
Test status
Simulation time 207508917 ps
CPU time 0.79 seconds
Started Jun 11 12:46:03 PM PDT 24
Finished Jun 11 12:46:06 PM PDT 24
Peak memory 206108 kb
Host smart-15b10040-61a5-491d-8d8a-1b4e2416ad5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896746751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3896746751
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.1803925605
Short name T523
Test name
Test status
Simulation time 4245795047 ps
CPU time 16.32 seconds
Started Jun 11 12:45:39 PM PDT 24
Finished Jun 11 12:46:00 PM PDT 24
Peak memory 232992 kb
Host smart-81fe72ec-08e8-4c6f-949b-4b40bf5405eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803925605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.1803925605
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.1522086871
Short name T381
Test name
Test status
Simulation time 36456299 ps
CPU time 0.71 seconds
Started Jun 11 12:45:53 PM PDT 24
Finished Jun 11 12:45:56 PM PDT 24
Peak memory 205156 kb
Host smart-586aba0a-6650-420c-be45-a558815b99e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522086871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
1522086871
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.2759476949
Short name T368
Test name
Test status
Simulation time 47961541 ps
CPU time 2.45 seconds
Started Jun 11 12:45:58 PM PDT 24
Finished Jun 11 12:46:02 PM PDT 24
Peak memory 232936 kb
Host smart-a0b66f96-5681-4f78-8d45-db72e166dded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759476949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.2759476949
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.3631863399
Short name T478
Test name
Test status
Simulation time 36968938 ps
CPU time 0.76 seconds
Started Jun 11 12:46:08 PM PDT 24
Finished Jun 11 12:46:11 PM PDT 24
Peak memory 207168 kb
Host smart-a5bbe4a1-2461-4b9b-8e93-2290a1015f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631863399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.3631863399
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.1976947283
Short name T276
Test name
Test status
Simulation time 25865505695 ps
CPU time 264.21 seconds
Started Jun 11 12:46:19 PM PDT 24
Finished Jun 11 12:50:47 PM PDT 24
Peak memory 248920 kb
Host smart-da9ee448-df19-4036-ab03-0b003990f459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976947283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.1976947283
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.4046282096
Short name T528
Test name
Test status
Simulation time 2173740619 ps
CPU time 45.91 seconds
Started Jun 11 12:46:08 PM PDT 24
Finished Jun 11 12:46:56 PM PDT 24
Peak memory 249544 kb
Host smart-0662d2e8-4b26-4151-b619-0bd900d56676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046282096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.4046282096
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.1463748562
Short name T796
Test name
Test status
Simulation time 1864461885 ps
CPU time 29.72 seconds
Started Jun 11 12:46:05 PM PDT 24
Finished Jun 11 12:46:37 PM PDT 24
Peak memory 238240 kb
Host smart-a0dcd953-9a80-4efb-b606-a04bf8b2b7fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463748562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1463748562
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.4198096124
Short name T876
Test name
Test status
Simulation time 3759188044 ps
CPU time 12.21 seconds
Started Jun 11 12:45:53 PM PDT 24
Finished Jun 11 12:46:07 PM PDT 24
Peak memory 233116 kb
Host smart-0178756e-e00d-4fcd-b801-51f56b5fb9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198096124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.4198096124
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.251962397
Short name T293
Test name
Test status
Simulation time 2278281475 ps
CPU time 7.31 seconds
Started Jun 11 12:45:52 PM PDT 24
Finished Jun 11 12:46:06 PM PDT 24
Peak memory 233088 kb
Host smart-b8c12a00-507f-41a0-b751-2ba307aa8dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251962397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.251962397
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.1248626560
Short name T289
Test name
Test status
Simulation time 71880752 ps
CPU time 2.7 seconds
Started Jun 11 12:45:55 PM PDT 24
Finished Jun 11 12:46:00 PM PDT 24
Peak memory 232992 kb
Host smart-d6ad4184-5ee6-4199-a334-98f84150bf19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248626560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.1248626560
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.2219830989
Short name T31
Test name
Test status
Simulation time 775664634 ps
CPU time 2.88 seconds
Started Jun 11 12:45:59 PM PDT 24
Finished Jun 11 12:46:04 PM PDT 24
Peak memory 233004 kb
Host smart-48e8d3a9-39d7-4f5a-890d-1de2a12f9c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219830989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.2219830989
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.453000383
Short name T137
Test name
Test status
Simulation time 767960482 ps
CPU time 3.62 seconds
Started Jun 11 12:45:55 PM PDT 24
Finished Jun 11 12:46:00 PM PDT 24
Peak memory 223332 kb
Host smart-cbde34a8-e83d-41de-b15a-d75bb4ed50e6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=453000383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dire
ct.453000383
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.2638349353
Short name T309
Test name
Test status
Simulation time 13381381956 ps
CPU time 24.94 seconds
Started Jun 11 12:45:56 PM PDT 24
Finished Jun 11 12:46:22 PM PDT 24
Peak memory 223904 kb
Host smart-e94ebf58-336e-4435-81e8-ebf04f90a502
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638349353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.2638349353
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.4224015514
Short name T537
Test name
Test status
Simulation time 479355880 ps
CPU time 3.68 seconds
Started Jun 11 12:45:54 PM PDT 24
Finished Jun 11 12:46:00 PM PDT 24
Peak memory 216620 kb
Host smart-1b85405f-59bd-4fef-b7be-89d1e9d0be1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224015514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.4224015514
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.736275626
Short name T625
Test name
Test status
Simulation time 3985151764 ps
CPU time 7.5 seconds
Started Jun 11 12:45:55 PM PDT 24
Finished Jun 11 12:46:04 PM PDT 24
Peak memory 216672 kb
Host smart-291b270c-48aa-483c-a964-cfd6babbd020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736275626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.736275626
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.3126052724
Short name T829
Test name
Test status
Simulation time 11459652 ps
CPU time 0.67 seconds
Started Jun 11 12:46:00 PM PDT 24
Finished Jun 11 12:46:02 PM PDT 24
Peak memory 205908 kb
Host smart-ad90dfae-86f7-426c-866f-48f31127d080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126052724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3126052724
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.1193950975
Short name T420
Test name
Test status
Simulation time 57772893 ps
CPU time 0.91 seconds
Started Jun 11 12:45:56 PM PDT 24
Finished Jun 11 12:45:59 PM PDT 24
Peak memory 206188 kb
Host smart-547e6f80-cb75-4dfc-a613-ae34e77a8220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193950975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.1193950975
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.3313636601
Short name T844
Test name
Test status
Simulation time 14517648080 ps
CPU time 13.41 seconds
Started Jun 11 12:45:54 PM PDT 24
Finished Jun 11 12:46:09 PM PDT 24
Peak memory 241296 kb
Host smart-192e25d6-6416-4382-8991-b7ad9be662f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313636601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.3313636601
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.356628829
Short name T378
Test name
Test status
Simulation time 20830013 ps
CPU time 0.71 seconds
Started Jun 11 12:46:04 PM PDT 24
Finished Jun 11 12:46:07 PM PDT 24
Peak memory 205676 kb
Host smart-6c4137c7-c433-452f-b92b-ddc3f2bbe550
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356628829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.356628829
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.2951608498
Short name T193
Test name
Test status
Simulation time 1194544618 ps
CPU time 14.71 seconds
Started Jun 11 12:46:04 PM PDT 24
Finished Jun 11 12:46:20 PM PDT 24
Peak memory 224820 kb
Host smart-22663e68-7a46-43d2-a2b5-ff1f14f6e11a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951608498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.2951608498
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.453507804
Short name T491
Test name
Test status
Simulation time 104773202 ps
CPU time 0.78 seconds
Started Jun 11 12:45:54 PM PDT 24
Finished Jun 11 12:45:57 PM PDT 24
Peak memory 206124 kb
Host smart-adb1c756-eb9c-4329-ba5f-9a8b4f5e5416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453507804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.453507804
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.571093611
Short name T246
Test name
Test status
Simulation time 4598251497 ps
CPU time 52.89 seconds
Started Jun 11 12:46:13 PM PDT 24
Finished Jun 11 12:47:09 PM PDT 24
Peak memory 254896 kb
Host smart-673cda11-1385-4bd2-8c49-80dd23aecfa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571093611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.571093611
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.4270791053
Short name T266
Test name
Test status
Simulation time 23682737515 ps
CPU time 206.57 seconds
Started Jun 11 12:46:07 PM PDT 24
Finished Jun 11 12:49:36 PM PDT 24
Peak memory 236640 kb
Host smart-6e8ce2b3-77cf-45fc-9fc6-a173d2e2ff9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270791053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.4270791053
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.579347529
Short name T561
Test name
Test status
Simulation time 10222901703 ps
CPU time 158.18 seconds
Started Jun 11 12:46:04 PM PDT 24
Finished Jun 11 12:48:44 PM PDT 24
Peak memory 264372 kb
Host smart-d514e771-d289-4090-a789-f0ad86216b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579347529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle
.579347529
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.1721747414
Short name T320
Test name
Test status
Simulation time 533572605 ps
CPU time 9.4 seconds
Started Jun 11 12:46:06 PM PDT 24
Finished Jun 11 12:46:17 PM PDT 24
Peak memory 234040 kb
Host smart-4d1fceae-55b2-4425-a020-59bd4636c942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721747414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1721747414
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.3013255706
Short name T164
Test name
Test status
Simulation time 4311524535 ps
CPU time 16.19 seconds
Started Jun 11 12:46:12 PM PDT 24
Finished Jun 11 12:46:31 PM PDT 24
Peak memory 233308 kb
Host smart-6d5d65cf-a902-4e9d-b2cb-e332e5a59654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013255706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.3013255706
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.2891670921
Short name T832
Test name
Test status
Simulation time 13118405201 ps
CPU time 89.37 seconds
Started Jun 11 12:46:06 PM PDT 24
Finished Jun 11 12:47:37 PM PDT 24
Peak memory 233108 kb
Host smart-d2e1d918-9811-48d6-b617-348021aa3f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891670921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.2891670921
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.4152624507
Short name T226
Test name
Test status
Simulation time 552731913 ps
CPU time 4.03 seconds
Started Jun 11 12:45:51 PM PDT 24
Finished Jun 11 12:45:57 PM PDT 24
Peak memory 228584 kb
Host smart-4ed770fa-6bfe-4d97-90fc-34bf0be202f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152624507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.4152624507
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.521949651
Short name T607
Test name
Test status
Simulation time 3303543440 ps
CPU time 4.95 seconds
Started Jun 11 12:46:16 PM PDT 24
Finished Jun 11 12:46:24 PM PDT 24
Peak memory 229584 kb
Host smart-e2867d9d-a6ed-41ae-aea3-e6ef97341c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521949651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.521949651
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.2739852864
Short name T950
Test name
Test status
Simulation time 5069119057 ps
CPU time 18.35 seconds
Started Jun 11 12:46:28 PM PDT 24
Finished Jun 11 12:46:48 PM PDT 24
Peak memory 221132 kb
Host smart-45bfd5d5-8390-48f9-9c09-27d3b4af75c2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2739852864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.2739852864
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.2275437369
Short name T310
Test name
Test status
Simulation time 1059469152 ps
CPU time 10.9 seconds
Started Jun 11 12:46:07 PM PDT 24
Finished Jun 11 12:46:20 PM PDT 24
Peak memory 216604 kb
Host smart-a8e353e6-e66e-45f6-8a87-837f5c234048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275437369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.2275437369
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.3466008938
Short name T881
Test name
Test status
Simulation time 7674232815 ps
CPU time 14.45 seconds
Started Jun 11 12:46:05 PM PDT 24
Finished Jun 11 12:46:22 PM PDT 24
Peak memory 216692 kb
Host smart-0d2e878f-40de-43b1-8179-0a9d1063a1e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466008938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3466008938
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.603276055
Short name T703
Test name
Test status
Simulation time 286585234 ps
CPU time 4.27 seconds
Started Jun 11 12:46:18 PM PDT 24
Finished Jun 11 12:46:26 PM PDT 24
Peak memory 216524 kb
Host smart-71c3d186-82d3-4622-a222-58dd8f37d49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603276055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.603276055
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.1621298706
Short name T335
Test name
Test status
Simulation time 321431174 ps
CPU time 0.91 seconds
Started Jun 11 12:45:50 PM PDT 24
Finished Jun 11 12:45:53 PM PDT 24
Peak memory 206156 kb
Host smart-6324a793-9fb9-4714-b053-8351b25bf2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621298706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.1621298706
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.2050149967
Short name T562
Test name
Test status
Simulation time 2181005257 ps
CPU time 7.94 seconds
Started Jun 11 12:46:09 PM PDT 24
Finished Jun 11 12:46:20 PM PDT 24
Peak memory 224812 kb
Host smart-9097adf4-2509-4302-b95b-c02e54790aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050149967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.2050149967
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.2887209897
Short name T370
Test name
Test status
Simulation time 12987250 ps
CPU time 0.71 seconds
Started Jun 11 12:46:15 PM PDT 24
Finished Jun 11 12:46:19 PM PDT 24
Peak memory 205116 kb
Host smart-1ac6a4ce-cdc2-45a4-87a0-27c36f09b281
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887209897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
2887209897
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.1369083497
Short name T647
Test name
Test status
Simulation time 625295872 ps
CPU time 3.69 seconds
Started Jun 11 12:45:59 PM PDT 24
Finished Jun 11 12:46:05 PM PDT 24
Peak memory 232952 kb
Host smart-c845de13-3599-4464-9456-671eeeabfcaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369083497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.1369083497
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.1782231443
Short name T824
Test name
Test status
Simulation time 28577367 ps
CPU time 0.76 seconds
Started Jun 11 12:46:14 PM PDT 24
Finished Jun 11 12:46:18 PM PDT 24
Peak memory 206836 kb
Host smart-7c08c55f-8617-486a-a6d6-276d248cdd0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782231443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.1782231443
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.1211571301
Short name T83
Test name
Test status
Simulation time 60271095787 ps
CPU time 92.5 seconds
Started Jun 11 12:46:18 PM PDT 24
Finished Jun 11 12:47:54 PM PDT 24
Peak memory 240280 kb
Host smart-66cd0c95-085f-413a-8f99-cdaa0f7cd53b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211571301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.1211571301
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.2720964240
Short name T855
Test name
Test status
Simulation time 2457152398 ps
CPU time 48.9 seconds
Started Jun 11 12:46:09 PM PDT 24
Finished Jun 11 12:47:01 PM PDT 24
Peak memory 240732 kb
Host smart-3068a59c-36c8-4684-b7e1-8f42bab73ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720964240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.2720964240
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.3902934729
Short name T160
Test name
Test status
Simulation time 17456399238 ps
CPU time 160.75 seconds
Started Jun 11 12:46:10 PM PDT 24
Finished Jun 11 12:48:54 PM PDT 24
Peak memory 249476 kb
Host smart-74b29b37-93ae-4dd1-874d-3cfc31802a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902934729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.3902934729
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.2182462360
Short name T465
Test name
Test status
Simulation time 2110411491 ps
CPU time 4.63 seconds
Started Jun 11 12:46:07 PM PDT 24
Finished Jun 11 12:46:14 PM PDT 24
Peak memory 233004 kb
Host smart-4eb54989-a911-481a-8404-c29deeeaf74f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182462360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.2182462360
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1473763849
Short name T375
Test name
Test status
Simulation time 3419276313 ps
CPU time 12.37 seconds
Started Jun 11 12:46:17 PM PDT 24
Finished Jun 11 12:46:34 PM PDT 24
Peak memory 224900 kb
Host smart-502abefe-38e3-41b7-a1d2-d2ce71358ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473763849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1473763849
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.13165584
Short name T682
Test name
Test status
Simulation time 113166837241 ps
CPU time 134.71 seconds
Started Jun 11 12:46:03 PM PDT 24
Finished Jun 11 12:48:19 PM PDT 24
Peak memory 249508 kb
Host smart-cf487906-a362-4774-8085-77d13e1c04d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13165584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.13165584
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.348474411
Short name T935
Test name
Test status
Simulation time 12701568976 ps
CPU time 28.73 seconds
Started Jun 11 12:45:51 PM PDT 24
Finished Jun 11 12:46:22 PM PDT 24
Peak memory 232956 kb
Host smart-43a385d3-9870-43d4-8a85-0edde48fdc2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348474411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap
.348474411
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.592034836
Short name T158
Test name
Test status
Simulation time 704634736 ps
CPU time 4.57 seconds
Started Jun 11 12:46:08 PM PDT 24
Finished Jun 11 12:46:15 PM PDT 24
Peak memory 232980 kb
Host smart-b64849a0-b619-4490-90af-eeadbc9c5578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592034836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.592034836
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.3085019136
Short name T860
Test name
Test status
Simulation time 1663239001 ps
CPU time 9.99 seconds
Started Jun 11 12:46:10 PM PDT 24
Finished Jun 11 12:46:23 PM PDT 24
Peak memory 218980 kb
Host smart-4b801541-1a23-46c0-9008-5c7753d1e328
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3085019136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.3085019136
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.88040965
Short name T493
Test name
Test status
Simulation time 137372898 ps
CPU time 0.94 seconds
Started Jun 11 12:45:58 PM PDT 24
Finished Jun 11 12:46:01 PM PDT 24
Peak memory 207216 kb
Host smart-255ce864-5f41-4a1e-86a9-6965822f96cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88040965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stress
_all.88040965
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.1396704486
Short name T532
Test name
Test status
Simulation time 5316439306 ps
CPU time 28.63 seconds
Started Jun 11 12:46:17 PM PDT 24
Finished Jun 11 12:46:49 PM PDT 24
Peak memory 216620 kb
Host smart-8dde8ecc-2a57-4b41-9eb8-f9e926cdaea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396704486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.1396704486
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.1634811047
Short name T677
Test name
Test status
Simulation time 112678825 ps
CPU time 3.53 seconds
Started Jun 11 12:46:08 PM PDT 24
Finished Jun 11 12:46:14 PM PDT 24
Peak memory 216500 kb
Host smart-9612a90e-5749-4082-a9f7-3d9e3ee117e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634811047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1634811047
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.817895080
Short name T349
Test name
Test status
Simulation time 37900612 ps
CPU time 0.78 seconds
Started Jun 11 12:46:06 PM PDT 24
Finished Jun 11 12:46:09 PM PDT 24
Peak memory 206108 kb
Host smart-3fcc9dd1-060b-4b62-a0fa-19ea1cc5ea64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817895080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.817895080
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.2576514016
Short name T288
Test name
Test status
Simulation time 1604581219 ps
CPU time 5.48 seconds
Started Jun 11 12:46:07 PM PDT 24
Finished Jun 11 12:46:15 PM PDT 24
Peak memory 224644 kb
Host smart-bf995a37-08b3-4ae9-bdcf-ab0a7c53d9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576514016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.2576514016
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.2490026170
Short name T847
Test name
Test status
Simulation time 53732843 ps
CPU time 0.7 seconds
Started Jun 11 12:46:11 PM PDT 24
Finished Jun 11 12:46:15 PM PDT 24
Peak memory 206060 kb
Host smart-4d5d6658-5406-40fc-b6d2-d5888504d94b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490026170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
2490026170
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.3226835342
Short name T620
Test name
Test status
Simulation time 2361671160 ps
CPU time 8.14 seconds
Started Jun 11 12:46:09 PM PDT 24
Finished Jun 11 12:46:19 PM PDT 24
Peak memory 224916 kb
Host smart-41ca8a38-ebb4-4d4d-8495-64dcc71f95cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226835342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.3226835342
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.1304062508
Short name T500
Test name
Test status
Simulation time 20223724 ps
CPU time 0.74 seconds
Started Jun 11 12:46:01 PM PDT 24
Finished Jun 11 12:46:04 PM PDT 24
Peak memory 206144 kb
Host smart-007272bd-6204-44b1-8b87-7ae01f93c179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304062508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.1304062508
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.3195144403
Short name T501
Test name
Test status
Simulation time 55899730148 ps
CPU time 27.37 seconds
Started Jun 11 12:46:09 PM PDT 24
Finished Jun 11 12:46:38 PM PDT 24
Peak memory 237392 kb
Host smart-4041da1a-2498-4f60-96a5-03c60e2009e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195144403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.3195144403
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.2440377991
Short name T40
Test name
Test status
Simulation time 3584121951 ps
CPU time 54.25 seconds
Started Jun 11 12:46:05 PM PDT 24
Finished Jun 11 12:47:01 PM PDT 24
Peak memory 255076 kb
Host smart-fba2eb39-8394-45a4-9176-f746087cb214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440377991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2440377991
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.2958496512
Short name T236
Test name
Test status
Simulation time 391216627041 ps
CPU time 396.73 seconds
Started Jun 11 12:46:02 PM PDT 24
Finished Jun 11 12:52:41 PM PDT 24
Peak memory 249688 kb
Host smart-80a7e91c-fdb7-47dc-9e0c-e79cd0944a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958496512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.2958496512
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.483849005
Short name T541
Test name
Test status
Simulation time 794530062 ps
CPU time 9.29 seconds
Started Jun 11 12:45:57 PM PDT 24
Finished Jun 11 12:46:08 PM PDT 24
Peak memory 224752 kb
Host smart-4336e4e7-2fe2-41a6-bc71-f7a2ab25abfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483849005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.483849005
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.3243354646
Short name T831
Test name
Test status
Simulation time 4480316627 ps
CPU time 7.04 seconds
Started Jun 11 12:46:16 PM PDT 24
Finished Jun 11 12:46:26 PM PDT 24
Peak memory 224840 kb
Host smart-972395b1-3d46-4e96-8d6b-9a438c2eff4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243354646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3243354646
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.3386948597
Short name T833
Test name
Test status
Simulation time 1870081123 ps
CPU time 23.73 seconds
Started Jun 11 12:46:07 PM PDT 24
Finished Jun 11 12:46:33 PM PDT 24
Peak memory 235152 kb
Host smart-43c338e7-cb29-4598-b72c-37a23940330e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386948597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.3386948597
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.886103374
Short name T497
Test name
Test status
Simulation time 18393848839 ps
CPU time 13.15 seconds
Started Jun 11 12:46:23 PM PDT 24
Finished Jun 11 12:46:39 PM PDT 24
Peak memory 224908 kb
Host smart-ffec2b7c-9abf-4ffd-89c0-efef4e7fbdd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886103374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap
.886103374
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.1768987489
Short name T405
Test name
Test status
Simulation time 1233714149 ps
CPU time 6.7 seconds
Started Jun 11 12:46:14 PM PDT 24
Finished Jun 11 12:46:24 PM PDT 24
Peak memory 232888 kb
Host smart-bd316308-acd6-48b3-829d-7182d0831cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768987489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1768987489
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.3834824727
Short name T946
Test name
Test status
Simulation time 23557769761 ps
CPU time 9.84 seconds
Started Jun 11 12:46:00 PM PDT 24
Finished Jun 11 12:46:13 PM PDT 24
Peak memory 219756 kb
Host smart-cd73a9dc-519f-4b4a-8ff0-27ddf8607ceb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3834824727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.3834824727
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.3407776604
Short name T696
Test name
Test status
Simulation time 854885159 ps
CPU time 8.65 seconds
Started Jun 11 12:46:06 PM PDT 24
Finished Jun 11 12:46:17 PM PDT 24
Peak memory 216540 kb
Host smart-9fe7f544-581a-4d40-94d5-21f28fb9fa68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407776604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3407776604
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3568122138
Short name T328
Test name
Test status
Simulation time 2042731213 ps
CPU time 6.29 seconds
Started Jun 11 12:46:02 PM PDT 24
Finished Jun 11 12:46:10 PM PDT 24
Peak memory 216500 kb
Host smart-81f479ae-6ca5-44ba-bc24-9b141622c469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568122138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3568122138
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.3254389941
Short name T557
Test name
Test status
Simulation time 98125571 ps
CPU time 0.88 seconds
Started Jun 11 12:46:18 PM PDT 24
Finished Jun 11 12:46:23 PM PDT 24
Peak memory 206184 kb
Host smart-fcd2527a-9fa3-4a95-811f-8699af01b743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254389941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3254389941
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.1651675957
Short name T527
Test name
Test status
Simulation time 4454986483 ps
CPU time 8.16 seconds
Started Jun 11 12:46:03 PM PDT 24
Finished Jun 11 12:46:13 PM PDT 24
Peak memory 224912 kb
Host smart-e7f99593-434d-4c42-9e01-649f5996e188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651675957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.1651675957
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.3873107376
Short name T719
Test name
Test status
Simulation time 59240639 ps
CPU time 0.74 seconds
Started Jun 11 12:46:15 PM PDT 24
Finished Jun 11 12:46:19 PM PDT 24
Peak memory 205700 kb
Host smart-5bfbb55e-7b99-47cd-be94-e0322afe392d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873107376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
3873107376
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.3232461366
Short name T759
Test name
Test status
Simulation time 78216200 ps
CPU time 2.21 seconds
Started Jun 11 12:46:08 PM PDT 24
Finished Jun 11 12:46:12 PM PDT 24
Peak memory 224984 kb
Host smart-680aa8b0-692c-4960-a7ec-c3b38116a2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232461366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.3232461366
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.549233825
Short name T763
Test name
Test status
Simulation time 39486522 ps
CPU time 0.75 seconds
Started Jun 11 12:46:03 PM PDT 24
Finished Jun 11 12:46:06 PM PDT 24
Peak memory 207224 kb
Host smart-9fe55d1b-eca1-480a-8bfb-f16fe5a3ed8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549233825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.549233825
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.1996982872
Short name T952
Test name
Test status
Simulation time 11773551646 ps
CPU time 124.52 seconds
Started Jun 11 12:46:17 PM PDT 24
Finished Jun 11 12:48:26 PM PDT 24
Peak memory 254552 kb
Host smart-77878a4e-63a4-4f23-9b4b-93107df67b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996982872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.1996982872
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.3646833684
Short name T179
Test name
Test status
Simulation time 79723463107 ps
CPU time 263.29 seconds
Started Jun 11 12:46:04 PM PDT 24
Finished Jun 11 12:50:29 PM PDT 24
Peak memory 254436 kb
Host smart-66bc55dd-ee58-4c72-a9fa-ccf21ee89654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646833684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.3646833684
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.3580124824
Short name T279
Test name
Test status
Simulation time 161659783451 ps
CPU time 376.67 seconds
Started Jun 11 12:46:10 PM PDT 24
Finished Jun 11 12:52:29 PM PDT 24
Peak memory 252176 kb
Host smart-5b7c9cbb-23ef-4ecf-9e5a-ee63fd6e21d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580124824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.3580124824
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.4239838060
Short name T861
Test name
Test status
Simulation time 3926794381 ps
CPU time 39.29 seconds
Started Jun 11 12:45:52 PM PDT 24
Finished Jun 11 12:46:34 PM PDT 24
Peak memory 249480 kb
Host smart-cde016e8-dd6c-4c1c-b60a-719145db8e5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239838060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.4239838060
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.1557536184
Short name T191
Test name
Test status
Simulation time 244230492 ps
CPU time 5.55 seconds
Started Jun 11 12:46:00 PM PDT 24
Finished Jun 11 12:46:07 PM PDT 24
Peak memory 232976 kb
Host smart-b7bad110-a9a7-4947-b23f-9543c69024a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557536184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.1557536184
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.2891687331
Short name T621
Test name
Test status
Simulation time 154609941 ps
CPU time 2.25 seconds
Started Jun 11 12:46:04 PM PDT 24
Finished Jun 11 12:46:08 PM PDT 24
Peak memory 232800 kb
Host smart-2cb508c9-a1ad-457f-a287-5274024bb5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2891687331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.2891687331
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2621862218
Short name T438
Test name
Test status
Simulation time 2104887903 ps
CPU time 10.49 seconds
Started Jun 11 12:45:50 PM PDT 24
Finished Jun 11 12:46:03 PM PDT 24
Peak memory 224808 kb
Host smart-9c439f4b-04c1-473a-a82e-23e8f80b922f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621862218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.2621862218
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.3036887253
Short name T705
Test name
Test status
Simulation time 1375064094 ps
CPU time 7.19 seconds
Started Jun 11 12:46:04 PM PDT 24
Finished Jun 11 12:46:12 PM PDT 24
Peak memory 240440 kb
Host smart-996951b6-ca76-4262-9b2b-a0e8e2520076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3036887253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.3036887253
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.2663769668
Short name T747
Test name
Test status
Simulation time 13405596766 ps
CPU time 173.38 seconds
Started Jun 11 12:46:23 PM PDT 24
Finished Jun 11 12:49:20 PM PDT 24
Peak memory 254192 kb
Host smart-8c6f82b8-9b7c-4128-a508-d8912f9b4d9d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663769668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.2663769668
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.993565855
Short name T907
Test name
Test status
Simulation time 15481429109 ps
CPU time 44.65 seconds
Started Jun 11 12:46:02 PM PDT 24
Finished Jun 11 12:46:48 PM PDT 24
Peak memory 221212 kb
Host smart-94e9f2e3-ebd7-4262-98ef-36c95b81ef60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993565855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.993565855
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1369277901
Short name T365
Test name
Test status
Simulation time 1328566876 ps
CPU time 3.8 seconds
Started Jun 11 12:46:10 PM PDT 24
Finished Jun 11 12:46:16 PM PDT 24
Peak memory 216732 kb
Host smart-761c7306-0399-452b-93f1-88317d4292ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369277901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1369277901
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.3936435324
Short name T771
Test name
Test status
Simulation time 187403023 ps
CPU time 1.3 seconds
Started Jun 11 12:45:58 PM PDT 24
Finished Jun 11 12:46:01 PM PDT 24
Peak memory 216364 kb
Host smart-3fc8c680-28fa-4b98-8544-4c171cf53dba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936435324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.3936435324
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.1211375840
Short name T538
Test name
Test status
Simulation time 109109425 ps
CPU time 0.9 seconds
Started Jun 11 12:45:56 PM PDT 24
Finished Jun 11 12:45:58 PM PDT 24
Peak memory 207180 kb
Host smart-b91b954f-8c4a-43af-806c-82eb066379f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211375840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1211375840
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.879684845
Short name T906
Test name
Test status
Simulation time 1456598604 ps
CPU time 3.24 seconds
Started Jun 11 12:46:04 PM PDT 24
Finished Jun 11 12:46:09 PM PDT 24
Peak memory 232948 kb
Host smart-e8f5bf45-61a7-4f8a-8869-400c58d87bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879684845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.879684845
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.467337579
Short name T413
Test name
Test status
Simulation time 38569160 ps
CPU time 0.69 seconds
Started Jun 11 12:46:11 PM PDT 24
Finished Jun 11 12:46:15 PM PDT 24
Peak memory 205064 kb
Host smart-936aee21-e4e5-45a7-931a-1b59b0860e94
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467337579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.467337579
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.3620675444
Short name T87
Test name
Test status
Simulation time 922598197 ps
CPU time 3.18 seconds
Started Jun 11 12:46:12 PM PDT 24
Finished Jun 11 12:46:18 PM PDT 24
Peak memory 224688 kb
Host smart-2901df21-777e-418c-9fe4-aed01be938d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620675444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.3620675444
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.591375291
Short name T722
Test name
Test status
Simulation time 98459487 ps
CPU time 0.76 seconds
Started Jun 11 12:46:21 PM PDT 24
Finished Jun 11 12:46:26 PM PDT 24
Peak memory 206916 kb
Host smart-3bbaf3fe-d24c-4360-83dd-7f0d58a54484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591375291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.591375291
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.2217487039
Short name T228
Test name
Test status
Simulation time 19389939281 ps
CPU time 93.82 seconds
Started Jun 11 12:46:25 PM PDT 24
Finished Jun 11 12:48:01 PM PDT 24
Peak memory 256560 kb
Host smart-7fbdbf2f-bfba-4361-bd95-69be3bb79345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217487039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.2217487039
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.1354899459
Short name T215
Test name
Test status
Simulation time 130642227520 ps
CPU time 509.25 seconds
Started Jun 11 12:46:11 PM PDT 24
Finished Jun 11 12:54:44 PM PDT 24
Peak memory 265244 kb
Host smart-629e43a2-35c6-46a5-badd-2d0458082197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354899459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.1354899459
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.2628520224
Short name T651
Test name
Test status
Simulation time 2223210147 ps
CPU time 38.75 seconds
Started Jun 11 12:46:37 PM PDT 24
Finished Jun 11 12:47:18 PM PDT 24
Peak memory 235404 kb
Host smart-93bde12b-4070-4587-a141-5826fdbff760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628520224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.2628520224
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.4016495292
Short name T303
Test name
Test status
Simulation time 1167106540 ps
CPU time 8.82 seconds
Started Jun 11 12:46:13 PM PDT 24
Finished Jun 11 12:46:25 PM PDT 24
Peak memory 224788 kb
Host smart-48ee09c1-971f-4992-ad4c-b1737e04101c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016495292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.4016495292
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.2561483132
Short name T187
Test name
Test status
Simulation time 490533902 ps
CPU time 6.93 seconds
Started Jun 11 12:46:15 PM PDT 24
Finished Jun 11 12:46:25 PM PDT 24
Peak memory 218912 kb
Host smart-85fab47c-b149-49d2-92cd-5fba10952004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561483132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.2561483132
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.2124821973
Short name T25
Test name
Test status
Simulation time 1000616351 ps
CPU time 18.52 seconds
Started Jun 11 12:46:16 PM PDT 24
Finished Jun 11 12:46:38 PM PDT 24
Peak memory 249316 kb
Host smart-c6e2f1e5-28c4-4db5-8cb8-e6f826904955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124821973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.2124821973
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.780574593
Short name T611
Test name
Test status
Simulation time 333612761 ps
CPU time 5.42 seconds
Started Jun 11 12:46:13 PM PDT 24
Finished Jun 11 12:46:22 PM PDT 24
Peak memory 224736 kb
Host smart-96ce86a4-97f0-40b0-a660-087fddcf1492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780574593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap
.780574593
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3108411192
Short name T581
Test name
Test status
Simulation time 399341934 ps
CPU time 4.86 seconds
Started Jun 11 12:46:15 PM PDT 24
Finished Jun 11 12:46:24 PM PDT 24
Peak memory 240572 kb
Host smart-62cd48d7-2cc2-4604-9101-71da83dc9419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108411192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3108411192
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.202181710
Short name T777
Test name
Test status
Simulation time 5965156637 ps
CPU time 22.91 seconds
Started Jun 11 12:46:14 PM PDT 24
Finished Jun 11 12:46:40 PM PDT 24
Peak memory 220688 kb
Host smart-5b114894-42fe-491b-b577-d6f8cdc8a0aa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=202181710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dire
ct.202181710
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.3669668560
Short name T799
Test name
Test status
Simulation time 13196142351 ps
CPU time 80.68 seconds
Started Jun 11 12:46:11 PM PDT 24
Finished Jun 11 12:47:35 PM PDT 24
Peak memory 237208 kb
Host smart-0bb56c28-19eb-41ff-8556-6d31b0a5da5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669668560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.3669668560
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.544784391
Short name T791
Test name
Test status
Simulation time 2595549720 ps
CPU time 7.9 seconds
Started Jun 11 12:46:11 PM PDT 24
Finished Jun 11 12:46:22 PM PDT 24
Peak memory 216684 kb
Host smart-e1198e09-1656-4459-9058-501d3cecc3d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544784391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.544784391
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.660281135
Short name T896
Test name
Test status
Simulation time 310647863 ps
CPU time 2.03 seconds
Started Jun 11 12:46:16 PM PDT 24
Finished Jun 11 12:46:21 PM PDT 24
Peak memory 207516 kb
Host smart-492b18d1-a4d8-4412-b879-655027f2df69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660281135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.660281135
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.460849173
Short name T699
Test name
Test status
Simulation time 872924885 ps
CPU time 2.87 seconds
Started Jun 11 12:46:11 PM PDT 24
Finished Jun 11 12:46:16 PM PDT 24
Peak memory 216608 kb
Host smart-274ff917-88b2-4837-a2bc-7950d817a158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460849173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.460849173
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.1730386648
Short name T529
Test name
Test status
Simulation time 61591711 ps
CPU time 0.79 seconds
Started Jun 11 12:46:21 PM PDT 24
Finished Jun 11 12:46:25 PM PDT 24
Peak memory 206168 kb
Host smart-f2d27626-6401-49e4-8bca-64a58216a0d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730386648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.1730386648
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.2668848601
Short name T798
Test name
Test status
Simulation time 502493660 ps
CPU time 6.51 seconds
Started Jun 11 12:46:23 PM PDT 24
Finished Jun 11 12:46:33 PM PDT 24
Peak memory 232924 kb
Host smart-0de6b530-cbb3-4a99-a0b0-084a0909cab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668848601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.2668848601
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.14768337
Short name T397
Test name
Test status
Simulation time 57820543 ps
CPU time 2.27 seconds
Started Jun 11 12:45:36 PM PDT 24
Finished Jun 11 12:45:41 PM PDT 24
Peak memory 233000 kb
Host smart-19fb6327-319d-4d61-a2b2-b7e01570e7d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14768337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.14768337
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.1838522088
Short name T483
Test name
Test status
Simulation time 139594372 ps
CPU time 0.76 seconds
Started Jun 11 12:45:30 PM PDT 24
Finished Jun 11 12:45:32 PM PDT 24
Peak memory 207248 kb
Host smart-3db44c9f-bf85-4a4e-9ffe-e30a3272b2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838522088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1838522088
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.2316374591
Short name T555
Test name
Test status
Simulation time 1607682116 ps
CPU time 5.89 seconds
Started Jun 11 12:45:26 PM PDT 24
Finished Jun 11 12:45:34 PM PDT 24
Peak memory 224780 kb
Host smart-3eaa7ebb-66b4-41e8-b824-37287d0f1bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316374591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.2316374591
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.4048926940
Short name T932
Test name
Test status
Simulation time 10246045370 ps
CPU time 101.49 seconds
Started Jun 11 12:45:28 PM PDT 24
Finished Jun 11 12:47:12 PM PDT 24
Peak memory 223144 kb
Host smart-2d42cb36-d4c1-4f1d-99a4-4df336d6250a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048926940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.4048926940
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.1770216265
Short name T307
Test name
Test status
Simulation time 612784972 ps
CPU time 16.62 seconds
Started Jun 11 12:45:23 PM PDT 24
Finished Jun 11 12:45:42 PM PDT 24
Peak memory 234492 kb
Host smart-b3d70717-54e0-4558-ad1a-c9441f7e19bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770216265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.1770216265
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3683450848
Short name T656
Test name
Test status
Simulation time 4076794638 ps
CPU time 9.14 seconds
Started Jun 11 12:45:35 PM PDT 24
Finished Jun 11 12:45:48 PM PDT 24
Peak memory 230720 kb
Host smart-ff69d8da-c767-461d-9c00-702eaab9e706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683450848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3683450848
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3541205212
Short name T738
Test name
Test status
Simulation time 13294985353 ps
CPU time 17.97 seconds
Started Jun 11 12:45:38 PM PDT 24
Finished Jun 11 12:46:01 PM PDT 24
Peak memory 240748 kb
Host smart-2602cb5a-1dea-4775-82f4-8c3063e19da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541205212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3541205212
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.4222086659
Short name T870
Test name
Test status
Simulation time 582674599 ps
CPU time 5.64 seconds
Started Jun 11 12:45:31 PM PDT 24
Finished Jun 11 12:45:39 PM PDT 24
Peak memory 233104 kb
Host smart-48378726-6b11-43b6-8bb1-0421da9b3b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222086659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.4222086659
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.3132551267
Short name T447
Test name
Test status
Simulation time 447024892 ps
CPU time 4.12 seconds
Started Jun 11 12:45:35 PM PDT 24
Finished Jun 11 12:45:42 PM PDT 24
Peak memory 223260 kb
Host smart-1314d909-6d71-46b1-b93e-8e52a0973164
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3132551267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.3132551267
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.2072379224
Short name T68
Test name
Test status
Simulation time 37129347 ps
CPU time 1.1 seconds
Started Jun 11 12:45:26 PM PDT 24
Finished Jun 11 12:45:29 PM PDT 24
Peak memory 235996 kb
Host smart-2ab5e124-f056-46f9-b7d2-58e8f1885d01
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072379224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2072379224
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.187729208
Short name T825
Test name
Test status
Simulation time 112024562 ps
CPU time 0.92 seconds
Started Jun 11 12:45:35 PM PDT 24
Finished Jun 11 12:45:39 PM PDT 24
Peak memory 206896 kb
Host smart-f1dcae75-13df-4898-8a0a-2f6d1fa847dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187729208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress
_all.187729208
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.1533180559
Short name T362
Test name
Test status
Simulation time 38449531 ps
CPU time 0.72 seconds
Started Jun 11 12:45:26 PM PDT 24
Finished Jun 11 12:45:28 PM PDT 24
Peak memory 206000 kb
Host smart-785a4f48-a578-43c9-9687-ddd7d3b8a38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533180559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.1533180559
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.848549473
Short name T51
Test name
Test status
Simulation time 17303540212 ps
CPU time 10.98 seconds
Started Jun 11 12:45:34 PM PDT 24
Finished Jun 11 12:45:48 PM PDT 24
Peak memory 216620 kb
Host smart-c197d2b3-2514-4334-b1ba-dade96ac1094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848549473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.848549473
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2234389
Short name T374
Test name
Test status
Simulation time 429896398 ps
CPU time 1.77 seconds
Started Jun 11 12:45:36 PM PDT 24
Finished Jun 11 12:45:41 PM PDT 24
Peak memory 216540 kb
Host smart-0a3eaf91-b902-4161-9f1d-c52de3c54baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2234389
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.4048430116
Short name T788
Test name
Test status
Simulation time 109329062 ps
CPU time 0.96 seconds
Started Jun 11 12:45:43 PM PDT 24
Finished Jun 11 12:45:48 PM PDT 24
Peak memory 206172 kb
Host smart-36ed8c45-a532-44e0-9335-92ad4efa1220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048430116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.4048430116
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.1918949362
Short name T793
Test name
Test status
Simulation time 28999365120 ps
CPU time 9.32 seconds
Started Jun 11 12:45:26 PM PDT 24
Finished Jun 11 12:45:37 PM PDT 24
Peak memory 236136 kb
Host smart-7afa79ba-e292-4bd3-bfc7-a6b51cdeef76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918949362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.1918949362
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.965934249
Short name T588
Test name
Test status
Simulation time 33740511 ps
CPU time 0.7 seconds
Started Jun 11 12:46:29 PM PDT 24
Finished Jun 11 12:46:31 PM PDT 24
Peak memory 205744 kb
Host smart-a262998b-a3e7-4589-9343-c191d34ce33d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965934249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.965934249
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.214438122
Short name T253
Test name
Test status
Simulation time 692343519 ps
CPU time 3.38 seconds
Started Jun 11 12:46:14 PM PDT 24
Finished Jun 11 12:46:21 PM PDT 24
Peak memory 224720 kb
Host smart-841ec4bb-c7b4-4327-9793-1b567f639a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214438122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.214438122
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.1015550651
Short name T330
Test name
Test status
Simulation time 40825792 ps
CPU time 0.73 seconds
Started Jun 11 12:46:20 PM PDT 24
Finished Jun 11 12:46:25 PM PDT 24
Peak memory 205760 kb
Host smart-bd7762a8-77c3-4cf3-a165-c17691310844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015550651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1015550651
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.2379202105
Short name T54
Test name
Test status
Simulation time 14036256220 ps
CPU time 39.66 seconds
Started Jun 11 12:46:22 PM PDT 24
Finished Jun 11 12:47:05 PM PDT 24
Peak memory 251184 kb
Host smart-4969fdda-64d3-4ccb-adc7-b5ed20512fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379202105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.2379202105
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.1958957814
Short name T308
Test name
Test status
Simulation time 995248608 ps
CPU time 20.41 seconds
Started Jun 11 12:46:06 PM PDT 24
Finished Jun 11 12:46:28 PM PDT 24
Peak memory 238816 kb
Host smart-12a58884-c9dd-41cb-a311-6b0948a932aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958957814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.1958957814
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.404170169
Short name T167
Test name
Test status
Simulation time 60869491416 ps
CPU time 137.44 seconds
Started Jun 11 12:46:25 PM PDT 24
Finished Jun 11 12:48:45 PM PDT 24
Peak memory 253172 kb
Host smart-b865d847-74da-47c4-b3af-20b6c1900703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404170169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle
.404170169
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.2486398146
Short name T664
Test name
Test status
Simulation time 5476180637 ps
CPU time 22.86 seconds
Started Jun 11 12:46:00 PM PDT 24
Finished Jun 11 12:46:25 PM PDT 24
Peak memory 241276 kb
Host smart-9a5ceb65-b071-4228-8f36-a915c1de5b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486398146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.2486398146
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.3973406994
Short name T629
Test name
Test status
Simulation time 3105394612 ps
CPU time 7.43 seconds
Started Jun 11 12:46:08 PM PDT 24
Finished Jun 11 12:46:17 PM PDT 24
Peak memory 224864 kb
Host smart-9b85a8aa-c7db-4767-aca8-f42bef9eaa7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973406994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.3973406994
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.2242139167
Short name T502
Test name
Test status
Simulation time 1107768761 ps
CPU time 6.48 seconds
Started Jun 11 12:46:31 PM PDT 24
Finished Jun 11 12:46:39 PM PDT 24
Peak memory 232960 kb
Host smart-64cad7d1-cf70-4a03-8474-fd8bea982551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242139167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.2242139167
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1000271906
Short name T945
Test name
Test status
Simulation time 2993826698 ps
CPU time 4.73 seconds
Started Jun 11 12:46:19 PM PDT 24
Finished Jun 11 12:46:28 PM PDT 24
Peak memory 224692 kb
Host smart-c43f5e83-c9fa-4814-b114-4c2035d162c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000271906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1000271906
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.389327252
Short name T782
Test name
Test status
Simulation time 5263705750 ps
CPU time 15.84 seconds
Started Jun 11 12:46:14 PM PDT 24
Finished Jun 11 12:46:33 PM PDT 24
Peak memory 233136 kb
Host smart-0b008753-2de3-4730-9da8-fd9aa1a519af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389327252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.389327252
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.3518965327
Short name T44
Test name
Test status
Simulation time 924099969 ps
CPU time 6.06 seconds
Started Jun 11 12:46:13 PM PDT 24
Finished Jun 11 12:46:22 PM PDT 24
Peak memory 222740 kb
Host smart-3a873256-bff7-423f-87dc-b2e89794593b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3518965327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.3518965327
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.1810423210
Short name T399
Test name
Test status
Simulation time 1162622780 ps
CPU time 7.99 seconds
Started Jun 11 12:46:14 PM PDT 24
Finished Jun 11 12:46:25 PM PDT 24
Peak memory 216900 kb
Host smart-8fb2418a-d99a-4002-a5f3-fc9c9975a6e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810423210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.1810423210
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.2831623712
Short name T943
Test name
Test status
Simulation time 13735963827 ps
CPU time 7.09 seconds
Started Jun 11 12:46:12 PM PDT 24
Finished Jun 11 12:46:22 PM PDT 24
Peak memory 216652 kb
Host smart-d62092ab-c0e4-4453-9525-e86850c2fb53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831623712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.2831623712
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.3621468240
Short name T149
Test name
Test status
Simulation time 63069574 ps
CPU time 0.85 seconds
Started Jun 11 12:46:24 PM PDT 24
Finished Jun 11 12:46:27 PM PDT 24
Peak memory 207176 kb
Host smart-6d149f9e-1677-42ae-9d9a-99ff588f7c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621468240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.3621468240
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2375980774
Short name T618
Test name
Test status
Simulation time 23092123 ps
CPU time 0.71 seconds
Started Jun 11 12:46:15 PM PDT 24
Finished Jun 11 12:46:19 PM PDT 24
Peak memory 205864 kb
Host smart-9fc4f6cc-2a33-40bd-9389-6004ed418268
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375980774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2375980774
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.2424386703
Short name T286
Test name
Test status
Simulation time 9114372983 ps
CPU time 29.32 seconds
Started Jun 11 12:46:40 PM PDT 24
Finished Jun 11 12:47:12 PM PDT 24
Peak memory 233072 kb
Host smart-fccad160-5796-440e-bc77-e277f61bbdb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424386703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.2424386703
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.3699788986
Short name T60
Test name
Test status
Simulation time 13729780 ps
CPU time 0.72 seconds
Started Jun 11 12:46:15 PM PDT 24
Finished Jun 11 12:46:19 PM PDT 24
Peak memory 206052 kb
Host smart-d7748774-3227-4ddc-8200-9320b57850bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3699788986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
3699788986
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.3805448800
Short name T941
Test name
Test status
Simulation time 2594059005 ps
CPU time 7.92 seconds
Started Jun 11 12:46:10 PM PDT 24
Finished Jun 11 12:46:20 PM PDT 24
Peak memory 224916 kb
Host smart-b2bda1fa-3781-4c8c-bf15-9c8984fcb234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805448800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.3805448800
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.1205128383
Short name T573
Test name
Test status
Simulation time 39495549 ps
CPU time 0.8 seconds
Started Jun 11 12:46:26 PM PDT 24
Finished Jun 11 12:46:28 PM PDT 24
Peak memory 206816 kb
Host smart-c382c819-273f-4b2d-acf3-9e9ce609082f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205128383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.1205128383
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.3647198894
Short name T411
Test name
Test status
Simulation time 4595455510 ps
CPU time 62.78 seconds
Started Jun 11 12:46:22 PM PDT 24
Finished Jun 11 12:47:28 PM PDT 24
Peak memory 251864 kb
Host smart-ed2ec0f2-b4b2-421e-86fc-6aaa69504072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647198894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.3647198894
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.3456330322
Short name T26
Test name
Test status
Simulation time 10521355238 ps
CPU time 73.64 seconds
Started Jun 11 12:46:29 PM PDT 24
Finished Jun 11 12:47:45 PM PDT 24
Peak memory 224076 kb
Host smart-463a55e8-2b47-44c1-9760-4463d1497241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456330322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.3456330322
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_intercept.599071759
Short name T728
Test name
Test status
Simulation time 1743825750 ps
CPU time 7.6 seconds
Started Jun 11 12:46:13 PM PDT 24
Finished Jun 11 12:46:24 PM PDT 24
Peak memory 232952 kb
Host smart-ca9a5132-a693-4e85-8cfa-cce2ddb37f61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599071759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.599071759
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.2869742777
Short name T670
Test name
Test status
Simulation time 1743099320 ps
CPU time 11.14 seconds
Started Jun 11 12:46:16 PM PDT 24
Finished Jun 11 12:46:30 PM PDT 24
Peak memory 232928 kb
Host smart-4ca39daa-222c-47be-9fad-9767f0f60c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869742777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2869742777
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.313662628
Short name T152
Test name
Test status
Simulation time 5819815152 ps
CPU time 10.72 seconds
Started Jun 11 12:46:15 PM PDT 24
Finished Jun 11 12:46:29 PM PDT 24
Peak memory 228276 kb
Host smart-ee5564c8-c671-471d-aaa8-40a3ee1e733f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313662628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap
.313662628
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.2842344017
Short name T184
Test name
Test status
Simulation time 1225028959 ps
CPU time 5.42 seconds
Started Jun 11 12:46:29 PM PDT 24
Finished Jun 11 12:46:36 PM PDT 24
Peak memory 232996 kb
Host smart-ca7d2bef-7388-482d-9a21-6bf906bc59da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842344017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.2842344017
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.2066381199
Short name T850
Test name
Test status
Simulation time 5489686537 ps
CPU time 7.71 seconds
Started Jun 11 12:46:29 PM PDT 24
Finished Jun 11 12:46:39 PM PDT 24
Peak memory 222628 kb
Host smart-e0d27ec4-7888-4790-abe1-eeab723565a2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2066381199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.2066381199
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.1362800202
Short name T605
Test name
Test status
Simulation time 13377952311 ps
CPU time 140.18 seconds
Started Jun 11 12:46:29 PM PDT 24
Finished Jun 11 12:48:51 PM PDT 24
Peak memory 257556 kb
Host smart-521375f1-2ea7-460f-9dcb-4deab754f5d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362800202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.1362800202
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.2433755151
Short name T812
Test name
Test status
Simulation time 1570749854 ps
CPU time 8.97 seconds
Started Jun 11 12:46:31 PM PDT 24
Finished Jun 11 12:46:42 PM PDT 24
Peak memory 216804 kb
Host smart-2ab6248c-1482-41e8-b38a-f689b09ac60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2433755151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.2433755151
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.4059770271
Short name T702
Test name
Test status
Simulation time 1914575652 ps
CPU time 5.91 seconds
Started Jun 11 12:46:12 PM PDT 24
Finished Jun 11 12:46:20 PM PDT 24
Peak memory 216788 kb
Host smart-5c155ff6-b40d-4005-83e3-99fe77ed4f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059770271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.4059770271
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.1242892784
Short name T939
Test name
Test status
Simulation time 1142983853 ps
CPU time 5.92 seconds
Started Jun 11 12:46:16 PM PDT 24
Finished Jun 11 12:46:25 PM PDT 24
Peak memory 216540 kb
Host smart-1e31c27f-055d-43a6-8127-adc6ca10bc61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242892784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.1242892784
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.642046270
Short name T815
Test name
Test status
Simulation time 304809858 ps
CPU time 1.12 seconds
Started Jun 11 12:46:19 PM PDT 24
Finished Jun 11 12:46:24 PM PDT 24
Peak memory 207204 kb
Host smart-9da16bc5-4ab8-4392-80ea-eb17167dd7c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=642046270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.642046270
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.3334960150
Short name T904
Test name
Test status
Simulation time 300223123 ps
CPU time 3.99 seconds
Started Jun 11 12:46:10 PM PDT 24
Finished Jun 11 12:46:17 PM PDT 24
Peak memory 224980 kb
Host smart-9e4653f2-cbe7-44ec-983a-03945eebbccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334960150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3334960150
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.1811399180
Short name T363
Test name
Test status
Simulation time 30916127 ps
CPU time 0.69 seconds
Started Jun 11 12:46:30 PM PDT 24
Finished Jun 11 12:46:33 PM PDT 24
Peak memory 206104 kb
Host smart-afefce34-4ffb-4a26-969b-377e887b6917
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811399180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
1811399180
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.1283359824
Short name T564
Test name
Test status
Simulation time 1762392595 ps
CPU time 4.9 seconds
Started Jun 11 12:46:29 PM PDT 24
Finished Jun 11 12:46:35 PM PDT 24
Peak memory 232920 kb
Host smart-976e22ea-005c-4cc9-a916-283145daa0a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283359824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.1283359824
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.158359696
Short name T751
Test name
Test status
Simulation time 52106897 ps
CPU time 0.78 seconds
Started Jun 11 12:46:14 PM PDT 24
Finished Jun 11 12:46:18 PM PDT 24
Peak memory 206884 kb
Host smart-275fab30-1391-4546-a813-5640a7721164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158359696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.158359696
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.3573721413
Short name T448
Test name
Test status
Simulation time 135495997364 ps
CPU time 334.49 seconds
Started Jun 11 12:46:07 PM PDT 24
Finished Jun 11 12:51:43 PM PDT 24
Peak memory 257748 kb
Host smart-1c12be71-7ece-4b14-b2b6-845fafc93ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573721413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.3573721413
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.3987923510
Short name T239
Test name
Test status
Simulation time 48030064711 ps
CPU time 57.42 seconds
Started Jun 11 12:46:09 PM PDT 24
Finished Jun 11 12:47:09 PM PDT 24
Peak memory 234472 kb
Host smart-7e521832-cebd-4901-8ab1-a448e8269e01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987923510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.3987923510
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1321605179
Short name T298
Test name
Test status
Simulation time 650438532 ps
CPU time 10.87 seconds
Started Jun 11 12:46:16 PM PDT 24
Finished Jun 11 12:46:31 PM PDT 24
Peak memory 241092 kb
Host smart-f6a583ce-8c7a-4d89-9bda-92b8e5bc0a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321605179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1321605179
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.2374998050
Short name T689
Test name
Test status
Simulation time 938192481 ps
CPU time 4.04 seconds
Started Jun 11 12:46:16 PM PDT 24
Finished Jun 11 12:46:24 PM PDT 24
Peak memory 224692 kb
Host smart-b5fab4b3-9f87-4803-a4a0-c156cdd78761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374998050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2374998050
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.2772029483
Short name T265
Test name
Test status
Simulation time 1922315985 ps
CPU time 16.11 seconds
Started Jun 11 12:46:16 PM PDT 24
Finished Jun 11 12:46:35 PM PDT 24
Peak memory 250012 kb
Host smart-a344fdf7-0158-4aed-bcc4-d9a1a07f43ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772029483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.2772029483
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.1009225352
Short name T804
Test name
Test status
Simulation time 1862360982 ps
CPU time 5.25 seconds
Started Jun 11 12:46:15 PM PDT 24
Finished Jun 11 12:46:24 PM PDT 24
Peak memory 229472 kb
Host smart-c9d15be0-f8cb-4f21-8108-f742b7d29b5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009225352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.1009225352
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.3582622958
Short name T504
Test name
Test status
Simulation time 598645650 ps
CPU time 3.56 seconds
Started Jun 11 12:46:18 PM PDT 24
Finished Jun 11 12:46:25 PM PDT 24
Peak memory 227996 kb
Host smart-d8421d4e-f673-4d17-893f-891bcf85f3aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582622958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.3582622958
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.215446236
Short name T774
Test name
Test status
Simulation time 669399134 ps
CPU time 4.13 seconds
Started Jun 11 12:46:24 PM PDT 24
Finished Jun 11 12:46:31 PM PDT 24
Peak memory 223296 kb
Host smart-f59b2a92-6da8-45b8-b741-5ad724a7c858
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=215446236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dire
ct.215446236
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.3376022117
Short name T822
Test name
Test status
Simulation time 10053072248 ps
CPU time 13.08 seconds
Started Jun 11 12:46:14 PM PDT 24
Finished Jun 11 12:46:30 PM PDT 24
Peak memory 217036 kb
Host smart-ed8a1712-3aca-4389-8ff8-ab3ee9fb95b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376022117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.3376022117
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.2038470829
Short name T150
Test name
Test status
Simulation time 3775673873 ps
CPU time 6.84 seconds
Started Jun 11 12:46:10 PM PDT 24
Finished Jun 11 12:46:19 PM PDT 24
Peak memory 216696 kb
Host smart-6c3bb049-844e-4508-9927-9cfe5e04bd4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038470829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.2038470829
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.1499759536
Short name T730
Test name
Test status
Simulation time 95935210 ps
CPU time 1.07 seconds
Started Jun 11 12:46:17 PM PDT 24
Finished Jun 11 12:46:22 PM PDT 24
Peak memory 207356 kb
Host smart-593ac92d-65f6-4eca-aa7c-9b3e3e3435e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499759536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1499759536
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.1840657644
Short name T341
Test name
Test status
Simulation time 57956784 ps
CPU time 0.72 seconds
Started Jun 11 12:46:29 PM PDT 24
Finished Jun 11 12:46:31 PM PDT 24
Peak memory 206168 kb
Host smart-e9efe056-ccb9-406e-b2cb-75f938f84ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840657644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.1840657644
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.4079655239
Short name T43
Test name
Test status
Simulation time 168036621 ps
CPU time 2.48 seconds
Started Jun 11 12:46:21 PM PDT 24
Finished Jun 11 12:46:27 PM PDT 24
Peak memory 224704 kb
Host smart-0cf40dda-6728-4b70-8e48-55b45ee17276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079655239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.4079655239
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.2070832796
Short name T416
Test name
Test status
Simulation time 27200529 ps
CPU time 0.75 seconds
Started Jun 11 12:46:16 PM PDT 24
Finished Jun 11 12:46:20 PM PDT 24
Peak memory 206036 kb
Host smart-28b611b6-674a-4156-b6c3-4e56d2956712
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070832796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
2070832796
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.3551738353
Short name T512
Test name
Test status
Simulation time 217338660 ps
CPU time 3.71 seconds
Started Jun 11 12:46:18 PM PDT 24
Finished Jun 11 12:46:26 PM PDT 24
Peak memory 232916 kb
Host smart-48b7b2ca-c6ce-4fac-aa62-88684ed50efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551738353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.3551738353
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.981371558
Short name T599
Test name
Test status
Simulation time 90635324 ps
CPU time 0.82 seconds
Started Jun 11 12:46:30 PM PDT 24
Finished Jun 11 12:46:33 PM PDT 24
Peak memory 207192 kb
Host smart-c2b42721-824c-491b-9da9-13a3d76ec97a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981371558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.981371558
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.1933243469
Short name T486
Test name
Test status
Simulation time 160327555445 ps
CPU time 129.77 seconds
Started Jun 11 12:46:24 PM PDT 24
Finished Jun 11 12:48:37 PM PDT 24
Peak memory 249580 kb
Host smart-e8c3277b-63a9-4dd3-8931-c68de5bf2557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933243469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1933243469
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.694539318
Short name T678
Test name
Test status
Simulation time 46889257047 ps
CPU time 87.37 seconds
Started Jun 11 12:46:23 PM PDT 24
Finished Jun 11 12:47:54 PM PDT 24
Peak memory 250628 kb
Host smart-8644787e-9a9f-4697-9af1-5db45eda253e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694539318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle
.694539318
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.3735805441
Short name T913
Test name
Test status
Simulation time 3735565962 ps
CPU time 14.66 seconds
Started Jun 11 12:46:20 PM PDT 24
Finished Jun 11 12:46:38 PM PDT 24
Peak memory 235916 kb
Host smart-58f8ce5f-00af-4e39-ad42-a66c4a0f2ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735805441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.3735805441
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.3663933828
Short name T503
Test name
Test status
Simulation time 2299267669 ps
CPU time 21.92 seconds
Started Jun 11 12:46:38 PM PDT 24
Finished Jun 11 12:47:03 PM PDT 24
Peak memory 224820 kb
Host smart-8d0e077f-0a71-4ed7-a1f6-f2f06033a241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663933828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.3663933828
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.575534579
Short name T843
Test name
Test status
Simulation time 7109816075 ps
CPU time 60.33 seconds
Started Jun 11 12:46:14 PM PDT 24
Finished Jun 11 12:47:18 PM PDT 24
Peak memory 234724 kb
Host smart-933b0a77-911a-46e0-8ee3-b4f4883f5ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575534579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.575534579
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.1713842408
Short name T458
Test name
Test status
Simulation time 54369098687 ps
CPU time 20.57 seconds
Started Jun 11 12:46:13 PM PDT 24
Finished Jun 11 12:46:37 PM PDT 24
Peak memory 224900 kb
Host smart-f70332da-e71b-4dff-b8a9-2be13a0881b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713842408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.1713842408
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.549422802
Short name T515
Test name
Test status
Simulation time 5684091992 ps
CPU time 8.94 seconds
Started Jun 11 12:46:11 PM PDT 24
Finished Jun 11 12:46:23 PM PDT 24
Peak memory 224800 kb
Host smart-a5f12579-c875-4e51-918b-fb216a3fe5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549422802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.549422802
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.3230819553
Short name T852
Test name
Test status
Simulation time 349539448 ps
CPU time 3.71 seconds
Started Jun 11 12:46:30 PM PDT 24
Finished Jun 11 12:46:35 PM PDT 24
Peak memory 218980 kb
Host smart-d5efc501-98fa-4aaf-8afd-2fe2f1240957
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3230819553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.3230819553
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.2457658092
Short name T127
Test name
Test status
Simulation time 56937686901 ps
CPU time 222.8 seconds
Started Jun 11 12:46:22 PM PDT 24
Finished Jun 11 12:50:08 PM PDT 24
Peak memory 269188 kb
Host smart-09ebefad-3f25-4a24-8f3e-4d49098ffa48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457658092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.2457658092
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.2327959359
Short name T311
Test name
Test status
Simulation time 805011414 ps
CPU time 3.37 seconds
Started Jun 11 12:46:21 PM PDT 24
Finished Jun 11 12:46:28 PM PDT 24
Peak memory 216904 kb
Host smart-4c8faa96-184c-46ac-9507-23350c27dbcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327959359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.2327959359
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3741637848
Short name T768
Test name
Test status
Simulation time 1922787145 ps
CPU time 3.35 seconds
Started Jun 11 12:46:18 PM PDT 24
Finished Jun 11 12:46:25 PM PDT 24
Peak memory 216548 kb
Host smart-a0926e9b-c1f6-44bf-8911-edfff16e664b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741637848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3741637848
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.74362344
Short name T382
Test name
Test status
Simulation time 17315766 ps
CPU time 0.7 seconds
Started Jun 11 12:46:21 PM PDT 24
Finished Jun 11 12:46:25 PM PDT 24
Peak memory 205892 kb
Host smart-afbaf581-da76-4b1f-9caa-e13e03b81abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74362344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.74362344
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.2922550406
Short name T357
Test name
Test status
Simulation time 21061933 ps
CPU time 0.78 seconds
Started Jun 11 12:46:16 PM PDT 24
Finished Jun 11 12:46:20 PM PDT 24
Peak memory 206160 kb
Host smart-5a9d05cf-beea-409a-b158-0d61e1ce7410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922550406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.2922550406
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.2894662111
Short name T698
Test name
Test status
Simulation time 27912109811 ps
CPU time 27.14 seconds
Started Jun 11 12:46:29 PM PDT 24
Finished Jun 11 12:46:58 PM PDT 24
Peak memory 234036 kb
Host smart-7498a431-5424-4d33-b8d4-0b8f5fa4d973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894662111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.2894662111
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.3902276789
Short name T944
Test name
Test status
Simulation time 42992400 ps
CPU time 0.72 seconds
Started Jun 11 12:46:21 PM PDT 24
Finished Jun 11 12:46:26 PM PDT 24
Peak memory 205192 kb
Host smart-e79bd8de-a755-4f28-9973-9293c0574867
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902276789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
3902276789
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.1623544522
Short name T931
Test name
Test status
Simulation time 94654525 ps
CPU time 2.19 seconds
Started Jun 11 12:46:35 PM PDT 24
Finished Jun 11 12:46:39 PM PDT 24
Peak memory 232872 kb
Host smart-c0e4ee8b-d42e-454b-ace7-c223ad3a5845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623544522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.1623544522
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.3114032084
Short name T514
Test name
Test status
Simulation time 45759551 ps
CPU time 0.75 seconds
Started Jun 11 12:46:24 PM PDT 24
Finished Jun 11 12:46:28 PM PDT 24
Peak memory 205732 kb
Host smart-6023c3c8-2996-43c5-98ce-8ecba2f7238e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114032084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3114032084
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.1450485514
Short name T217
Test name
Test status
Simulation time 3235104244 ps
CPU time 23.33 seconds
Started Jun 11 12:46:23 PM PDT 24
Finished Jun 11 12:46:49 PM PDT 24
Peak memory 236960 kb
Host smart-20e13d5c-0cbd-4360-ab96-3b2feaa8f182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450485514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.1450485514
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.3775590761
Short name T11
Test name
Test status
Simulation time 17093622804 ps
CPU time 138.77 seconds
Started Jun 11 12:46:21 PM PDT 24
Finished Jun 11 12:48:44 PM PDT 24
Peak memory 250472 kb
Host smart-ef6f5850-3bd0-430a-b524-883b9a5c9d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775590761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.3775590761
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.1969229789
Short name T585
Test name
Test status
Simulation time 13175466271 ps
CPU time 100.13 seconds
Started Jun 11 12:46:14 PM PDT 24
Finished Jun 11 12:47:57 PM PDT 24
Peak memory 241348 kb
Host smart-08f381a6-2aaf-4add-be06-6c6dff3e9ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969229789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.1969229789
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.889254152
Short name T889
Test name
Test status
Simulation time 3970678716 ps
CPU time 39.06 seconds
Started Jun 11 12:46:20 PM PDT 24
Finished Jun 11 12:47:03 PM PDT 24
Peak memory 241044 kb
Host smart-b0f70d5c-6922-4851-ad21-48d46e12c44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889254152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.889254152
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.1530124071
Short name T417
Test name
Test status
Simulation time 68927549 ps
CPU time 2.65 seconds
Started Jun 11 12:46:11 PM PDT 24
Finished Jun 11 12:46:16 PM PDT 24
Peak memory 232976 kb
Host smart-78f1224d-de9a-4d73-8d6c-8ebc94e6fc09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530124071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.1530124071
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.1887455931
Short name T880
Test name
Test status
Simulation time 154559751952 ps
CPU time 91.31 seconds
Started Jun 11 12:46:32 PM PDT 24
Finished Jun 11 12:48:07 PM PDT 24
Peak memory 240744 kb
Host smart-2639b7b9-5e96-431d-aa93-6cb56d5fcec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887455931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1887455931
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3198575830
Short name T903
Test name
Test status
Simulation time 21798602016 ps
CPU time 15.83 seconds
Started Jun 11 12:46:28 PM PDT 24
Finished Jun 11 12:46:45 PM PDT 24
Peak memory 233044 kb
Host smart-f9ead0c1-f421-475c-a5e1-1efb86783ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198575830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.3198575830
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.233812628
Short name T463
Test name
Test status
Simulation time 11354094746 ps
CPU time 30.86 seconds
Started Jun 11 12:46:15 PM PDT 24
Finished Jun 11 12:46:50 PM PDT 24
Peak memory 233092 kb
Host smart-bdb009a2-0b13-42d5-87d0-b5871d628ea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233812628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.233812628
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2930644246
Short name T650
Test name
Test status
Simulation time 1023254222 ps
CPU time 7.52 seconds
Started Jun 11 12:46:28 PM PDT 24
Finished Jun 11 12:46:37 PM PDT 24
Peak memory 219064 kb
Host smart-231197c4-2b31-4a8a-a42d-2234b584f365
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2930644246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2930644246
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.1893938618
Short name T914
Test name
Test status
Simulation time 43855906052 ps
CPU time 354.85 seconds
Started Jun 11 12:46:31 PM PDT 24
Finished Jun 11 12:52:28 PM PDT 24
Peak memory 250564 kb
Host smart-48fe2d15-6ffe-40d1-8387-ce0775f5c005
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893938618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.1893938618
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.226375182
Short name T82
Test name
Test status
Simulation time 3175591346 ps
CPU time 17.15 seconds
Started Jun 11 12:46:24 PM PDT 24
Finished Jun 11 12:46:44 PM PDT 24
Peak memory 216708 kb
Host smart-831a64a4-1513-4247-b17d-1249fbb276f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226375182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.226375182
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1779315841
Short name T366
Test name
Test status
Simulation time 1504767053 ps
CPU time 2.77 seconds
Started Jun 11 12:46:28 PM PDT 24
Finished Jun 11 12:46:32 PM PDT 24
Peak memory 216432 kb
Host smart-732aa2bc-0d76-4b53-8ebf-4035c2e5b516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779315841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1779315841
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.776880973
Short name T367
Test name
Test status
Simulation time 35816422 ps
CPU time 1.07 seconds
Started Jun 11 12:46:31 PM PDT 24
Finished Jun 11 12:46:34 PM PDT 24
Peak memory 207552 kb
Host smart-417655cf-a60b-4aa6-8a67-b6c1e8eda8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776880973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.776880973
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.3583731239
Short name T600
Test name
Test status
Simulation time 11398784 ps
CPU time 0.73 seconds
Started Jun 11 12:46:22 PM PDT 24
Finished Jun 11 12:46:26 PM PDT 24
Peak memory 205924 kb
Host smart-a3519485-dde7-4b5b-93a6-70b483a74741
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583731239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.3583731239
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.808541517
Short name T919
Test name
Test status
Simulation time 16183912157 ps
CPU time 22.94 seconds
Started Jun 11 12:46:20 PM PDT 24
Finished Jun 11 12:46:46 PM PDT 24
Peak memory 233128 kb
Host smart-680168b3-0234-4ca9-94c4-1349a307842a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808541517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.808541517
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3602118412
Short name T658
Test name
Test status
Simulation time 28836246 ps
CPU time 0.69 seconds
Started Jun 11 12:46:19 PM PDT 24
Finished Jun 11 12:46:24 PM PDT 24
Peak memory 205164 kb
Host smart-e792395e-680a-4d5c-a81b-a675ceff5ccd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602118412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3602118412
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.1506249628
Short name T428
Test name
Test status
Simulation time 324143968 ps
CPU time 5.62 seconds
Started Jun 11 12:46:30 PM PDT 24
Finished Jun 11 12:46:38 PM PDT 24
Peak memory 233008 kb
Host smart-e944b50f-aa8a-48e6-80e8-b890d8cedb4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506249628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.1506249628
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.2127538695
Short name T321
Test name
Test status
Simulation time 66176647 ps
CPU time 0.78 seconds
Started Jun 11 12:46:32 PM PDT 24
Finished Jun 11 12:46:36 PM PDT 24
Peak memory 206820 kb
Host smart-f0d82415-0a68-44f3-a1aa-5cead83835f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127538695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.2127538695
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.3202170943
Short name T244
Test name
Test status
Simulation time 3620326595 ps
CPU time 43.34 seconds
Started Jun 11 12:46:23 PM PDT 24
Finished Jun 11 12:47:10 PM PDT 24
Peak memory 251904 kb
Host smart-7838f4a0-4aac-4f7d-85b6-f8c5351e92e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202170943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.3202170943
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.2413281205
Short name T27
Test name
Test status
Simulation time 33170556151 ps
CPU time 280.18 seconds
Started Jun 11 12:46:22 PM PDT 24
Finished Jun 11 12:51:06 PM PDT 24
Peak memory 254340 kb
Host smart-bc2b2a1e-3816-4e12-bf24-368a724a2102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413281205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.2413281205
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.599053531
Short name T441
Test name
Test status
Simulation time 28672123944 ps
CPU time 208.58 seconds
Started Jun 11 12:46:34 PM PDT 24
Finished Jun 11 12:50:05 PM PDT 24
Peak memory 250808 kb
Host smart-9d2e7f90-c87d-4130-a54c-3b0b7372bd31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599053531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle
.599053531
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.2415661773
Short name T301
Test name
Test status
Simulation time 1117932115 ps
CPU time 13.22 seconds
Started Jun 11 12:46:21 PM PDT 24
Finished Jun 11 12:46:38 PM PDT 24
Peak memory 224800 kb
Host smart-940b3191-25a2-4dcb-8e86-ef63c6b7ea7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415661773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.2415661773
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.421335386
Short name T464
Test name
Test status
Simulation time 1238136970 ps
CPU time 5.44 seconds
Started Jun 11 12:46:31 PM PDT 24
Finished Jun 11 12:46:39 PM PDT 24
Peak memory 232960 kb
Host smart-9dd0f4c5-2756-4be7-9ebc-3f8515abbcb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421335386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.421335386
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.3702394044
Short name T125
Test name
Test status
Simulation time 6887192178 ps
CPU time 18.89 seconds
Started Jun 11 12:46:21 PM PDT 24
Finished Jun 11 12:46:44 PM PDT 24
Peak memory 233084 kb
Host smart-caa20944-1749-4574-9b09-4876afee3cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3702394044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.3702394044
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.3082131889
Short name T290
Test name
Test status
Simulation time 25147305880 ps
CPU time 16.45 seconds
Started Jun 11 12:46:30 PM PDT 24
Finished Jun 11 12:46:49 PM PDT 24
Peak memory 233048 kb
Host smart-9629ed83-f41e-4735-9c65-5032ed9cab1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082131889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.3082131889
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.2356311475
Short name T277
Test name
Test status
Simulation time 11230651985 ps
CPU time 14.84 seconds
Started Jun 11 12:46:22 PM PDT 24
Finished Jun 11 12:46:41 PM PDT 24
Peak memory 232992 kb
Host smart-cd949e3a-7261-473c-9afa-001922ef90cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356311475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2356311475
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.2351413915
Short name T472
Test name
Test status
Simulation time 1127612447 ps
CPU time 3.93 seconds
Started Jun 11 12:46:38 PM PDT 24
Finished Jun 11 12:46:45 PM PDT 24
Peak memory 220280 kb
Host smart-bf2f9883-d4b9-4d54-9385-414c68c11719
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2351413915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.2351413915
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.21826216
Short name T19
Test name
Test status
Simulation time 1100167431 ps
CPU time 1.07 seconds
Started Jun 11 12:46:20 PM PDT 24
Finished Jun 11 12:46:25 PM PDT 24
Peak memory 207008 kb
Host smart-0f4520e0-49e3-4c50-9a12-fa25f78ece04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21826216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stress
_all.21826216
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.4271849583
Short name T345
Test name
Test status
Simulation time 5020678963 ps
CPU time 18.81 seconds
Started Jun 11 12:46:21 PM PDT 24
Finished Jun 11 12:46:44 PM PDT 24
Peak memory 216720 kb
Host smart-baaceea1-1c9a-41e3-836c-444346fb06ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271849583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.4271849583
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.2646581292
Short name T781
Test name
Test status
Simulation time 9783608430 ps
CPU time 5.36 seconds
Started Jun 11 12:46:32 PM PDT 24
Finished Jun 11 12:46:40 PM PDT 24
Peak memory 216736 kb
Host smart-1743cac0-4046-4926-8599-98b45995d8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646581292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.2646581292
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.1082128690
Short name T613
Test name
Test status
Simulation time 77727281 ps
CPU time 1.25 seconds
Started Jun 11 12:46:29 PM PDT 24
Finished Jun 11 12:46:31 PM PDT 24
Peak memory 216396 kb
Host smart-9e511350-cb4b-40ac-a2b9-9764cbb436f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082128690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.1082128690
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.3969822761
Short name T456
Test name
Test status
Simulation time 476809761 ps
CPU time 0.85 seconds
Started Jun 11 12:46:19 PM PDT 24
Finished Jun 11 12:46:24 PM PDT 24
Peak memory 206092 kb
Host smart-276eca3e-9751-4b89-8586-3c9c65e6f306
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969822761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3969822761
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.3499450365
Short name T893
Test name
Test status
Simulation time 648884385 ps
CPU time 5.18 seconds
Started Jun 11 12:46:27 PM PDT 24
Finished Jun 11 12:46:34 PM PDT 24
Peak memory 224732 kb
Host smart-1b5912f3-2aa4-457d-bce0-43bcfce3b406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499450365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.3499450365
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.2895446899
Short name T794
Test name
Test status
Simulation time 33151712 ps
CPU time 0.71 seconds
Started Jun 11 12:46:20 PM PDT 24
Finished Jun 11 12:46:24 PM PDT 24
Peak memory 205108 kb
Host smart-fe96f129-afe3-4ea7-adc7-f85128d609ea
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895446899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
2895446899
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.1513468286
Short name T837
Test name
Test status
Simulation time 33431543 ps
CPU time 2.62 seconds
Started Jun 11 12:46:26 PM PDT 24
Finished Jun 11 12:46:31 PM PDT 24
Peak memory 232924 kb
Host smart-824bc251-a753-4bc8-bc66-fdff89969340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513468286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.1513468286
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.3936871102
Short name T770
Test name
Test status
Simulation time 56344719 ps
CPU time 0.76 seconds
Started Jun 11 12:46:31 PM PDT 24
Finished Jun 11 12:46:35 PM PDT 24
Peak memory 205836 kb
Host smart-4f2e9e8d-ab8a-4e69-875d-624224c2ae86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936871102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.3936871102
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.3068525169
Short name T835
Test name
Test status
Simulation time 92571922220 ps
CPU time 87.49 seconds
Started Jun 11 12:46:41 PM PDT 24
Finished Jun 11 12:48:11 PM PDT 24
Peak memory 241340 kb
Host smart-5575b757-21d9-467d-94af-b94a05eb5e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068525169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.3068525169
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.3262336731
Short name T306
Test name
Test status
Simulation time 509234773 ps
CPU time 4.99 seconds
Started Jun 11 12:46:36 PM PDT 24
Finished Jun 11 12:46:43 PM PDT 24
Peak memory 223080 kb
Host smart-1c748e27-3fe8-466a-acaa-b9438a9760ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262336731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.3262336731
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.3199907840
Short name T385
Test name
Test status
Simulation time 3382141871 ps
CPU time 9.43 seconds
Started Jun 11 12:46:28 PM PDT 24
Finished Jun 11 12:46:39 PM PDT 24
Peak memory 224876 kb
Host smart-86061ac4-e70e-4164-934b-dcca8e09e6d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199907840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.3199907840
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.2799662431
Short name T766
Test name
Test status
Simulation time 67858748406 ps
CPU time 119.97 seconds
Started Jun 11 12:46:15 PM PDT 24
Finished Jun 11 12:48:18 PM PDT 24
Peak memory 257040 kb
Host smart-db256b34-d0eb-4acf-b0b0-abb0e5a605ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799662431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.2799662431
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.2889396149
Short name T182
Test name
Test status
Simulation time 24066498709 ps
CPU time 27.32 seconds
Started Jun 11 12:46:17 PM PDT 24
Finished Jun 11 12:46:49 PM PDT 24
Peak memory 240772 kb
Host smart-d034858d-85ef-41b3-9197-ef432d81ce89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889396149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.2889396149
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.4073089099
Short name T93
Test name
Test status
Simulation time 2095882552 ps
CPU time 9.81 seconds
Started Jun 11 12:46:31 PM PDT 24
Finished Jun 11 12:46:43 PM PDT 24
Peak memory 241116 kb
Host smart-6d6f2573-0271-41ce-84c3-dd15a7acd6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073089099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.4073089099
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.3742448026
Short name T552
Test name
Test status
Simulation time 1531041702 ps
CPU time 11.11 seconds
Started Jun 11 12:46:20 PM PDT 24
Finished Jun 11 12:46:35 PM PDT 24
Peak memory 220548 kb
Host smart-d2b5b806-3116-44dd-b0f9-6bb2bf19cf4d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3742448026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.3742448026
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.1857883534
Short name T641
Test name
Test status
Simulation time 3778232687 ps
CPU time 24.6 seconds
Started Jun 11 12:46:25 PM PDT 24
Finished Jun 11 12:46:52 PM PDT 24
Peak memory 216692 kb
Host smart-c4db7c6a-2ee9-4a96-895e-673d01c5d60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1857883534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.1857883534
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.835808791
Short name T713
Test name
Test status
Simulation time 4908416079 ps
CPU time 7.2 seconds
Started Jun 11 12:46:23 PM PDT 24
Finished Jun 11 12:46:33 PM PDT 24
Peak memory 216620 kb
Host smart-050ce215-b891-42dc-8deb-635ac7e9590f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=835808791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.835808791
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.893914765
Short name T154
Test name
Test status
Simulation time 103311160 ps
CPU time 1.01 seconds
Started Jun 11 12:46:25 PM PDT 24
Finished Jun 11 12:46:28 PM PDT 24
Peak memory 207636 kb
Host smart-759f5574-755f-4d42-b904-d27da9fbbfea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893914765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.893914765
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2127230137
Short name T773
Test name
Test status
Simulation time 178120795 ps
CPU time 0.92 seconds
Started Jun 11 12:46:23 PM PDT 24
Finished Jun 11 12:46:27 PM PDT 24
Peak memory 206180 kb
Host smart-b2a92443-55f8-4815-af97-6509a4a20161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127230137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2127230137
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.2803789527
Short name T577
Test name
Test status
Simulation time 358060824 ps
CPU time 3.2 seconds
Started Jun 11 12:46:24 PM PDT 24
Finished Jun 11 12:46:30 PM PDT 24
Peak memory 224700 kb
Host smart-3993a3bd-9244-44b1-a017-04e212c2ed4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803789527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.2803789527
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.2804473499
Short name T495
Test name
Test status
Simulation time 12679222 ps
CPU time 0.78 seconds
Started Jun 11 12:46:28 PM PDT 24
Finished Jun 11 12:46:31 PM PDT 24
Peak memory 205056 kb
Host smart-259e8280-25ce-4606-81d0-6f7c48d1ec66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804473499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
2804473499
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.698955842
Short name T576
Test name
Test status
Simulation time 1152602585 ps
CPU time 4.76 seconds
Started Jun 11 12:46:24 PM PDT 24
Finished Jun 11 12:46:32 PM PDT 24
Peak memory 232780 kb
Host smart-aa3ddfe8-59e9-437c-beb4-68340c28bccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698955842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.698955842
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.80930931
Short name T402
Test name
Test status
Simulation time 19146422 ps
CPU time 0.74 seconds
Started Jun 11 12:46:26 PM PDT 24
Finished Jun 11 12:46:29 PM PDT 24
Peak memory 205800 kb
Host smart-d88bbb91-7478-4ede-b160-ed4624003b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80930931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.80930931
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.3424320264
Short name T864
Test name
Test status
Simulation time 7880861252 ps
CPU time 34.67 seconds
Started Jun 11 12:46:19 PM PDT 24
Finished Jun 11 12:46:58 PM PDT 24
Peak memory 255960 kb
Host smart-7e01b852-25c1-453e-8c68-5f744d19b826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424320264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.3424320264
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.3150174637
Short name T186
Test name
Test status
Simulation time 3197680521 ps
CPU time 13.56 seconds
Started Jun 11 12:46:44 PM PDT 24
Finished Jun 11 12:47:00 PM PDT 24
Peak memory 241336 kb
Host smart-e68948eb-57f4-45a4-a9bc-30a39940883b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150174637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.3150174637
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.1835564489
Short name T920
Test name
Test status
Simulation time 1467065009 ps
CPU time 11.29 seconds
Started Jun 11 12:46:33 PM PDT 24
Finished Jun 11 12:46:47 PM PDT 24
Peak memory 241088 kb
Host smart-0eb0f4e7-7f62-478e-888c-91f37cd9e88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835564489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.1835564489
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.4218757214
Short name T915
Test name
Test status
Simulation time 4627585478 ps
CPU time 11.13 seconds
Started Jun 11 12:46:36 PM PDT 24
Finished Jun 11 12:46:50 PM PDT 24
Peak memory 224816 kb
Host smart-e62925ae-1e43-4def-8c89-2bbd1980f44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218757214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.4218757214
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.1432711949
Short name T199
Test name
Test status
Simulation time 11429488178 ps
CPU time 28.35 seconds
Started Jun 11 12:46:36 PM PDT 24
Finished Jun 11 12:47:07 PM PDT 24
Peak memory 224836 kb
Host smart-eb70d413-890b-4614-9444-199ff98968ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432711949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.1432711949
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3780912732
Short name T775
Test name
Test status
Simulation time 17058709451 ps
CPU time 7.96 seconds
Started Jun 11 12:46:32 PM PDT 24
Finished Jun 11 12:46:42 PM PDT 24
Peak memory 224852 kb
Host smart-ea0f40d0-0e6b-45eb-aa81-5fe25d1b494a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780912732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3780912732
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.1171321874
Short name T165
Test name
Test status
Simulation time 6976184318 ps
CPU time 20.45 seconds
Started Jun 11 12:46:21 PM PDT 24
Finished Jun 11 12:46:45 PM PDT 24
Peak memory 233060 kb
Host smart-d8a190d5-024d-40ed-be5e-ae260a56cee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171321874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.1171321874
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.313436286
Short name T140
Test name
Test status
Simulation time 620821203 ps
CPU time 7.79 seconds
Started Jun 11 12:46:35 PM PDT 24
Finished Jun 11 12:46:46 PM PDT 24
Peak memory 223280 kb
Host smart-7b6cf5f1-5d22-4866-942b-240ad4c5d0ba
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=313436286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dire
ct.313436286
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.841232485
Short name T71
Test name
Test status
Simulation time 3999988671 ps
CPU time 25.64 seconds
Started Jun 11 12:46:23 PM PDT 24
Finished Jun 11 12:46:52 PM PDT 24
Peak memory 216656 kb
Host smart-7539eb4d-4ee1-4685-b772-613414cee679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841232485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.841232485
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.1957888891
Short name T809
Test name
Test status
Simulation time 1325071497 ps
CPU time 6.65 seconds
Started Jun 11 12:46:27 PM PDT 24
Finished Jun 11 12:46:35 PM PDT 24
Peak memory 216552 kb
Host smart-e377f734-2e22-4fce-b02c-f5fcf0ef0e74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957888891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1957888891
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.1260702078
Short name T358
Test name
Test status
Simulation time 363109005 ps
CPU time 2.91 seconds
Started Jun 11 12:46:31 PM PDT 24
Finished Jun 11 12:46:36 PM PDT 24
Peak memory 216556 kb
Host smart-83bd6205-f963-481c-8cf9-6f758eb95c7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260702078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.1260702078
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.4051488284
Short name T506
Test name
Test status
Simulation time 100392566 ps
CPU time 1.02 seconds
Started Jun 11 12:46:21 PM PDT 24
Finished Jun 11 12:46:26 PM PDT 24
Peak memory 207160 kb
Host smart-8f118151-4dd7-4acd-8b48-033724ac11b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051488284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.4051488284
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.2468851702
Short name T519
Test name
Test status
Simulation time 945067946 ps
CPU time 6.2 seconds
Started Jun 11 12:46:33 PM PDT 24
Finished Jun 11 12:46:42 PM PDT 24
Peak memory 241124 kb
Host smart-876d5021-dc12-4a7f-9636-7c202073a84a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2468851702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2468851702
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.3054212804
Short name T449
Test name
Test status
Simulation time 39492035 ps
CPU time 0.74 seconds
Started Jun 11 12:46:32 PM PDT 24
Finished Jun 11 12:46:35 PM PDT 24
Peak memory 205688 kb
Host smart-202f3dc3-d6e4-499d-a29e-3276b90b1ec3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054212804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
3054212804
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.1899505314
Short name T489
Test name
Test status
Simulation time 331592004 ps
CPU time 2.82 seconds
Started Jun 11 12:46:32 PM PDT 24
Finished Jun 11 12:46:37 PM PDT 24
Peak memory 233008 kb
Host smart-ad4de7b5-a832-4333-9fec-21516972b61a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899505314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1899505314
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.3759120880
Short name T872
Test name
Test status
Simulation time 58651194 ps
CPU time 0.81 seconds
Started Jun 11 12:46:25 PM PDT 24
Finished Jun 11 12:46:28 PM PDT 24
Peak memory 205720 kb
Host smart-17b6e811-bc26-4184-a456-104c3cb31a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759120880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3759120880
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.2987334
Short name T778
Test name
Test status
Simulation time 258912929200 ps
CPU time 312.14 seconds
Started Jun 11 12:46:32 PM PDT 24
Finished Jun 11 12:51:47 PM PDT 24
Peak memory 252776 kb
Host smart-75f2eae8-8b6b-4fb3-8503-828c12e9a983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.2987334
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.3736592002
Short name T900
Test name
Test status
Simulation time 4148299167 ps
CPU time 62.34 seconds
Started Jun 11 12:46:30 PM PDT 24
Finished Jun 11 12:47:34 PM PDT 24
Peak memory 249564 kb
Host smart-403f0821-e16b-4e41-8671-01cd09244244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736592002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.3736592002
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.3350271520
Short name T929
Test name
Test status
Simulation time 488188026 ps
CPU time 2.59 seconds
Started Jun 11 12:46:32 PM PDT 24
Finished Jun 11 12:46:37 PM PDT 24
Peak memory 233000 kb
Host smart-4205b2c7-84c6-4151-a9df-7a6e1e4bd3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350271520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.3350271520
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.4026865787
Short name T517
Test name
Test status
Simulation time 187893244 ps
CPU time 5.02 seconds
Started Jun 11 12:46:32 PM PDT 24
Finished Jun 11 12:46:40 PM PDT 24
Peak memory 232840 kb
Host smart-f2ea7058-daae-4638-8ee3-e06eb3b47189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026865787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.4026865787
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.3473193022
Short name T173
Test name
Test status
Simulation time 903431682 ps
CPU time 14.06 seconds
Started Jun 11 12:46:30 PM PDT 24
Finished Jun 11 12:46:46 PM PDT 24
Peak memory 233004 kb
Host smart-b1199a70-5ea4-4bb5-a6b8-387e3889affa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473193022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.3473193022
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.185382538
Short name T634
Test name
Test status
Simulation time 7464351286 ps
CPU time 12.49 seconds
Started Jun 11 12:46:48 PM PDT 24
Finished Jun 11 12:47:03 PM PDT 24
Peak memory 233032 kb
Host smart-1fa66456-d341-4d6f-99c6-eae45fcbcf5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185382538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap
.185382538
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.3343175915
Short name T910
Test name
Test status
Simulation time 365829416 ps
CPU time 6.21 seconds
Started Jun 11 12:46:24 PM PDT 24
Finished Jun 11 12:46:33 PM PDT 24
Peak memory 232896 kb
Host smart-25fe8c10-9dbd-4391-b94c-e72513e9729a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343175915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.3343175915
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.903425004
Short name T138
Test name
Test status
Simulation time 1724715386 ps
CPU time 20.26 seconds
Started Jun 11 12:46:28 PM PDT 24
Finished Jun 11 12:46:49 PM PDT 24
Peak memory 220108 kb
Host smart-28ec2fc0-6dbf-4226-a0ae-715ea8a91f8b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=903425004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dire
ct.903425004
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.439089735
Short name T148
Test name
Test status
Simulation time 145202605 ps
CPU time 0.9 seconds
Started Jun 11 12:46:49 PM PDT 24
Finished Jun 11 12:46:52 PM PDT 24
Peak memory 206920 kb
Host smart-4dd8bc49-a430-431b-8c2a-04240d56ff17
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439089735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stres
s_all.439089735
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.3595284820
Short name T757
Test name
Test status
Simulation time 1812356722 ps
CPU time 25.04 seconds
Started Jun 11 12:46:24 PM PDT 24
Finished Jun 11 12:46:52 PM PDT 24
Peak memory 219668 kb
Host smart-6ba87265-50a7-417b-b55e-f757106e1e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595284820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.3595284820
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.2321972442
Short name T334
Test name
Test status
Simulation time 14812436 ps
CPU time 0.71 seconds
Started Jun 11 12:46:31 PM PDT 24
Finished Jun 11 12:46:34 PM PDT 24
Peak memory 205868 kb
Host smart-1931b508-2c02-45a9-a2d7-655fa8b7dfdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321972442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.2321972442
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.3228300377
Short name T853
Test name
Test status
Simulation time 72807633 ps
CPU time 0.76 seconds
Started Jun 11 12:46:33 PM PDT 24
Finished Jun 11 12:46:41 PM PDT 24
Peak memory 206040 kb
Host smart-24743f03-fe9f-4dc3-9c29-1b90d3fe064d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228300377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.3228300377
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.588376346
Short name T323
Test name
Test status
Simulation time 101663009 ps
CPU time 0.76 seconds
Started Jun 11 12:46:31 PM PDT 24
Finished Jun 11 12:46:34 PM PDT 24
Peak memory 206172 kb
Host smart-a4fcdd15-40b9-4f48-a5ea-005045a91459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588376346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.588376346
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.376333576
Short name T185
Test name
Test status
Simulation time 34890311133 ps
CPU time 8.14 seconds
Started Jun 11 12:46:32 PM PDT 24
Finished Jun 11 12:46:42 PM PDT 24
Peak memory 233076 kb
Host smart-5b138e2d-17bc-4a2c-85a8-915d3467bdba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376333576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.376333576
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.3224530253
Short name T630
Test name
Test status
Simulation time 15032796 ps
CPU time 0.73 seconds
Started Jun 11 12:46:38 PM PDT 24
Finished Jun 11 12:46:41 PM PDT 24
Peak memory 205184 kb
Host smart-21d895ab-509a-428f-87d1-6a81ea523afd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224530253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
3224530253
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.708677187
Short name T522
Test name
Test status
Simulation time 134219021 ps
CPU time 2.23 seconds
Started Jun 11 12:46:38 PM PDT 24
Finished Jun 11 12:46:43 PM PDT 24
Peak memory 224196 kb
Host smart-023d0b63-bed6-4ce6-bf7c-ff1661763be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708677187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.708677187
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.994308785
Short name T936
Test name
Test status
Simulation time 53301146 ps
CPU time 0.75 seconds
Started Jun 11 12:46:51 PM PDT 24
Finished Jun 11 12:46:54 PM PDT 24
Peak memory 206208 kb
Host smart-3b7afb5f-0828-42aa-988b-ad37732450f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994308785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.994308785
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.1518911095
Short name T211
Test name
Test status
Simulation time 62293327280 ps
CPU time 116.64 seconds
Started Jun 11 12:46:53 PM PDT 24
Finished Jun 11 12:48:51 PM PDT 24
Peak memory 250508 kb
Host smart-dae0148d-3e15-4423-9cef-5ee6b38938de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518911095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.1518911095
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.3235114252
Short name T225
Test name
Test status
Simulation time 58391236845 ps
CPU time 392.46 seconds
Started Jun 11 12:46:44 PM PDT 24
Finished Jun 11 12:53:19 PM PDT 24
Peak memory 265944 kb
Host smart-d70e9c35-6e62-4c14-83f8-f9cd5d887f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235114252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.3235114252
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.4027014866
Short name T189
Test name
Test status
Simulation time 191745834001 ps
CPU time 480.86 seconds
Started Jun 11 12:46:37 PM PDT 24
Finished Jun 11 12:54:41 PM PDT 24
Peak memory 254560 kb
Host smart-e56d95b8-684f-403b-b657-6e7b73cbaf3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027014866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.4027014866
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.1373917453
Short name T800
Test name
Test status
Simulation time 743183307 ps
CPU time 5.5 seconds
Started Jun 11 12:46:40 PM PDT 24
Finished Jun 11 12:46:48 PM PDT 24
Peak memory 232924 kb
Host smart-8416b3bd-007a-445a-99fb-5ce94b3f965c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373917453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.1373917453
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.61732166
Short name T56
Test name
Test status
Simulation time 3391411532 ps
CPU time 26.49 seconds
Started Jun 11 12:46:32 PM PDT 24
Finished Jun 11 12:47:01 PM PDT 24
Peak memory 233124 kb
Host smart-706458bc-09ac-470d-b751-95f074f37bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61732166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.61732166
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.597060155
Short name T319
Test name
Test status
Simulation time 197629280 ps
CPU time 4.29 seconds
Started Jun 11 12:46:39 PM PDT 24
Finished Jun 11 12:46:46 PM PDT 24
Peak memory 232964 kb
Host smart-8f4081b6-d3a8-4c06-aa2d-4a390a01765b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597060155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.597060155
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3754976480
Short name T153
Test name
Test status
Simulation time 1137664021 ps
CPU time 10.53 seconds
Started Jun 11 12:46:48 PM PDT 24
Finished Jun 11 12:47:01 PM PDT 24
Peak memory 232980 kb
Host smart-3aaa119c-7743-4297-b420-8dd354d3b14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754976480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3754976480
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.1789921958
Short name T789
Test name
Test status
Simulation time 617678740 ps
CPU time 3.63 seconds
Started Jun 11 12:46:34 PM PDT 24
Finished Jun 11 12:46:40 PM PDT 24
Peak memory 219148 kb
Host smart-25abf017-da7d-4e94-a68a-d2eafb00fdd8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1789921958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.1789921958
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.425766898
Short name T238
Test name
Test status
Simulation time 49304080200 ps
CPU time 405.37 seconds
Started Jun 11 12:46:34 PM PDT 24
Finished Jun 11 12:53:22 PM PDT 24
Peak memory 254184 kb
Host smart-2be91cc7-d80b-48c4-b944-389bba0898e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425766898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stres
s_all.425766898
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.1953952469
Short name T652
Test name
Test status
Simulation time 6107189668 ps
CPU time 36.74 seconds
Started Jun 11 12:46:29 PM PDT 24
Finished Jun 11 12:47:08 PM PDT 24
Peak memory 216616 kb
Host smart-996dcadb-9d6c-426b-a6e6-df7821f6dfe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953952469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1953952469
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.1001664758
Short name T484
Test name
Test status
Simulation time 13927574770 ps
CPU time 8.65 seconds
Started Jun 11 12:46:29 PM PDT 24
Finished Jun 11 12:46:39 PM PDT 24
Peak memory 216620 kb
Host smart-16b71f98-39e2-433b-9fe5-543e0e844da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001664758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.1001664758
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.2337652772
Short name T373
Test name
Test status
Simulation time 120271434 ps
CPU time 0.74 seconds
Started Jun 11 12:46:40 PM PDT 24
Finished Jun 11 12:46:48 PM PDT 24
Peak memory 205872 kb
Host smart-24e7d5c9-0cbc-427b-b22d-42701680bf34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337652772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2337652772
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.1966589326
Short name T407
Test name
Test status
Simulation time 144546469 ps
CPU time 0.85 seconds
Started Jun 11 12:46:48 PM PDT 24
Finished Jun 11 12:46:52 PM PDT 24
Peak memory 207204 kb
Host smart-14f89699-f432-4213-a5a3-18536099a451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966589326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.1966589326
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.1380922599
Short name T780
Test name
Test status
Simulation time 243967733 ps
CPU time 2.42 seconds
Started Jun 11 12:46:39 PM PDT 24
Finished Jun 11 12:46:44 PM PDT 24
Peak memory 224220 kb
Host smart-22628c44-e601-474f-8932-13d085b936cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380922599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.1380922599
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.212788504
Short name T688
Test name
Test status
Simulation time 16147435 ps
CPU time 0.73 seconds
Started Jun 11 12:45:26 PM PDT 24
Finished Jun 11 12:45:29 PM PDT 24
Peak memory 206072 kb
Host smart-3bc284ab-e2b4-4a6b-b365-70664d74045e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212788504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.212788504
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3190096756
Short name T635
Test name
Test status
Simulation time 82546513 ps
CPU time 2.64 seconds
Started Jun 11 12:45:39 PM PDT 24
Finished Jun 11 12:45:46 PM PDT 24
Peak memory 227504 kb
Host smart-58013189-7f07-4c79-a31b-e60f7eab369b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190096756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3190096756
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.477571507
Short name T418
Test name
Test status
Simulation time 42729827 ps
CPU time 0.76 seconds
Started Jun 11 12:45:36 PM PDT 24
Finished Jun 11 12:45:41 PM PDT 24
Peak memory 205824 kb
Host smart-71cf11ee-5760-4a1c-ac5a-a2ceea5d441e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477571507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.477571507
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.4103727516
Short name T230
Test name
Test status
Simulation time 107595586838 ps
CPU time 166.63 seconds
Started Jun 11 12:45:40 PM PDT 24
Finished Jun 11 12:48:32 PM PDT 24
Peak memory 237712 kb
Host smart-0a65f1f1-8219-4166-b885-339219b0f70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103727516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.4103727516
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.81612877
Short name T849
Test name
Test status
Simulation time 21469358106 ps
CPU time 77.77 seconds
Started Jun 11 12:45:29 PM PDT 24
Finished Jun 11 12:46:49 PM PDT 24
Peak memory 257724 kb
Host smart-0204acf6-9d52-4820-9e77-a6c418e346cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81612877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.81612877
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_intercept.616862479
Short name T727
Test name
Test status
Simulation time 488617900 ps
CPU time 2.79 seconds
Started Jun 11 12:45:29 PM PDT 24
Finished Jun 11 12:45:34 PM PDT 24
Peak memory 224672 kb
Host smart-94ab590e-b1e4-46ed-9abd-bd9de5b74ded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616862479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.616862479
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3207214780
Short name T291
Test name
Test status
Simulation time 285015145 ps
CPU time 4.28 seconds
Started Jun 11 12:45:28 PM PDT 24
Finished Jun 11 12:45:35 PM PDT 24
Peak memory 233184 kb
Host smart-bbde5ed3-edb2-4b2b-871f-5e4da1c85e55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207214780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3207214780
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1345144388
Short name T662
Test name
Test status
Simulation time 71567749 ps
CPU time 2.63 seconds
Started Jun 11 12:45:48 PM PDT 24
Finished Jun 11 12:45:54 PM PDT 24
Peak memory 233008 kb
Host smart-67c0bcb6-e906-49a7-b0b1-dd1c3bfdef79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345144388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1345144388
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.2676905767
Short name T394
Test name
Test status
Simulation time 13050062312 ps
CPU time 8.76 seconds
Started Jun 11 12:45:26 PM PDT 24
Finished Jun 11 12:45:37 PM PDT 24
Peak memory 223160 kb
Host smart-626944fe-f260-4cd3-9b3e-aa76c2c33400
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2676905767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.2676905767
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.4165387930
Short name T67
Test name
Test status
Simulation time 265035143 ps
CPU time 0.99 seconds
Started Jun 11 12:45:21 PM PDT 24
Finished Jun 11 12:45:25 PM PDT 24
Peak memory 236128 kb
Host smart-bd787118-2261-447e-b94d-810439890d29
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4165387930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.4165387930
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.1298766412
Short name T877
Test name
Test status
Simulation time 14998391188 ps
CPU time 123.88 seconds
Started Jun 11 12:45:32 PM PDT 24
Finished Jun 11 12:47:38 PM PDT 24
Peak memory 254664 kb
Host smart-b36b3a8b-84ed-4552-a767-92953964e6e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298766412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.1298766412
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.2708886969
Short name T951
Test name
Test status
Simulation time 3641257635 ps
CPU time 26.63 seconds
Started Jun 11 12:45:32 PM PDT 24
Finished Jun 11 12:46:01 PM PDT 24
Peak memory 216692 kb
Host smart-ce74cfee-e570-4176-9ed0-45c317576515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708886969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2708886969
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.3868762873
Short name T364
Test name
Test status
Simulation time 8905387652 ps
CPU time 7.36 seconds
Started Jun 11 12:45:27 PM PDT 24
Finished Jun 11 12:45:37 PM PDT 24
Peak memory 216676 kb
Host smart-73f41cb3-7cbd-4f52-9844-9368d98c27f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868762873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.3868762873
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.207611725
Short name T434
Test name
Test status
Simulation time 64229483 ps
CPU time 1.22 seconds
Started Jun 11 12:45:27 PM PDT 24
Finished Jun 11 12:45:30 PM PDT 24
Peak memory 216316 kb
Host smart-1ce0fbc6-fcfd-45c8-b5dd-0c807e158a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207611725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.207611725
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.3553950119
Short name T761
Test name
Test status
Simulation time 47791261 ps
CPU time 0.75 seconds
Started Jun 11 12:45:23 PM PDT 24
Finished Jun 11 12:45:26 PM PDT 24
Peak memory 206184 kb
Host smart-12d53d77-509f-46d1-8d17-bd56976726dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553950119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.3553950119
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.2120728150
Short name T602
Test name
Test status
Simulation time 4100593283 ps
CPU time 14.51 seconds
Started Jun 11 12:45:36 PM PDT 24
Finished Jun 11 12:45:55 PM PDT 24
Peak memory 233084 kb
Host smart-45eadd4a-917f-4dcc-9fc9-d8064e9c5b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120728150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2120728150
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.240628398
Short name T9
Test name
Test status
Simulation time 11773817 ps
CPU time 0.73 seconds
Started Jun 11 12:46:36 PM PDT 24
Finished Jun 11 12:46:39 PM PDT 24
Peak memory 205168 kb
Host smart-c113436c-a43a-44c8-8308-7ec75dbb8765
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240628398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.240628398
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2409625509
Short name T863
Test name
Test status
Simulation time 13253276977 ps
CPU time 33.74 seconds
Started Jun 11 12:46:40 PM PDT 24
Finished Jun 11 12:47:16 PM PDT 24
Peak memory 233132 kb
Host smart-6caa1c46-3e8b-4ab1-a54f-5ad4b4d8abe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409625509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2409625509
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.1649351405
Short name T326
Test name
Test status
Simulation time 64038695 ps
CPU time 0.78 seconds
Started Jun 11 12:46:34 PM PDT 24
Finished Jun 11 12:46:38 PM PDT 24
Peak memory 207196 kb
Host smart-5e24a697-2fce-45a0-a7f9-2c7e9d0d5b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649351405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.1649351405
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.3106460771
Short name T883
Test name
Test status
Simulation time 4343266403 ps
CPU time 23.15 seconds
Started Jun 11 12:46:34 PM PDT 24
Finished Jun 11 12:47:00 PM PDT 24
Peak memory 238024 kb
Host smart-edb7692e-984d-48e7-82cf-2b3a48f4574a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3106460771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.3106460771
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.3421759660
Short name T589
Test name
Test status
Simulation time 2121651518 ps
CPU time 9.15 seconds
Started Jun 11 12:46:45 PM PDT 24
Finished Jun 11 12:47:01 PM PDT 24
Peak memory 221692 kb
Host smart-77c16c34-5d73-47af-939a-9cc41933dd96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421759660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.3421759660
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.3958232408
Short name T245
Test name
Test status
Simulation time 62577739452 ps
CPU time 526.43 seconds
Started Jun 11 12:46:34 PM PDT 24
Finished Jun 11 12:55:23 PM PDT 24
Peak memory 253532 kb
Host smart-fce44425-5549-40eb-9357-eee793bd8477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958232408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.3958232408
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.3272525103
Short name T359
Test name
Test status
Simulation time 7349655922 ps
CPU time 36.06 seconds
Started Jun 11 12:46:35 PM PDT 24
Finished Jun 11 12:47:14 PM PDT 24
Peak memory 241308 kb
Host smart-639a8d4a-a367-45d1-a08e-d8f166ea3329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272525103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3272525103
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.3640489582
Short name T548
Test name
Test status
Simulation time 826225007 ps
CPU time 4.81 seconds
Started Jun 11 12:46:30 PM PDT 24
Finished Jun 11 12:46:37 PM PDT 24
Peak memory 224808 kb
Host smart-d27f964a-8654-4884-ae3e-93b55d62c7b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640489582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.3640489582
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.1823881572
Short name T175
Test name
Test status
Simulation time 2751079408 ps
CPU time 30.78 seconds
Started Jun 11 12:46:40 PM PDT 24
Finished Jun 11 12:47:13 PM PDT 24
Peak memory 240672 kb
Host smart-03d3896a-5c6a-4a49-a0dd-e5ba9c1247b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823881572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.1823881572
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.933310805
Short name T12
Test name
Test status
Simulation time 595366858 ps
CPU time 6.04 seconds
Started Jun 11 12:46:39 PM PDT 24
Finished Jun 11 12:46:47 PM PDT 24
Peak memory 232992 kb
Host smart-2736381d-732a-4104-9725-412bab0c67dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933310805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap
.933310805
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.3820567820
Short name T379
Test name
Test status
Simulation time 1475844876 ps
CPU time 7.07 seconds
Started Jun 11 12:46:37 PM PDT 24
Finished Jun 11 12:46:47 PM PDT 24
Peak memory 240932 kb
Host smart-fb0fc9b6-17cb-4a84-96e6-b8a69a848a2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820567820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.3820567820
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.3606707308
Short name T865
Test name
Test status
Simulation time 80684869 ps
CPU time 3.62 seconds
Started Jun 11 12:46:46 PM PDT 24
Finished Jun 11 12:46:52 PM PDT 24
Peak memory 220668 kb
Host smart-5a8850c3-8afa-4932-bb71-06986ec4586d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3606707308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.3606707308
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.2668234141
Short name T911
Test name
Test status
Simulation time 1855447342 ps
CPU time 15.02 seconds
Started Jun 11 12:46:20 PM PDT 24
Finished Jun 11 12:46:39 PM PDT 24
Peak memory 216864 kb
Host smart-e752336d-ad9d-41dd-8a10-a82a7e422bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668234141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.2668234141
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.2880911384
Short name T646
Test name
Test status
Simulation time 1558071848 ps
CPU time 4.67 seconds
Started Jun 11 12:46:33 PM PDT 24
Finished Jun 11 12:46:41 PM PDT 24
Peak memory 216600 kb
Host smart-c1128293-d118-47d5-9db4-79ae53f1237a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880911384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2880911384
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.2038367994
Short name T322
Test name
Test status
Simulation time 55813179 ps
CPU time 1.33 seconds
Started Jun 11 12:46:46 PM PDT 24
Finished Jun 11 12:46:50 PM PDT 24
Peak memory 216592 kb
Host smart-fad7fb0d-94bb-4c93-abda-8bbe2a3fc3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038367994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2038367994
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.1866976378
Short name T857
Test name
Test status
Simulation time 38843904 ps
CPU time 0.82 seconds
Started Jun 11 12:46:39 PM PDT 24
Finished Jun 11 12:46:43 PM PDT 24
Peak memory 206148 kb
Host smart-a202cfd1-8603-4359-8ad3-5ebdaee377b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866976378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1866976378
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.1880650915
Short name T435
Test name
Test status
Simulation time 26171913593 ps
CPU time 14.38 seconds
Started Jun 11 12:46:34 PM PDT 24
Finished Jun 11 12:46:51 PM PDT 24
Peak memory 233108 kb
Host smart-bfc0da84-18bf-440b-93b0-45e858784123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880650915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.1880650915
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.979341536
Short name T383
Test name
Test status
Simulation time 40174693 ps
CPU time 0.73 seconds
Started Jun 11 12:46:36 PM PDT 24
Finished Jun 11 12:46:39 PM PDT 24
Peak memory 205664 kb
Host smart-1b4cb590-a976-4f5b-bb50-42b2755d0103
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979341536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.979341536
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.1839957440
Short name T505
Test name
Test status
Simulation time 459952318 ps
CPU time 2.97 seconds
Started Jun 11 12:46:32 PM PDT 24
Finished Jun 11 12:46:38 PM PDT 24
Peak memory 233012 kb
Host smart-0963f648-a352-49f0-86ac-cf3ffeb0a277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839957440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.1839957440
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.1638708558
Short name T884
Test name
Test status
Simulation time 122956833 ps
CPU time 0.72 seconds
Started Jun 11 12:46:49 PM PDT 24
Finished Jun 11 12:46:52 PM PDT 24
Peak memory 205836 kb
Host smart-7785da45-23c0-49e1-a186-0c91a86df626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638708558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1638708558
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.3552757069
Short name T686
Test name
Test status
Simulation time 55510732943 ps
CPU time 85.66 seconds
Started Jun 11 12:46:40 PM PDT 24
Finished Jun 11 12:48:08 PM PDT 24
Peak memory 256616 kb
Host smart-63889ee7-4578-430d-82ae-585666de7a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552757069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.3552757069
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.1457826987
Short name T200
Test name
Test status
Simulation time 6964348857 ps
CPU time 94.01 seconds
Started Jun 11 12:46:31 PM PDT 24
Finished Jun 11 12:48:07 PM PDT 24
Peak memory 253060 kb
Host smart-6199d15c-9ea3-4bd1-a1ed-5c10144abb56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457826987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.1457826987
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.1427170698
Short name T685
Test name
Test status
Simulation time 9931139046 ps
CPU time 17.52 seconds
Started Jun 11 12:46:40 PM PDT 24
Finished Jun 11 12:47:00 PM PDT 24
Peak memory 219692 kb
Host smart-12130433-8762-4e1e-91fe-01192fa6fdd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427170698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.1427170698
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.3234266571
Short name T938
Test name
Test status
Simulation time 2472125532 ps
CPU time 39.18 seconds
Started Jun 11 12:46:33 PM PDT 24
Finished Jun 11 12:47:15 PM PDT 24
Peak memory 224840 kb
Host smart-e56acdea-3915-4229-8db5-e5b5ac726b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234266571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.3234266571
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.4015063287
Short name T594
Test name
Test status
Simulation time 11956599041 ps
CPU time 22.17 seconds
Started Jun 11 12:46:32 PM PDT 24
Finished Jun 11 12:46:57 PM PDT 24
Peak memory 224748 kb
Host smart-202bbd56-b081-4f1f-aae0-b69c557bc75c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015063287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.4015063287
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.3158533069
Short name T819
Test name
Test status
Simulation time 14717396870 ps
CPU time 29.79 seconds
Started Jun 11 12:46:56 PM PDT 24
Finished Jun 11 12:47:28 PM PDT 24
Peak memory 224796 kb
Host smart-efa6ae98-c453-47b4-89ba-931683bca80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158533069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.3158533069
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.2903236037
Short name T206
Test name
Test status
Simulation time 2260743451 ps
CPU time 5.02 seconds
Started Jun 11 12:46:34 PM PDT 24
Finished Jun 11 12:46:42 PM PDT 24
Peak memory 219112 kb
Host smart-07774cac-5c03-459c-9fa6-9d97f2d34206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903236037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.2903236037
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3749587158
Short name T740
Test name
Test status
Simulation time 3361132209 ps
CPU time 6.36 seconds
Started Jun 11 12:46:29 PM PDT 24
Finished Jun 11 12:46:37 PM PDT 24
Peak memory 224904 kb
Host smart-3e14cd5d-137b-4d69-90e2-fe7f962e1a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3749587158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3749587158
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.2846554690
Short name T535
Test name
Test status
Simulation time 394268612 ps
CPU time 4.89 seconds
Started Jun 11 12:46:42 PM PDT 24
Finished Jun 11 12:46:49 PM PDT 24
Peak memory 220256 kb
Host smart-81767207-bdcb-4c84-91d8-b121490b4f4b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2846554690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.2846554690
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.23240264
Short name T212
Test name
Test status
Simulation time 80347032192 ps
CPU time 312.39 seconds
Started Jun 11 12:46:48 PM PDT 24
Finished Jun 11 12:52:03 PM PDT 24
Peak memory 271700 kb
Host smart-301d33d9-64eb-40b9-877a-084dba95fa0a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23240264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stress
_all.23240264
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.1732124089
Short name T709
Test name
Test status
Simulation time 14880421774 ps
CPU time 37.18 seconds
Started Jun 11 12:46:27 PM PDT 24
Finished Jun 11 12:47:06 PM PDT 24
Peak memory 216920 kb
Host smart-9f5ae31d-f22f-4e09-91cc-70d1d974f416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732124089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.1732124089
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.2486933793
Short name T642
Test name
Test status
Simulation time 4223624637 ps
CPU time 14.43 seconds
Started Jun 11 12:46:40 PM PDT 24
Finished Jun 11 12:46:57 PM PDT 24
Peak memory 216664 kb
Host smart-57875df6-5dc2-4bbd-a5fc-81dcba79bb6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486933793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.2486933793
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.2232771802
Short name T749
Test name
Test status
Simulation time 119145139 ps
CPU time 1.82 seconds
Started Jun 11 12:46:32 PM PDT 24
Finished Jun 11 12:46:37 PM PDT 24
Peak memory 208312 kb
Host smart-95b2c04a-433b-4aff-87aa-7b2adcc9949e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232771802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.2232771802
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.3584041592
Short name T316
Test name
Test status
Simulation time 197892309 ps
CPU time 0.87 seconds
Started Jun 11 12:46:37 PM PDT 24
Finished Jun 11 12:46:40 PM PDT 24
Peak memory 206156 kb
Host smart-a3a6d885-b547-4bd9-9a74-fffd62c8261a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584041592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.3584041592
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.3088920685
Short name T953
Test name
Test status
Simulation time 15181788289 ps
CPU time 11.9 seconds
Started Jun 11 12:46:59 PM PDT 24
Finished Jun 11 12:47:13 PM PDT 24
Peak memory 219916 kb
Host smart-d40b24a0-e605-4a87-81a4-f24b0594c45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088920685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3088920685
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.388725413
Short name T333
Test name
Test status
Simulation time 131738326 ps
CPU time 0.73 seconds
Started Jun 11 12:46:35 PM PDT 24
Finished Jun 11 12:46:38 PM PDT 24
Peak memory 205156 kb
Host smart-0215c499-a2c6-4f99-bc4b-1bfa52203488
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388725413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.388725413
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.484430795
Short name T389
Test name
Test status
Simulation time 2049924230 ps
CPU time 4.59 seconds
Started Jun 11 12:46:46 PM PDT 24
Finished Jun 11 12:46:52 PM PDT 24
Peak memory 232880 kb
Host smart-3f34a9c8-4037-471f-88fb-f9d523423d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484430795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.484430795
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.3766549062
Short name T875
Test name
Test status
Simulation time 20838749 ps
CPU time 0.77 seconds
Started Jun 11 12:46:57 PM PDT 24
Finished Jun 11 12:47:00 PM PDT 24
Peak memory 206848 kb
Host smart-dadb2f5d-99d5-4461-988d-07bea0e55bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766549062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3766549062
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.3236480913
Short name T45
Test name
Test status
Simulation time 7397437797 ps
CPU time 43.58 seconds
Started Jun 11 12:46:40 PM PDT 24
Finished Jun 11 12:47:30 PM PDT 24
Peak memory 224872 kb
Host smart-6008a243-8a92-4921-be28-457ab19c6425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236480913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.3236480913
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.849017125
Short name T122
Test name
Test status
Simulation time 9989349838 ps
CPU time 84.64 seconds
Started Jun 11 12:46:50 PM PDT 24
Finished Jun 11 12:48:17 PM PDT 24
Peak memory 252720 kb
Host smart-56370bcd-ee84-4626-969d-db6b345fa38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849017125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.849017125
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.2819937141
Short name T415
Test name
Test status
Simulation time 28744476612 ps
CPU time 37.85 seconds
Started Jun 11 12:46:33 PM PDT 24
Finished Jun 11 12:47:13 PM PDT 24
Peak memory 224812 kb
Host smart-cbe01d8e-ada2-46ec-8a25-f845d7c0d14a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819937141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.2819937141
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.2313644009
Short name T294
Test name
Test status
Simulation time 29123906896 ps
CPU time 34.26 seconds
Started Jun 11 12:46:35 PM PDT 24
Finished Jun 11 12:47:16 PM PDT 24
Peak memory 240716 kb
Host smart-4a3baf68-5084-4e1e-9ebd-4250cd703c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313644009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2313644009
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.1893459722
Short name T414
Test name
Test status
Simulation time 4552409631 ps
CPU time 9.06 seconds
Started Jun 11 12:46:49 PM PDT 24
Finished Jun 11 12:47:00 PM PDT 24
Peak memory 233108 kb
Host smart-32347c32-d77b-4868-a79a-02dcf175ac00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893459722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.1893459722
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.2161939612
Short name T593
Test name
Test status
Simulation time 246579584 ps
CPU time 4.05 seconds
Started Jun 11 12:46:34 PM PDT 24
Finished Jun 11 12:46:40 PM PDT 24
Peak memory 224652 kb
Host smart-90198d01-5347-42c8-81ef-97b2ba398364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2161939612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.2161939612
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.3510538338
Short name T263
Test name
Test status
Simulation time 6465668234 ps
CPU time 8.5 seconds
Started Jun 11 12:46:34 PM PDT 24
Finished Jun 11 12:46:45 PM PDT 24
Peak memory 224844 kb
Host smart-ef67f722-883b-4ce8-b9d2-55f559881d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510538338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.3510538338
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.4127832548
Short name T721
Test name
Test status
Simulation time 251757163 ps
CPU time 5.14 seconds
Started Jun 11 12:46:45 PM PDT 24
Finished Jun 11 12:46:52 PM PDT 24
Peak memory 240932 kb
Host smart-8400d9c2-43f8-4b5a-bfe7-1b6fd010deff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127832548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.4127832548
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.2117260179
Short name T134
Test name
Test status
Simulation time 10742558528 ps
CPU time 12.25 seconds
Started Jun 11 12:46:42 PM PDT 24
Finished Jun 11 12:46:56 PM PDT 24
Peak memory 222056 kb
Host smart-a872d875-77af-403f-a3db-5318b6e7a76f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2117260179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.2117260179
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.3845758578
Short name T22
Test name
Test status
Simulation time 38556159 ps
CPU time 0.91 seconds
Started Jun 11 12:46:35 PM PDT 24
Finished Jun 11 12:46:39 PM PDT 24
Peak memory 206928 kb
Host smart-bcfa8a7f-436e-4a7d-878c-0905f3135330
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845758578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.3845758578
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.2045820724
Short name T485
Test name
Test status
Simulation time 1342677685 ps
CPU time 8.41 seconds
Started Jun 11 12:46:54 PM PDT 24
Finished Jun 11 12:47:03 PM PDT 24
Peak memory 216620 kb
Host smart-e9b0dba0-ac62-45b7-b4f2-841867134da3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045820724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.2045820724
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.121278697
Short name T609
Test name
Test status
Simulation time 4596979103 ps
CPU time 10.66 seconds
Started Jun 11 12:46:52 PM PDT 24
Finished Jun 11 12:47:04 PM PDT 24
Peak memory 216620 kb
Host smart-5ee30c9c-1acd-4cfd-a274-761349d9c427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=121278697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.121278697
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.219672650
Short name T480
Test name
Test status
Simulation time 47013742 ps
CPU time 0.68 seconds
Started Jun 11 12:46:50 PM PDT 24
Finished Jun 11 12:46:53 PM PDT 24
Peak memory 205892 kb
Host smart-27ccd479-b79b-4639-a622-75a07146a87f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219672650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.219672650
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.3297870082
Short name T340
Test name
Test status
Simulation time 104566640 ps
CPU time 1.05 seconds
Started Jun 11 12:46:42 PM PDT 24
Finished Jun 11 12:46:45 PM PDT 24
Peak memory 207184 kb
Host smart-f243105e-9107-4539-91de-51569041321e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297870082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3297870082
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.1455149903
Short name T901
Test name
Test status
Simulation time 280236289 ps
CPU time 4.47 seconds
Started Jun 11 12:46:44 PM PDT 24
Finished Jun 11 12:46:51 PM PDT 24
Peak memory 232968 kb
Host smart-a751d138-28db-4bdc-a61d-bb7140602df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455149903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1455149903
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.1251905422
Short name T725
Test name
Test status
Simulation time 15251303 ps
CPU time 0.75 seconds
Started Jun 11 12:46:34 PM PDT 24
Finished Jun 11 12:46:37 PM PDT 24
Peak memory 205716 kb
Host smart-73e6f1e7-218b-4eb1-9ad5-bdcdfd9acfff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251905422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
1251905422
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.1272633658
Short name T401
Test name
Test status
Simulation time 686544787 ps
CPU time 2.53 seconds
Started Jun 11 12:46:48 PM PDT 24
Finished Jun 11 12:46:53 PM PDT 24
Peak memory 224712 kb
Host smart-31ae3451-52c3-4fdc-905e-1a06daa68790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1272633658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1272633658
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.677311352
Short name T69
Test name
Test status
Simulation time 182361568 ps
CPU time 0.76 seconds
Started Jun 11 12:46:46 PM PDT 24
Finished Jun 11 12:46:49 PM PDT 24
Peak memory 207184 kb
Host smart-915fc058-be91-43b9-92e6-7c1d06186eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677311352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.677311352
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.3129607175
Short name T481
Test name
Test status
Simulation time 18668978582 ps
CPU time 65.47 seconds
Started Jun 11 12:46:43 PM PDT 24
Finished Jun 11 12:47:51 PM PDT 24
Peak memory 249392 kb
Host smart-8fbff011-5fdc-4112-832e-35b9957738bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129607175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.3129607175
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.784436754
Short name T859
Test name
Test status
Simulation time 10562241963 ps
CPU time 60.69 seconds
Started Jun 11 12:46:40 PM PDT 24
Finished Jun 11 12:47:43 PM PDT 24
Peak memory 251720 kb
Host smart-798a3db8-5870-4254-832c-7fce67ff7182
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784436754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.784436754
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.1326777666
Short name T948
Test name
Test status
Simulation time 5571943731 ps
CPU time 53.35 seconds
Started Jun 11 12:46:30 PM PDT 24
Finished Jun 11 12:47:25 PM PDT 24
Peak memory 249756 kb
Host smart-8b07837c-09ee-4bd1-b104-bb9370280468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326777666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.1326777666
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.2763568688
Short name T569
Test name
Test status
Simulation time 750584181 ps
CPU time 6.11 seconds
Started Jun 11 12:46:31 PM PDT 24
Finished Jun 11 12:46:40 PM PDT 24
Peak memory 239216 kb
Host smart-38ec86b9-1517-4a02-9613-a606c08175d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763568688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2763568688
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.3345800705
Short name T828
Test name
Test status
Simulation time 222167441 ps
CPU time 5.91 seconds
Started Jun 11 12:46:33 PM PDT 24
Finished Jun 11 12:46:42 PM PDT 24
Peak memory 232916 kb
Host smart-5ad39fb4-a6d5-4502-ae60-e16ffc4f0440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345800705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.3345800705
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.841333145
Short name T691
Test name
Test status
Simulation time 283123305 ps
CPU time 4.48 seconds
Started Jun 11 12:46:49 PM PDT 24
Finished Jun 11 12:46:56 PM PDT 24
Peak memory 232092 kb
Host smart-7f73c28d-bfce-4a6f-9f6a-4795cbcc8c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841333145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.841333145
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1461025957
Short name T1
Test name
Test status
Simulation time 704459686 ps
CPU time 5.76 seconds
Started Jun 11 12:46:39 PM PDT 24
Finished Jun 11 12:46:47 PM PDT 24
Peak memory 232976 kb
Host smart-ab9d7dc2-5ee5-4808-ad8d-313f0cf60043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461025957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.1461025957
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.4175328231
Short name T258
Test name
Test status
Simulation time 4592506099 ps
CPU time 8.79 seconds
Started Jun 11 12:46:36 PM PDT 24
Finished Jun 11 12:46:47 PM PDT 24
Peak memory 224896 kb
Host smart-e40f4647-89b7-4185-81a9-93fbf7d053c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175328231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.4175328231
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.2491783298
Short name T445
Test name
Test status
Simulation time 1880231323 ps
CPU time 8.49 seconds
Started Jun 11 12:46:48 PM PDT 24
Finished Jun 11 12:46:58 PM PDT 24
Peak memory 222588 kb
Host smart-def2b2df-ab6d-4859-9c85-6d9b2d8ff478
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2491783298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.2491783298
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.348818421
Short name T214
Test name
Test status
Simulation time 38050174439 ps
CPU time 146.95 seconds
Started Jun 11 12:46:47 PM PDT 24
Finished Jun 11 12:49:16 PM PDT 24
Peak memory 265520 kb
Host smart-abeb3187-e38c-401a-aee7-b2d2b7c0c256
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348818421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stres
s_all.348818421
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.4083721816
Short name T760
Test name
Test status
Simulation time 3475092669 ps
CPU time 22.48 seconds
Started Jun 11 12:46:36 PM PDT 24
Finished Jun 11 12:47:01 PM PDT 24
Peak memory 216896 kb
Host smart-5572c8c6-0a31-44a1-a8bd-296cf5cea3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083721816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.4083721816
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.3867645606
Short name T550
Test name
Test status
Simulation time 1779714787 ps
CPU time 1.56 seconds
Started Jun 11 12:46:31 PM PDT 24
Finished Jun 11 12:46:34 PM PDT 24
Peak memory 208088 kb
Host smart-b21d4a9f-45c8-4b5a-8428-b73d5a999c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867645606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.3867645606
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.3549587755
Short name T324
Test name
Test status
Simulation time 42886881 ps
CPU time 0.72 seconds
Started Jun 11 12:46:45 PM PDT 24
Finished Jun 11 12:46:48 PM PDT 24
Peak memory 206160 kb
Host smart-0941411d-07b6-4fbb-ae65-6e2c737e9f69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549587755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3549587755
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.1721566335
Short name T744
Test name
Test status
Simulation time 44591866 ps
CPU time 0.75 seconds
Started Jun 11 12:46:40 PM PDT 24
Finished Jun 11 12:46:43 PM PDT 24
Peak memory 205912 kb
Host smart-477197a1-e39f-4270-bf4c-c54c98434749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721566335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.1721566335
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.1903274014
Short name T75
Test name
Test status
Simulation time 9231143308 ps
CPU time 16.56 seconds
Started Jun 11 12:46:34 PM PDT 24
Finished Jun 11 12:47:03 PM PDT 24
Peak memory 240588 kb
Host smart-69c3efe9-2f27-4bd1-a728-6daad8f9eb2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903274014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.1903274014
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.4282111807
Short name T553
Test name
Test status
Simulation time 55017061 ps
CPU time 0.72 seconds
Started Jun 11 12:47:11 PM PDT 24
Finished Jun 11 12:47:15 PM PDT 24
Peak memory 206076 kb
Host smart-bdb02c7d-f93e-44d0-ba3b-009bb7403931
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282111807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
4282111807
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.3939858106
Short name T282
Test name
Test status
Simulation time 161353036 ps
CPU time 5.37 seconds
Started Jun 11 12:46:51 PM PDT 24
Finished Jun 11 12:46:58 PM PDT 24
Peak memory 232956 kb
Host smart-5c7ce0e1-a514-4001-aff9-4489a1ade977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939858106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3939858106
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1297013488
Short name T628
Test name
Test status
Simulation time 60995819 ps
CPU time 0.74 seconds
Started Jun 11 12:46:59 PM PDT 24
Finished Jun 11 12:47:03 PM PDT 24
Peak memory 206160 kb
Host smart-763806e8-461c-45b5-b789-d4f865f64a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297013488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1297013488
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.165992818
Short name T545
Test name
Test status
Simulation time 9445654614 ps
CPU time 17.64 seconds
Started Jun 11 12:47:30 PM PDT 24
Finished Jun 11 12:47:53 PM PDT 24
Peak memory 236368 kb
Host smart-d9c4bc4f-3107-4487-a120-514444d950a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165992818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.165992818
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.2878855307
Short name T73
Test name
Test status
Simulation time 6021788129 ps
CPU time 30.88 seconds
Started Jun 11 12:47:08 PM PDT 24
Finished Jun 11 12:47:42 PM PDT 24
Peak memory 224864 kb
Host smart-8b10a5b7-b95d-4059-bafb-3f3ed9899327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878855307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.2878855307
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.1500414945
Short name T841
Test name
Test status
Simulation time 201967396964 ps
CPU time 169.57 seconds
Started Jun 11 12:46:51 PM PDT 24
Finished Jun 11 12:49:42 PM PDT 24
Peak memory 249644 kb
Host smart-f96e906a-c0eb-4720-8a6a-dd845f1a06cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500414945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.1500414945
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.372555937
Short name T701
Test name
Test status
Simulation time 511039109 ps
CPU time 5.23 seconds
Started Jun 11 12:46:33 PM PDT 24
Finished Jun 11 12:46:46 PM PDT 24
Peak memory 224680 kb
Host smart-d29483d0-f5a5-4df4-9b2f-e52d29eed447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372555937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.372555937
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.2598312384
Short name T543
Test name
Test status
Simulation time 2297839074 ps
CPU time 7.6 seconds
Started Jun 11 12:46:51 PM PDT 24
Finished Jun 11 12:47:00 PM PDT 24
Peak memory 233104 kb
Host smart-da9b8186-6d7f-4506-80c6-39de1f7f96af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598312384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.2598312384
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.1954609526
Short name T580
Test name
Test status
Simulation time 15594890532 ps
CPU time 41.29 seconds
Started Jun 11 12:46:40 PM PDT 24
Finished Jun 11 12:47:24 PM PDT 24
Peak memory 240704 kb
Host smart-e054ac67-5e93-474a-a3fc-9cc0452bccd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954609526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.1954609526
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.4176099704
Short name T203
Test name
Test status
Simulation time 474209898 ps
CPU time 6.33 seconds
Started Jun 11 12:46:45 PM PDT 24
Finished Jun 11 12:46:54 PM PDT 24
Peak memory 227524 kb
Host smart-bafb025b-b913-457c-8004-6bf78fc6a33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176099704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.4176099704
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.872698579
Short name T280
Test name
Test status
Simulation time 432658731 ps
CPU time 2.85 seconds
Started Jun 11 12:46:33 PM PDT 24
Finished Jun 11 12:46:39 PM PDT 24
Peak memory 224700 kb
Host smart-29a6cfd3-0cdd-4856-9ef9-4418a56d357b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872698579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.872698579
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.1433812849
Short name T606
Test name
Test status
Simulation time 262853563 ps
CPU time 3.84 seconds
Started Jun 11 12:46:51 PM PDT 24
Finished Jun 11 12:46:56 PM PDT 24
Peak memory 220884 kb
Host smart-4574e12d-b7fb-4708-953e-0c72e5824214
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1433812849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.1433812849
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1830287210
Short name T216
Test name
Test status
Simulation time 16735005183 ps
CPU time 175.25 seconds
Started Jun 11 12:46:58 PM PDT 24
Finished Jun 11 12:49:56 PM PDT 24
Peak memory 251376 kb
Host smart-04b885e6-3c08-417e-8147-63558acf33ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830287210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1830287210
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.3297840538
Short name T732
Test name
Test status
Simulation time 28824584763 ps
CPU time 40.35 seconds
Started Jun 11 12:46:35 PM PDT 24
Finished Jun 11 12:47:18 PM PDT 24
Peak memory 220396 kb
Host smart-5f80c977-b6b6-47d3-ac2b-4278a1735c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3297840538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.3297840538
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.2620249188
Short name T433
Test name
Test status
Simulation time 993893998 ps
CPU time 5.98 seconds
Started Jun 11 12:46:40 PM PDT 24
Finished Jun 11 12:46:48 PM PDT 24
Peak memory 216572 kb
Host smart-1646fe7a-fecb-4290-b2fe-dc7b35fa0ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620249188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.2620249188
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.3267339031
Short name T431
Test name
Test status
Simulation time 30104718 ps
CPU time 0.9 seconds
Started Jun 11 12:46:29 PM PDT 24
Finished Jun 11 12:46:32 PM PDT 24
Peak memory 207028 kb
Host smart-36043de9-59d4-41a8-b4ee-8963c9d2824c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267339031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.3267339031
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.4029569834
Short name T332
Test name
Test status
Simulation time 64350613 ps
CPU time 0.83 seconds
Started Jun 11 12:46:42 PM PDT 24
Finished Jun 11 12:46:45 PM PDT 24
Peak memory 206156 kb
Host smart-e01919d3-ac45-49c5-9d39-d0e62039f2b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4029569834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.4029569834
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.3855337857
Short name T342
Test name
Test status
Simulation time 41209422 ps
CPU time 2.49 seconds
Started Jun 11 12:46:50 PM PDT 24
Finished Jun 11 12:46:54 PM PDT 24
Peak memory 224600 kb
Host smart-12a20dec-a65a-4e7f-bbba-76a60b30f022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855337857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.3855337857
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.476906551
Short name T520
Test name
Test status
Simulation time 51164136 ps
CPU time 0.76 seconds
Started Jun 11 12:47:08 PM PDT 24
Finished Jun 11 12:47:12 PM PDT 24
Peak memory 205692 kb
Host smart-e5b6a0de-1b45-4b0d-9a8e-febc1355533d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476906551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.476906551
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.3869088667
Short name T281
Test name
Test status
Simulation time 467015735 ps
CPU time 2.45 seconds
Started Jun 11 12:46:47 PM PDT 24
Finished Jun 11 12:46:52 PM PDT 24
Peak memory 224920 kb
Host smart-b2a2ea72-5224-436a-bf4f-d79e9c11e3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869088667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.3869088667
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.2276016157
Short name T327
Test name
Test status
Simulation time 17941801 ps
CPU time 0.76 seconds
Started Jun 11 12:46:59 PM PDT 24
Finished Jun 11 12:47:03 PM PDT 24
Peak memory 205844 kb
Host smart-6bad2236-2225-482d-b2b9-c747f263e28f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276016157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.2276016157
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.2897140383
Short name T494
Test name
Test status
Simulation time 3824166428 ps
CPU time 51.95 seconds
Started Jun 11 12:46:49 PM PDT 24
Finished Jun 11 12:47:43 PM PDT 24
Peak memory 249428 kb
Host smart-e546eda1-c00c-4d18-a69a-3773a8f82ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897140383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.2897140383
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.3876641371
Short name T814
Test name
Test status
Simulation time 3940689922 ps
CPU time 33.98 seconds
Started Jun 11 12:46:47 PM PDT 24
Finished Jun 11 12:47:24 PM PDT 24
Peak memory 239816 kb
Host smart-eaf4adb6-b6c8-4cbc-a9b8-4e7ace356e90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876641371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.3876641371
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.3823500954
Short name T267
Test name
Test status
Simulation time 4674031741 ps
CPU time 70.98 seconds
Started Jun 11 12:46:56 PM PDT 24
Finished Jun 11 12:48:09 PM PDT 24
Peak memory 254328 kb
Host smart-1d48cd3e-cc2f-45a0-8b0c-f56ed283a9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823500954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.3823500954
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.711143564
Short name T296
Test name
Test status
Simulation time 494611632 ps
CPU time 5.78 seconds
Started Jun 11 12:46:57 PM PDT 24
Finished Jun 11 12:47:05 PM PDT 24
Peak memory 239940 kb
Host smart-23d995db-53ef-4547-bf4c-8a5f300f8d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711143564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.711143564
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.1906033379
Short name T162
Test name
Test status
Simulation time 678410109 ps
CPU time 7.47 seconds
Started Jun 11 12:46:54 PM PDT 24
Finished Jun 11 12:47:03 PM PDT 24
Peak memory 232912 kb
Host smart-189b07c0-bb84-42f8-bdfc-18534e9064e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906033379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.1906033379
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.2882120094
Short name T842
Test name
Test status
Simulation time 5322757383 ps
CPU time 47.54 seconds
Started Jun 11 12:46:50 PM PDT 24
Finished Jun 11 12:47:40 PM PDT 24
Peak memory 234300 kb
Host smart-ed46c67c-0143-4fb5-8c3a-6cefeea6dddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882120094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.2882120094
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.3920766741
Short name T50
Test name
Test status
Simulation time 5823249473 ps
CPU time 9 seconds
Started Jun 11 12:46:44 PM PDT 24
Finished Jun 11 12:46:55 PM PDT 24
Peak memory 233104 kb
Host smart-f0dc894c-7a38-43d4-98ba-1add8fc69a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920766741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.3920766741
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.2954011726
Short name T672
Test name
Test status
Simulation time 312479872 ps
CPU time 2.92 seconds
Started Jun 11 12:47:08 PM PDT 24
Finished Jun 11 12:47:14 PM PDT 24
Peak memory 224616 kb
Host smart-0c8e1868-5b2c-4cd3-95b3-1d525c7224ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954011726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2954011726
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.3419392693
Short name T717
Test name
Test status
Simulation time 309505797 ps
CPU time 4.56 seconds
Started Jun 11 12:47:01 PM PDT 24
Finished Jun 11 12:47:08 PM PDT 24
Peak memory 219572 kb
Host smart-b8fbbbc4-266d-49d8-b73b-f81370830b12
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3419392693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.3419392693
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.3931736783
Short name T894
Test name
Test status
Simulation time 8672100728 ps
CPU time 22.67 seconds
Started Jun 11 12:46:50 PM PDT 24
Finished Jun 11 12:47:14 PM PDT 24
Peak memory 235224 kb
Host smart-7a2d0d00-d243-430d-b5b0-806426c7d121
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931736783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.3931736783
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.3686772571
Short name T542
Test name
Test status
Simulation time 7182100137 ps
CPU time 19.64 seconds
Started Jun 11 12:47:00 PM PDT 24
Finished Jun 11 12:47:23 PM PDT 24
Peak memory 216776 kb
Host smart-01996e93-4ef4-43fe-a818-474902d29a7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686772571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.3686772571
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.3459328110
Short name T785
Test name
Test status
Simulation time 34120730446 ps
CPU time 10.89 seconds
Started Jun 11 12:46:55 PM PDT 24
Finished Jun 11 12:47:08 PM PDT 24
Peak memory 216692 kb
Host smart-12e62d63-180f-4006-93af-73d6847adb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459328110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3459328110
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.4067969607
Short name T596
Test name
Test status
Simulation time 16228730 ps
CPU time 0.87 seconds
Started Jun 11 12:47:01 PM PDT 24
Finished Jun 11 12:47:05 PM PDT 24
Peak memory 207288 kb
Host smart-4eba2278-95c4-4ec4-bcd9-85d40817032f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067969607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.4067969607
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.455421040
Short name T818
Test name
Test status
Simulation time 29234189 ps
CPU time 0.75 seconds
Started Jun 11 12:46:58 PM PDT 24
Finished Jun 11 12:47:02 PM PDT 24
Peak memory 206176 kb
Host smart-8b577e22-a132-4932-993a-9a6f20f7d1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455421040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.455421040
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.945447936
Short name T908
Test name
Test status
Simulation time 8300571263 ps
CPU time 12.01 seconds
Started Jun 11 12:46:54 PM PDT 24
Finished Jun 11 12:47:08 PM PDT 24
Peak memory 233156 kb
Host smart-fb48a544-bd1a-4e82-be4f-70188e6d3888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945447936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.945447936
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.2298878165
Short name T715
Test name
Test status
Simulation time 34213563 ps
CPU time 0.75 seconds
Started Jun 11 12:46:36 PM PDT 24
Finished Jun 11 12:46:39 PM PDT 24
Peak memory 205184 kb
Host smart-0dd030b7-6a89-40b6-85ff-96ebf9a0f18e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298878165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
2298878165
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.1098631392
Short name T772
Test name
Test status
Simulation time 39696217 ps
CPU time 2.56 seconds
Started Jun 11 12:46:57 PM PDT 24
Finished Jun 11 12:47:03 PM PDT 24
Peak memory 232992 kb
Host smart-e4d7f24d-b2eb-412a-bd97-2c763b9c63d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098631392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1098631392
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.1111961156
Short name T400
Test name
Test status
Simulation time 51976176 ps
CPU time 0.8 seconds
Started Jun 11 12:46:49 PM PDT 24
Finished Jun 11 12:46:52 PM PDT 24
Peak memory 206748 kb
Host smart-0977a996-45b5-4f9c-89d9-c51d08f47553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111961156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.1111961156
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.3960731157
Short name T77
Test name
Test status
Simulation time 15049065219 ps
CPU time 97.03 seconds
Started Jun 11 12:47:13 PM PDT 24
Finished Jun 11 12:48:52 PM PDT 24
Peak memory 254864 kb
Host smart-465f2552-df7c-41ca-9cfb-62a9fe5fc7ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960731157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.3960731157
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.2198232273
Short name T41
Test name
Test status
Simulation time 16260274752 ps
CPU time 166.62 seconds
Started Jun 11 12:47:06 PM PDT 24
Finished Jun 11 12:49:55 PM PDT 24
Peak memory 257408 kb
Host smart-32934639-8f23-4e16-aea2-4b93dbaf15fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198232273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.2198232273
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.2450644036
Short name T767
Test name
Test status
Simulation time 2987321077 ps
CPU time 13.01 seconds
Started Jun 11 12:47:00 PM PDT 24
Finished Jun 11 12:47:16 PM PDT 24
Peak memory 217924 kb
Host smart-1b95b923-9034-40e2-a21d-c18c94152a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450644036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.2450644036
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.240476655
Short name T617
Test name
Test status
Simulation time 1478475166 ps
CPU time 6.51 seconds
Started Jun 11 12:46:49 PM PDT 24
Finished Jun 11 12:46:57 PM PDT 24
Peak memory 224716 kb
Host smart-b0793d23-dbf7-4178-919f-a61ec77b9a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240476655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.240476655
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.225016258
Short name T410
Test name
Test status
Simulation time 608548235 ps
CPU time 4.05 seconds
Started Jun 11 12:46:58 PM PDT 24
Finished Jun 11 12:47:05 PM PDT 24
Peak memory 224704 kb
Host smart-ae417f5d-fbdc-4029-af36-ccd5a2405a5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225016258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.225016258
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.1334762086
Short name T680
Test name
Test status
Simulation time 116831711 ps
CPU time 3.3 seconds
Started Jun 11 12:46:50 PM PDT 24
Finished Jun 11 12:46:55 PM PDT 24
Peak memory 227780 kb
Host smart-e8fc411b-1438-49a6-9de2-6d36e2dbdbca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334762086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.1334762086
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.2092362844
Short name T733
Test name
Test status
Simulation time 264124355 ps
CPU time 5.74 seconds
Started Jun 11 12:46:56 PM PDT 24
Finished Jun 11 12:47:04 PM PDT 24
Peak memory 240548 kb
Host smart-55bd0b22-94e5-4e3d-bcf3-33a6a1649acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092362844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.2092362844
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.3601529858
Short name T807
Test name
Test status
Simulation time 1391445861 ps
CPU time 5.53 seconds
Started Jun 11 12:46:47 PM PDT 24
Finished Jun 11 12:46:55 PM PDT 24
Peak memory 224680 kb
Host smart-8d6636d4-f37d-4068-bbe9-8a13d83f6da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601529858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3601529858
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.1082753507
Short name T792
Test name
Test status
Simulation time 658845978 ps
CPU time 8.6 seconds
Started Jun 11 12:46:56 PM PDT 24
Finished Jun 11 12:47:07 PM PDT 24
Peak memory 220632 kb
Host smart-18253b63-3d93-4db0-bb64-2b998ed297f4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1082753507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.1082753507
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.2999831348
Short name T28
Test name
Test status
Simulation time 165933790 ps
CPU time 0.85 seconds
Started Jun 11 12:46:46 PM PDT 24
Finished Jun 11 12:46:49 PM PDT 24
Peak memory 206868 kb
Host smart-59fe27c0-1ad4-4b05-bf2a-069960df8bbd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999831348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.2999831348
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.1607628807
Short name T544
Test name
Test status
Simulation time 14959432337 ps
CPU time 41.16 seconds
Started Jun 11 12:46:37 PM PDT 24
Finished Jun 11 12:47:21 PM PDT 24
Peak memory 216524 kb
Host smart-c1c291a3-949f-4a94-8d5c-67afbe9a2c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607628807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1607628807
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3050743334
Short name T74
Test name
Test status
Simulation time 6743781857 ps
CPU time 17.21 seconds
Started Jun 11 12:46:57 PM PDT 24
Finished Jun 11 12:47:17 PM PDT 24
Peak memory 216716 kb
Host smart-502c55c1-a93d-4284-9f60-85fa7124bb0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050743334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3050743334
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.983466361
Short name T616
Test name
Test status
Simulation time 32220817 ps
CPU time 0.8 seconds
Started Jun 11 12:46:48 PM PDT 24
Finished Jun 11 12:46:51 PM PDT 24
Peak memory 206896 kb
Host smart-ff8452e5-2754-447d-964c-8509ee53a731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983466361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.983466361
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.2932090948
Short name T352
Test name
Test status
Simulation time 19983187 ps
CPU time 0.73 seconds
Started Jun 11 12:46:47 PM PDT 24
Finished Jun 11 12:46:50 PM PDT 24
Peak memory 206128 kb
Host smart-d1db0d7d-780c-464d-868f-da73f21b586b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932090948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.2932090948
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.2228864524
Short name T170
Test name
Test status
Simulation time 2934307319 ps
CPU time 10.26 seconds
Started Jun 11 12:46:38 PM PDT 24
Finished Jun 11 12:46:51 PM PDT 24
Peak memory 249380 kb
Host smart-48de79b6-9505-477b-83fe-442a492b43b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228864524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.2228864524
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.1636938078
Short name T949
Test name
Test status
Simulation time 33952689 ps
CPU time 0.71 seconds
Started Jun 11 12:46:52 PM PDT 24
Finished Jun 11 12:46:54 PM PDT 24
Peak memory 205168 kb
Host smart-4ba205ab-2886-4995-a7bc-f0d127628f97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636938078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
1636938078
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.2289240535
Short name T665
Test name
Test status
Simulation time 140599159 ps
CPU time 3.2 seconds
Started Jun 11 12:46:53 PM PDT 24
Finished Jun 11 12:46:57 PM PDT 24
Peak memory 224700 kb
Host smart-717db150-f082-4790-bf32-bb84e53074af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289240535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2289240535
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.3738433884
Short name T930
Test name
Test status
Simulation time 44348065 ps
CPU time 0.73 seconds
Started Jun 11 12:46:56 PM PDT 24
Finished Jun 11 12:46:59 PM PDT 24
Peak memory 206152 kb
Host smart-395333fa-fbfd-4d4f-922d-89ec4a059382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738433884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.3738433884
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.1072245735
Short name T653
Test name
Test status
Simulation time 42751308660 ps
CPU time 72.66 seconds
Started Jun 11 12:46:58 PM PDT 24
Finished Jun 11 12:48:13 PM PDT 24
Peak memory 249748 kb
Host smart-3738627d-d15b-4972-9b12-459a0e16692f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072245735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.1072245735
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.917864215
Short name T243
Test name
Test status
Simulation time 73048012013 ps
CPU time 148.72 seconds
Started Jun 11 12:47:01 PM PDT 24
Finished Jun 11 12:49:33 PM PDT 24
Peak memory 240056 kb
Host smart-00eb6059-ec0a-48af-be06-9a038b2b9dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917864215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle
.917864215
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.279903910
Short name T657
Test name
Test status
Simulation time 1230775064 ps
CPU time 9.67 seconds
Started Jun 11 12:46:56 PM PDT 24
Finished Jun 11 12:47:08 PM PDT 24
Peak memory 243228 kb
Host smart-97e0ebb5-7a1e-415f-9446-159542652b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279903910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.279903910
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.1711863831
Short name T467
Test name
Test status
Simulation time 719649074 ps
CPU time 4.45 seconds
Started Jun 11 12:46:45 PM PDT 24
Finished Jun 11 12:46:52 PM PDT 24
Peak memory 232996 kb
Host smart-2ed259c8-e8cc-4f86-b138-01b46c096aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711863831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.1711863831
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3074306243
Short name T421
Test name
Test status
Simulation time 153426579 ps
CPU time 3.34 seconds
Started Jun 11 12:46:53 PM PDT 24
Finished Jun 11 12:46:57 PM PDT 24
Peak memory 224648 kb
Host smart-463e7585-4e39-4391-82fc-54c7f93bccf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3074306243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3074306243
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.3627934796
Short name T748
Test name
Test status
Simulation time 18368726297 ps
CPU time 20.92 seconds
Started Jun 11 12:46:44 PM PDT 24
Finished Jun 11 12:47:07 PM PDT 24
Peak memory 233124 kb
Host smart-7bdd0249-7cbd-4abd-9a2c-37e7ac3d1939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627934796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.3627934796
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.2930867622
Short name T123
Test name
Test status
Simulation time 417772668 ps
CPU time 3.59 seconds
Started Jun 11 12:47:09 PM PDT 24
Finished Jun 11 12:47:15 PM PDT 24
Peak memory 232980 kb
Host smart-38ae4b78-2942-4cac-9d9f-a3d95f1402ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930867622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2930867622
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.3844417522
Short name T716
Test name
Test status
Simulation time 109653868 ps
CPU time 4.02 seconds
Started Jun 11 12:46:54 PM PDT 24
Finished Jun 11 12:47:00 PM PDT 24
Peak memory 222212 kb
Host smart-506280a9-c819-4383-97cd-6088d7271202
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3844417522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.3844417522
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.26482974
Short name T313
Test name
Test status
Simulation time 2059204639 ps
CPU time 21.37 seconds
Started Jun 11 12:47:00 PM PDT 24
Finished Jun 11 12:47:25 PM PDT 24
Peak memory 219532 kb
Host smart-e6433b2a-1b30-400f-8b57-3b5321903953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26482974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.26482974
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.3096054395
Short name T882
Test name
Test status
Simulation time 5250328856 ps
CPU time 13.21 seconds
Started Jun 11 12:47:00 PM PDT 24
Finished Jun 11 12:47:16 PM PDT 24
Peak memory 216660 kb
Host smart-ef902a84-cc72-4022-be53-e5e789ae8c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096054395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.3096054395
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.3469649433
Short name T934
Test name
Test status
Simulation time 119554773 ps
CPU time 1.58 seconds
Started Jun 11 12:46:58 PM PDT 24
Finished Jun 11 12:47:03 PM PDT 24
Peak memory 216616 kb
Host smart-3c09f708-fc9b-4e68-976d-52d42859bd68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469649433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.3469649433
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.1026780378
Short name T344
Test name
Test status
Simulation time 83264771 ps
CPU time 0.79 seconds
Started Jun 11 12:46:56 PM PDT 24
Finished Jun 11 12:47:00 PM PDT 24
Peak memory 206184 kb
Host smart-3dfd0c57-42a0-4020-aebd-2226f462fd66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026780378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.1026780378
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.2075651369
Short name T902
Test name
Test status
Simulation time 229918380 ps
CPU time 5.68 seconds
Started Jun 11 12:46:50 PM PDT 24
Finished Jun 11 12:46:58 PM PDT 24
Peak memory 240864 kb
Host smart-8f9f45bf-0edd-46bd-82d6-a5c7b3deb871
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075651369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.2075651369
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.4218783341
Short name T443
Test name
Test status
Simulation time 18855796 ps
CPU time 0.7 seconds
Started Jun 11 12:46:59 PM PDT 24
Finished Jun 11 12:47:03 PM PDT 24
Peak memory 205164 kb
Host smart-4c9a15e6-a170-41cb-8e0d-7d0060d3946d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218783341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
4218783341
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.644920819
Short name T697
Test name
Test status
Simulation time 2309284501 ps
CPU time 22.96 seconds
Started Jun 11 12:47:03 PM PDT 24
Finished Jun 11 12:47:29 PM PDT 24
Peak memory 233092 kb
Host smart-9aa39b67-ed0d-4b3d-9913-6e131c78abbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644920819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.644920819
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.2073818844
Short name T836
Test name
Test status
Simulation time 16360939 ps
CPU time 0.76 seconds
Started Jun 11 12:46:56 PM PDT 24
Finished Jun 11 12:46:59 PM PDT 24
Peak memory 206160 kb
Host smart-11f30827-2382-4284-8856-9bd4228f5fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073818844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2073818844
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.2287843011
Short name T437
Test name
Test status
Simulation time 29242802229 ps
CPU time 213.7 seconds
Started Jun 11 12:47:01 PM PDT 24
Finished Jun 11 12:50:38 PM PDT 24
Peak memory 249464 kb
Host smart-2c6e0549-446f-4d0a-bf02-2dff4eee2a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287843011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.2287843011
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.1717687029
Short name T706
Test name
Test status
Simulation time 72784782190 ps
CPU time 162.73 seconds
Started Jun 11 12:47:16 PM PDT 24
Finished Jun 11 12:50:01 PM PDT 24
Peak memory 249560 kb
Host smart-83521271-3cda-4997-a75f-ac73eb3597ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717687029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.1717687029
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.2206459659
Short name T879
Test name
Test status
Simulation time 7114189985 ps
CPU time 44.35 seconds
Started Jun 11 12:47:11 PM PDT 24
Finished Jun 11 12:47:58 PM PDT 24
Peak memory 223216 kb
Host smart-708bea34-37dd-4969-b4a7-379ffab58827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206459659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.2206459659
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.4026785101
Short name T888
Test name
Test status
Simulation time 2459621998 ps
CPU time 19.46 seconds
Started Jun 11 12:46:55 PM PDT 24
Finished Jun 11 12:47:17 PM PDT 24
Peak memory 240624 kb
Host smart-56c093d4-3036-4b7b-b6ae-920a72ebd56f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026785101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.4026785101
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1004732128
Short name T803
Test name
Test status
Simulation time 87579902 ps
CPU time 2.53 seconds
Started Jun 11 12:46:56 PM PDT 24
Finished Jun 11 12:47:01 PM PDT 24
Peak memory 224740 kb
Host smart-f7733f42-ad1b-4a2b-82d6-e7700fc06415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1004732128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1004732128
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.2094493592
Short name T264
Test name
Test status
Simulation time 8504257899 ps
CPU time 22.32 seconds
Started Jun 11 12:47:00 PM PDT 24
Finished Jun 11 12:47:25 PM PDT 24
Peak memory 233120 kb
Host smart-c2ac5819-6968-4084-bf45-0abd5b0621bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094493592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.2094493592
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2384430306
Short name T745
Test name
Test status
Simulation time 1329147383 ps
CPU time 2.04 seconds
Started Jun 11 12:46:54 PM PDT 24
Finished Jun 11 12:46:57 PM PDT 24
Peak memory 223472 kb
Host smart-316eb721-57e6-4dbf-b976-1a02f3f1f2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384430306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2384430306
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.489636378
Short name T474
Test name
Test status
Simulation time 127908721 ps
CPU time 2.61 seconds
Started Jun 11 12:47:00 PM PDT 24
Finished Jun 11 12:47:06 PM PDT 24
Peak memory 232788 kb
Host smart-664edc7d-0279-4f2c-a3f3-c6098174de3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489636378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.489636378
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.521623330
Short name T361
Test name
Test status
Simulation time 389787578 ps
CPU time 3.39 seconds
Started Jun 11 12:47:00 PM PDT 24
Finished Jun 11 12:47:07 PM PDT 24
Peak memory 219316 kb
Host smart-e9560fcd-fb63-4fba-b5ab-98809357de92
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=521623330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dire
ct.521623330
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.2240990922
Short name T145
Test name
Test status
Simulation time 172037796556 ps
CPU time 160.73 seconds
Started Jun 11 12:46:57 PM PDT 24
Finished Jun 11 12:49:41 PM PDT 24
Peak memory 249552 kb
Host smart-32d12e8f-a314-4d12-a554-3017e0f661b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240990922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.2240990922
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.472605306
Short name T692
Test name
Test status
Simulation time 7997295331 ps
CPU time 21.2 seconds
Started Jun 11 12:46:49 PM PDT 24
Finished Jun 11 12:47:12 PM PDT 24
Peak memory 216632 kb
Host smart-75fad78e-c692-4b6d-ac10-c7704ddfa420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472605306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.472605306
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.2863857779
Short name T356
Test name
Test status
Simulation time 30908650995 ps
CPU time 20.06 seconds
Started Jun 11 12:46:55 PM PDT 24
Finished Jun 11 12:47:17 PM PDT 24
Peak memory 216724 kb
Host smart-2f595abf-80b2-4e83-af50-50100b9f3e60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2863857779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.2863857779
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.2373144254
Short name T530
Test name
Test status
Simulation time 47650519 ps
CPU time 0.83 seconds
Started Jun 11 12:46:47 PM PDT 24
Finished Jun 11 12:46:50 PM PDT 24
Peak memory 207072 kb
Host smart-e2ac362a-4bea-4f95-9be6-f9df83a4b3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373144254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2373144254
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.4009395010
Short name T925
Test name
Test status
Simulation time 18842105 ps
CPU time 0.77 seconds
Started Jun 11 12:46:51 PM PDT 24
Finished Jun 11 12:46:53 PM PDT 24
Peak memory 206140 kb
Host smart-ffb3247d-1014-4f17-bdd3-f7f283ff4019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009395010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.4009395010
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.3666099916
Short name T507
Test name
Test status
Simulation time 222573363 ps
CPU time 2.72 seconds
Started Jun 11 12:46:55 PM PDT 24
Finished Jun 11 12:47:00 PM PDT 24
Peak memory 224712 kb
Host smart-33873e6e-2c22-49fe-b4b2-f39f5acf25d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666099916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3666099916
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.2973297068
Short name T805
Test name
Test status
Simulation time 47982029 ps
CPU time 0.74 seconds
Started Jun 11 12:46:57 PM PDT 24
Finished Jun 11 12:47:01 PM PDT 24
Peak memory 205596 kb
Host smart-ab159cd5-3189-40ee-b82b-8d6394dfae5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973297068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
2973297068
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.3080546990
Short name T408
Test name
Test status
Simulation time 51233241 ps
CPU time 2.77 seconds
Started Jun 11 12:46:58 PM PDT 24
Finished Jun 11 12:47:03 PM PDT 24
Peak memory 232896 kb
Host smart-fe48356c-636c-4538-9546-62d6252e5b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080546990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.3080546990
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.1318921231
Short name T591
Test name
Test status
Simulation time 196210675 ps
CPU time 0.76 seconds
Started Jun 11 12:46:52 PM PDT 24
Finished Jun 11 12:46:55 PM PDT 24
Peak memory 206696 kb
Host smart-d7340093-c0f1-48a3-a1aa-1ad86c97f2d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318921231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1318921231
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.231250374
Short name T76
Test name
Test status
Simulation time 6228047251 ps
CPU time 81.21 seconds
Started Jun 11 12:46:50 PM PDT 24
Finished Jun 11 12:48:13 PM PDT 24
Peak memory 255736 kb
Host smart-f26b314d-f46d-49b5-b2c3-7f427ccc04e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231250374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.231250374
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.3249433947
Short name T213
Test name
Test status
Simulation time 8212470560 ps
CPU time 53.99 seconds
Started Jun 11 12:47:00 PM PDT 24
Finished Jun 11 12:47:57 PM PDT 24
Peak memory 257684 kb
Host smart-642575af-2a2a-40c5-a58e-a57096f99565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249433947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.3249433947
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.1020410408
Short name T161
Test name
Test status
Simulation time 9143252299 ps
CPU time 32.6 seconds
Started Jun 11 12:47:01 PM PDT 24
Finished Jun 11 12:47:36 PM PDT 24
Peak memory 241380 kb
Host smart-f67f9283-baea-497c-9da1-3fe0ab282892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1020410408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.1020410408
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.2318284425
Short name T304
Test name
Test status
Simulation time 454584726 ps
CPU time 9.11 seconds
Started Jun 11 12:47:04 PM PDT 24
Finished Jun 11 12:47:16 PM PDT 24
Peak memory 232976 kb
Host smart-ff5a8f26-d5d1-4ebc-b682-1b7ee226c3c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318284425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.2318284425
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.3390756121
Short name T169
Test name
Test status
Simulation time 263895055 ps
CPU time 5.31 seconds
Started Jun 11 12:46:58 PM PDT 24
Finished Jun 11 12:47:06 PM PDT 24
Peak memory 224708 kb
Host smart-0270bdae-d1b8-4361-8f81-1786d20b792e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390756121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3390756121
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.110449132
Short name T430
Test name
Test status
Simulation time 10189876283 ps
CPU time 98.82 seconds
Started Jun 11 12:47:07 PM PDT 24
Finished Jun 11 12:48:49 PM PDT 24
Peak memory 253176 kb
Host smart-0e102239-72b3-4ba6-86e1-14184d91fa8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110449132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.110449132
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.456633698
Short name T574
Test name
Test status
Simulation time 10744545058 ps
CPU time 5.6 seconds
Started Jun 11 12:46:57 PM PDT 24
Finished Jun 11 12:47:06 PM PDT 24
Peak memory 224848 kb
Host smart-350ff76e-95bb-4f07-8b41-9d1cddaf9fc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456633698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap
.456633698
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.1517054628
Short name T524
Test name
Test status
Simulation time 6237215150 ps
CPU time 17.27 seconds
Started Jun 11 12:46:50 PM PDT 24
Finished Jun 11 12:47:09 PM PDT 24
Peak memory 233136 kb
Host smart-0adfa805-069e-40f6-94d4-8c227fc54c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1517054628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1517054628
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.3305484036
Short name T808
Test name
Test status
Simulation time 4891761495 ps
CPU time 30.88 seconds
Started Jun 11 12:46:57 PM PDT 24
Finished Jun 11 12:47:30 PM PDT 24
Peak memory 219508 kb
Host smart-3285c207-a352-4937-9210-95b306b45f17
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3305484036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.3305484036
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.4017682038
Short name T885
Test name
Test status
Simulation time 89592112 ps
CPU time 0.7 seconds
Started Jun 11 12:46:58 PM PDT 24
Finished Jun 11 12:47:02 PM PDT 24
Peak memory 205872 kb
Host smart-c142c05a-091d-4ed2-ba07-a528ec26873f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017682038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.4017682038
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.492421097
Short name T695
Test name
Test status
Simulation time 11373431 ps
CPU time 0.71 seconds
Started Jun 11 12:47:05 PM PDT 24
Finished Jun 11 12:47:08 PM PDT 24
Peak memory 205960 kb
Host smart-81112788-d0c2-43d3-849e-51ba7caa2865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492421097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.492421097
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.2459504207
Short name T753
Test name
Test status
Simulation time 22826822 ps
CPU time 1.42 seconds
Started Jun 11 12:47:04 PM PDT 24
Finished Jun 11 12:47:08 PM PDT 24
Peak memory 216804 kb
Host smart-99c69d58-b5ae-4964-9304-1100c400fd89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459504207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.2459504207
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.459150437
Short name T764
Test name
Test status
Simulation time 83119184 ps
CPU time 0.96 seconds
Started Jun 11 12:46:58 PM PDT 24
Finished Jun 11 12:47:02 PM PDT 24
Peak memory 206136 kb
Host smart-eb257aa8-5fb0-4326-85f4-66b0d6f93849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459150437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.459150437
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.1180382820
Short name T272
Test name
Test status
Simulation time 7776944139 ps
CPU time 10.15 seconds
Started Jun 11 12:46:58 PM PDT 24
Finished Jun 11 12:47:11 PM PDT 24
Peak memory 223844 kb
Host smart-91a5fab8-4936-4f3d-97d9-446ac4d6bd12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180382820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1180382820
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.593982396
Short name T643
Test name
Test status
Simulation time 17087356 ps
CPU time 0.72 seconds
Started Jun 11 12:45:38 PM PDT 24
Finished Jun 11 12:45:43 PM PDT 24
Peak memory 205752 kb
Host smart-24f77da6-66b2-420e-8ac7-efb35d86f68d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593982396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.593982396
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.1884535263
Short name T674
Test name
Test status
Simulation time 2873689188 ps
CPU time 5.48 seconds
Started Jun 11 12:45:28 PM PDT 24
Finished Jun 11 12:45:36 PM PDT 24
Peak memory 224832 kb
Host smart-9987404d-33a8-41d6-bf8b-98f4c251c965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884535263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.1884535263
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.409830007
Short name T317
Test name
Test status
Simulation time 14955384 ps
CPU time 0.75 seconds
Started Jun 11 12:45:39 PM PDT 24
Finished Jun 11 12:45:44 PM PDT 24
Peak memory 205840 kb
Host smart-73156451-29e3-4436-bcd3-3a2d1d6298d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409830007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.409830007
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.218440122
Short name T673
Test name
Test status
Simulation time 2229800332 ps
CPU time 39.74 seconds
Started Jun 11 12:45:36 PM PDT 24
Finished Jun 11 12:46:20 PM PDT 24
Peak memory 249452 kb
Host smart-707a152d-c6b6-4819-9f69-ab7d29a9397d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218440122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.218440122
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.3541914195
Short name T46
Test name
Test status
Simulation time 93583829448 ps
CPU time 103.66 seconds
Started Jun 11 12:45:49 PM PDT 24
Finished Jun 11 12:47:35 PM PDT 24
Peak memory 251880 kb
Host smart-8cb4ae93-a152-4986-9461-016c46e9f4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3541914195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.3541914195
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.3782807565
Short name T412
Test name
Test status
Simulation time 1885061890 ps
CPU time 29.52 seconds
Started Jun 11 12:45:56 PM PDT 24
Finished Jun 11 12:46:27 PM PDT 24
Peak memory 250112 kb
Host smart-cb025d73-b44c-4a2c-bd6e-1023e67d1d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782807565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.3782807565
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.3046371786
Short name T660
Test name
Test status
Simulation time 584755467 ps
CPU time 4.68 seconds
Started Jun 11 12:45:34 PM PDT 24
Finished Jun 11 12:45:41 PM PDT 24
Peak memory 224636 kb
Host smart-433c664f-67e5-4bc3-99ca-068c7fec19ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046371786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3046371786
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.3245156960
Short name T631
Test name
Test status
Simulation time 8676306795 ps
CPU time 67.71 seconds
Started Jun 11 12:45:34 PM PDT 24
Finished Jun 11 12:46:44 PM PDT 24
Peak memory 249580 kb
Host smart-a4be4ad6-9ebe-4611-a795-f2b3d7183c43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245156960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.3245156960
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2172779840
Short name T261
Test name
Test status
Simulation time 10192976556 ps
CPU time 29.64 seconds
Started Jun 11 12:45:31 PM PDT 24
Finished Jun 11 12:46:03 PM PDT 24
Peak memory 232944 kb
Host smart-e0602eef-4e30-4b0a-8364-9bab5b69b3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172779840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.2172779840
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.171763672
Short name T765
Test name
Test status
Simulation time 662749259 ps
CPU time 2.28 seconds
Started Jun 11 12:45:30 PM PDT 24
Finished Jun 11 12:45:34 PM PDT 24
Peak memory 224600 kb
Host smart-3030818e-16b6-4c29-a20d-c315b5ff6081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171763672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.171763672
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.1890009161
Short name T595
Test name
Test status
Simulation time 393896938 ps
CPU time 4.58 seconds
Started Jun 11 12:45:38 PM PDT 24
Finished Jun 11 12:45:47 PM PDT 24
Peak memory 219564 kb
Host smart-c70c334a-e6e0-4ad5-9f12-92c4cce4e142
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1890009161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.1890009161
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.3995971043
Short name T66
Test name
Test status
Simulation time 103397553 ps
CPU time 0.97 seconds
Started Jun 11 12:45:37 PM PDT 24
Finished Jun 11 12:45:42 PM PDT 24
Peak memory 236120 kb
Host smart-8753f7e7-cd50-4d1d-87d8-c7648df9f0a0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995971043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.3995971043
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.1160731575
Short name T222
Test name
Test status
Simulation time 51933309276 ps
CPU time 522.01 seconds
Started Jun 11 12:45:39 PM PDT 24
Finished Jun 11 12:54:26 PM PDT 24
Peak memory 270932 kb
Host smart-69f0ada9-8ae3-4b58-b01e-1a40c75f13c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160731575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.1160731575
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.748701911
Short name T462
Test name
Test status
Simulation time 3550785699 ps
CPU time 10.92 seconds
Started Jun 11 12:45:33 PM PDT 24
Finished Jun 11 12:45:47 PM PDT 24
Peak memory 217056 kb
Host smart-0e88636f-efdb-4b6a-ac70-5b8fc6e3a7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748701911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.748701911
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3149496487
Short name T371
Test name
Test status
Simulation time 1690439705 ps
CPU time 8.47 seconds
Started Jun 11 12:45:24 PM PDT 24
Finished Jun 11 12:45:35 PM PDT 24
Peak memory 216600 kb
Host smart-b6240b42-46a3-449c-baf3-62deed025ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149496487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3149496487
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.3118032018
Short name T331
Test name
Test status
Simulation time 794622796 ps
CPU time 4.56 seconds
Started Jun 11 12:45:32 PM PDT 24
Finished Jun 11 12:45:40 PM PDT 24
Peak memory 216504 kb
Host smart-7f246631-fe16-4485-8445-d9a0b440a3a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118032018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3118032018
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.2371680871
Short name T866
Test name
Test status
Simulation time 160012846 ps
CPU time 0.83 seconds
Started Jun 11 12:45:32 PM PDT 24
Finished Jun 11 12:45:35 PM PDT 24
Peak memory 206064 kb
Host smart-2c3932d8-dfb5-4fa1-89fb-7b90b1248703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371680871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.2371680871
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.505026396
Short name T477
Test name
Test status
Simulation time 84328754 ps
CPU time 2 seconds
Started Jun 11 12:45:32 PM PDT 24
Finished Jun 11 12:45:37 PM PDT 24
Peak memory 223700 kb
Host smart-f0aab084-12d7-42da-aa79-29862f429b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505026396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.505026396
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.2866362318
Short name T354
Test name
Test status
Simulation time 18362964 ps
CPU time 0.74 seconds
Started Jun 11 12:47:19 PM PDT 24
Finished Jun 11 12:47:23 PM PDT 24
Peak memory 206060 kb
Host smart-4b480560-c736-46c2-a25b-e713890c74e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866362318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
2866362318
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.1218527202
Short name T671
Test name
Test status
Simulation time 85403445 ps
CPU time 2.73 seconds
Started Jun 11 12:46:59 PM PDT 24
Finished Jun 11 12:47:05 PM PDT 24
Peak memory 233012 kb
Host smart-60e25685-8117-4e40-a5a3-d4580d5864e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218527202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1218527202
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.2741863582
Short name T856
Test name
Test status
Simulation time 26411941 ps
CPU time 0.79 seconds
Started Jun 11 12:47:00 PM PDT 24
Finished Jun 11 12:47:04 PM PDT 24
Peak memory 206808 kb
Host smart-4152b713-8431-44e5-bb6e-44677921f00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741863582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.2741863582
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.1746806768
Short name T622
Test name
Test status
Simulation time 20263176671 ps
CPU time 80.01 seconds
Started Jun 11 12:46:59 PM PDT 24
Finished Jun 11 12:48:22 PM PDT 24
Peak memory 250452 kb
Host smart-60f7add7-6919-4386-a065-ab43612a099a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746806768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.1746806768
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.3161544104
Short name T58
Test name
Test status
Simulation time 14624821849 ps
CPU time 104.13 seconds
Started Jun 11 12:47:01 PM PDT 24
Finished Jun 11 12:48:48 PM PDT 24
Peak memory 255908 kb
Host smart-fb954499-8578-4d47-a5d3-a15bf2f703ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161544104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.3161544104
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.2539109996
Short name T235
Test name
Test status
Simulation time 20404816704 ps
CPU time 95.16 seconds
Started Jun 11 12:46:59 PM PDT 24
Finished Jun 11 12:48:37 PM PDT 24
Peak memory 265700 kb
Host smart-6c9709c0-72b8-4b47-a27b-f3f8cf26ec29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539109996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.2539109996
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.1747764014
Short name T133
Test name
Test status
Simulation time 1545253212 ps
CPU time 24.3 seconds
Started Jun 11 12:47:01 PM PDT 24
Finished Jun 11 12:47:28 PM PDT 24
Peak memory 232968 kb
Host smart-3f639027-2fd2-459d-b39c-c73705d38e10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747764014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.1747764014
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.43098984
Short name T714
Test name
Test status
Simulation time 339790435 ps
CPU time 3.49 seconds
Started Jun 11 12:47:04 PM PDT 24
Finished Jun 11 12:47:10 PM PDT 24
Peak memory 224756 kb
Host smart-fb2afd07-0b87-4304-8d07-91eda85a776f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43098984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.43098984
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.2164148256
Short name T419
Test name
Test status
Simulation time 131355442 ps
CPU time 2.53 seconds
Started Jun 11 12:46:52 PM PDT 24
Finished Jun 11 12:46:56 PM PDT 24
Peak memory 227208 kb
Host smart-7c0bb0bf-d1bd-4f4c-89a5-4fc13e437d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164148256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.2164148256
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.346735757
Short name T839
Test name
Test status
Simulation time 1512900496 ps
CPU time 6.27 seconds
Started Jun 11 12:46:53 PM PDT 24
Finished Jun 11 12:47:01 PM PDT 24
Peak memory 233012 kb
Host smart-f594e9e4-e54e-4821-9962-a118f687bddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346735757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap
.346735757
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.1021731092
Short name T654
Test name
Test status
Simulation time 1379870637 ps
CPU time 3.86 seconds
Started Jun 11 12:46:52 PM PDT 24
Finished Jun 11 12:46:58 PM PDT 24
Peak memory 224700 kb
Host smart-cc7feece-d14a-4f62-9a4e-1c4ced853614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021731092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.1021731092
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.63054606
Short name T546
Test name
Test status
Simulation time 478684011 ps
CPU time 6.27 seconds
Started Jun 11 12:47:05 PM PDT 24
Finished Jun 11 12:47:14 PM PDT 24
Peak memory 223304 kb
Host smart-79db00da-509f-4daf-b6a1-7cad81abe557
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=63054606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_direc
t.63054606
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.3775931346
Short name T391
Test name
Test status
Simulation time 1326892470 ps
CPU time 22.34 seconds
Started Jun 11 12:47:00 PM PDT 24
Finished Jun 11 12:47:26 PM PDT 24
Peak memory 216528 kb
Host smart-f1bc1193-b08a-40ae-81ab-7c94f3ccbbf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775931346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.3775931346
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.1106528271
Short name T454
Test name
Test status
Simulation time 35212060755 ps
CPU time 13.6 seconds
Started Jun 11 12:46:58 PM PDT 24
Finished Jun 11 12:47:14 PM PDT 24
Peak memory 217828 kb
Host smart-33606491-f0a6-4e22-b2b9-1339ac63a9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1106528271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.1106528271
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.3878719386
Short name T409
Test name
Test status
Simulation time 775154799 ps
CPU time 1.7 seconds
Started Jun 11 12:47:14 PM PDT 24
Finished Jun 11 12:47:18 PM PDT 24
Peak memory 216556 kb
Host smart-c463f8ea-29bd-4a6f-b209-c092127151d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878719386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.3878719386
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3487238634
Short name T155
Test name
Test status
Simulation time 92021446 ps
CPU time 0.73 seconds
Started Jun 11 12:47:00 PM PDT 24
Finished Jun 11 12:47:03 PM PDT 24
Peak memory 206172 kb
Host smart-dae3c1f7-0aa2-49be-abe5-68828cdf71bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487238634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3487238634
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.1048286762
Short name T396
Test name
Test status
Simulation time 177485834 ps
CPU time 2.55 seconds
Started Jun 11 12:47:02 PM PDT 24
Finished Jun 11 12:47:12 PM PDT 24
Peak memory 232792 kb
Host smart-2ef01ba4-a47b-4bd9-a013-68f9756dda39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1048286762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1048286762
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.1583918664
Short name T360
Test name
Test status
Simulation time 31852740 ps
CPU time 0.71 seconds
Started Jun 11 12:47:02 PM PDT 24
Finished Jun 11 12:47:06 PM PDT 24
Peak memory 205740 kb
Host smart-9adb1143-5c4a-48ef-ae45-104c694b9f80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583918664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
1583918664
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.2329669674
Short name T492
Test name
Test status
Simulation time 4751684288 ps
CPU time 13.15 seconds
Started Jun 11 12:47:11 PM PDT 24
Finished Jun 11 12:47:27 PM PDT 24
Peak memory 233124 kb
Host smart-5f503823-75a5-4a6c-93e9-57cade087b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329669674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.2329669674
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.1897672639
Short name T898
Test name
Test status
Simulation time 27389753 ps
CPU time 0.84 seconds
Started Jun 11 12:46:54 PM PDT 24
Finished Jun 11 12:46:56 PM PDT 24
Peak memory 207200 kb
Host smart-7ff5f2e9-1b56-463b-8cb2-5c84887e2941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897672639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1897672639
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.3729376413
Short name T422
Test name
Test status
Simulation time 7039281789 ps
CPU time 46.35 seconds
Started Jun 11 12:47:03 PM PDT 24
Finished Jun 11 12:47:52 PM PDT 24
Peak memory 249572 kb
Host smart-0424add4-7cb2-4721-88cf-13ceb3cfa4d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729376413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.3729376413
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.2286790178
Short name T180
Test name
Test status
Simulation time 6098654287 ps
CPU time 112.66 seconds
Started Jun 11 12:46:53 PM PDT 24
Finished Jun 11 12:48:47 PM PDT 24
Peak memory 256924 kb
Host smart-0065c5cf-4143-4979-9b25-b2bd46731622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286790178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.2286790178
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.2112211245
Short name T921
Test name
Test status
Simulation time 13255857282 ps
CPU time 30.32 seconds
Started Jun 11 12:47:04 PM PDT 24
Finished Jun 11 12:47:37 PM PDT 24
Peak memory 241280 kb
Host smart-eba3baba-17d0-4ceb-bd10-da6bb4bb6cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112211245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2112211245
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.833366373
Short name T482
Test name
Test status
Simulation time 312834620 ps
CPU time 3.15 seconds
Started Jun 11 12:47:04 PM PDT 24
Finished Jun 11 12:47:10 PM PDT 24
Peak memory 224640 kb
Host smart-de1d0ab1-8673-4016-a041-759ce445daf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833366373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.833366373
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2989274294
Short name T392
Test name
Test status
Simulation time 3628791926 ps
CPU time 12.3 seconds
Started Jun 11 12:46:58 PM PDT 24
Finished Jun 11 12:47:14 PM PDT 24
Peak memory 240876 kb
Host smart-2f30f2a0-037e-4108-9e31-d5ea3cd4c499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989274294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2989274294
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.388635391
Short name T737
Test name
Test status
Simulation time 5590969994 ps
CPU time 7.32 seconds
Started Jun 11 12:47:09 PM PDT 24
Finished Jun 11 12:47:19 PM PDT 24
Peak memory 224856 kb
Host smart-600b6822-3a14-4eb9-87f7-ba4c39efe2f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388635391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap
.388635391
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.385332748
Short name T533
Test name
Test status
Simulation time 1150145484 ps
CPU time 4.49 seconds
Started Jun 11 12:47:00 PM PDT 24
Finished Jun 11 12:47:07 PM PDT 24
Peak memory 232976 kb
Host smart-18fdb1da-5d92-4751-9c06-86a10c1cf1fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=385332748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.385332748
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.1364193182
Short name T731
Test name
Test status
Simulation time 2976571387 ps
CPU time 10.91 seconds
Started Jun 11 12:47:04 PM PDT 24
Finished Jun 11 12:47:17 PM PDT 24
Peak memory 222788 kb
Host smart-827ea89f-57f1-48d6-8e53-62396d1caddd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1364193182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.1364193182
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.774335694
Short name T224
Test name
Test status
Simulation time 149270086607 ps
CPU time 309.29 seconds
Started Jun 11 12:46:55 PM PDT 24
Finished Jun 11 12:52:07 PM PDT 24
Peak memory 274160 kb
Host smart-779fe54d-43dd-4a9f-8546-b5ea2ce48196
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774335694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stres
s_all.774335694
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.637794322
Short name T312
Test name
Test status
Simulation time 1647217070 ps
CPU time 5.2 seconds
Started Jun 11 12:47:02 PM PDT 24
Finished Jun 11 12:47:10 PM PDT 24
Peak memory 216660 kb
Host smart-9d3975d3-c1e1-4b56-adbe-75251d141b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637794322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.637794322
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.332513842
Short name T339
Test name
Test status
Simulation time 832316322 ps
CPU time 6.21 seconds
Started Jun 11 12:47:04 PM PDT 24
Finished Jun 11 12:47:13 PM PDT 24
Peak memory 216440 kb
Host smart-3ca5cae0-0b57-4f11-b261-717a2d56c1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332513842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.332513842
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.3380795301
Short name T343
Test name
Test status
Simulation time 10848365 ps
CPU time 0.7 seconds
Started Jun 11 12:46:55 PM PDT 24
Finished Jun 11 12:46:58 PM PDT 24
Peak memory 205904 kb
Host smart-20a799ce-b412-4807-bd4a-b40b772b0bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380795301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3380795301
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.4120761228
Short name T395
Test name
Test status
Simulation time 20005749 ps
CPU time 0.74 seconds
Started Jun 11 12:47:00 PM PDT 24
Finished Jun 11 12:47:04 PM PDT 24
Peak memory 206168 kb
Host smart-c3e217ec-260b-4e3f-9e5c-91987fff69d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120761228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.4120761228
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.713028628
Short name T188
Test name
Test status
Simulation time 12524089509 ps
CPU time 25.27 seconds
Started Jun 11 12:47:03 PM PDT 24
Finished Jun 11 12:47:31 PM PDT 24
Peak memory 233128 kb
Host smart-9179ebb7-951d-4063-adcc-1180fd7ec2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713028628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.713028628
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.793860899
Short name T873
Test name
Test status
Simulation time 40475111 ps
CPU time 0.73 seconds
Started Jun 11 12:47:03 PM PDT 24
Finished Jun 11 12:47:07 PM PDT 24
Peak memory 205144 kb
Host smart-ca4e9cfc-f0b7-4511-b5f8-e127ffbed0cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793860899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.793860899
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.1240328065
Short name T644
Test name
Test status
Simulation time 55527758 ps
CPU time 2.67 seconds
Started Jun 11 12:47:10 PM PDT 24
Finished Jun 11 12:47:16 PM PDT 24
Peak memory 232912 kb
Host smart-5ce9e293-91f4-4c0c-bb66-2c5084bcf4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240328065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.1240328065
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.3267680825
Short name T404
Test name
Test status
Simulation time 19822344 ps
CPU time 0.83 seconds
Started Jun 11 12:47:08 PM PDT 24
Finished Jun 11 12:47:12 PM PDT 24
Peak memory 207172 kb
Host smart-724cf341-d2cf-4afa-9d80-bbc9a152d480
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3267680825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3267680825
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.3782711759
Short name T490
Test name
Test status
Simulation time 24867380281 ps
CPU time 102.47 seconds
Started Jun 11 12:47:00 PM PDT 24
Finished Jun 11 12:48:46 PM PDT 24
Peak memory 233188 kb
Host smart-1fb69e4d-7180-4f80-bf1a-78061f793e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3782711759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.3782711759
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.770506794
Short name T496
Test name
Test status
Simulation time 55551338503 ps
CPU time 133.73 seconds
Started Jun 11 12:47:05 PM PDT 24
Finished Jun 11 12:49:21 PM PDT 24
Peak memory 240464 kb
Host smart-c016691e-c108-4669-ac10-1ee3491ae333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770506794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle
.770506794
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_intercept.2650716650
Short name T891
Test name
Test status
Simulation time 2510382108 ps
CPU time 14.48 seconds
Started Jun 11 12:47:07 PM PDT 24
Finished Jun 11 12:47:24 PM PDT 24
Peak memory 233100 kb
Host smart-c25ba83f-f3d2-4c06-aea7-3d3bb007376e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650716650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.2650716650
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.3114616164
Short name T121
Test name
Test status
Simulation time 375291045 ps
CPU time 5.52 seconds
Started Jun 11 12:46:57 PM PDT 24
Finished Jun 11 12:47:05 PM PDT 24
Peak memory 233016 kb
Host smart-65efe387-37d4-421d-b9a8-74ceb63a8681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3114616164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.3114616164
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.4274383610
Short name T687
Test name
Test status
Simulation time 1298424793 ps
CPU time 6.18 seconds
Started Jun 11 12:47:05 PM PDT 24
Finished Jun 11 12:47:14 PM PDT 24
Peak memory 232972 kb
Host smart-1d31c40d-aed5-4b58-a02d-f6d7d117d27d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274383610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.4274383610
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1264151271
Short name T53
Test name
Test status
Simulation time 15818050960 ps
CPU time 14.79 seconds
Started Jun 11 12:47:12 PM PDT 24
Finished Jun 11 12:47:29 PM PDT 24
Peak memory 233076 kb
Host smart-d1488029-d0d5-47ca-88ed-b9a0cde22117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264151271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1264151271
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.1513296261
Short name T139
Test name
Test status
Simulation time 765030423 ps
CPU time 4.26 seconds
Started Jun 11 12:47:03 PM PDT 24
Finished Jun 11 12:47:10 PM PDT 24
Peak memory 219956 kb
Host smart-53181445-8fa8-4b9a-bd0b-a7c070303f06
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1513296261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.1513296261
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.930872389
Short name T144
Test name
Test status
Simulation time 59542204 ps
CPU time 1.16 seconds
Started Jun 11 12:46:59 PM PDT 24
Finished Jun 11 12:47:03 PM PDT 24
Peak memory 208092 kb
Host smart-2a4c5f73-405b-4526-b27b-4fceef6313f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930872389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stres
s_all.930872389
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.2089185499
Short name T942
Test name
Test status
Simulation time 4410021633 ps
CPU time 6.1 seconds
Started Jun 11 12:47:10 PM PDT 24
Finished Jun 11 12:47:20 PM PDT 24
Peak memory 216704 kb
Host smart-06eb5d46-bb6a-45ca-8ec9-1b374bb923d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089185499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.2089185499
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.2408352874
Short name T684
Test name
Test status
Simulation time 2541315235 ps
CPU time 8.17 seconds
Started Jun 11 12:46:59 PM PDT 24
Finished Jun 11 12:47:10 PM PDT 24
Peak memory 216484 kb
Host smart-93e8a89d-8274-4998-90df-d7fe0c203c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2408352874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.2408352874
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.4181668551
Short name T372
Test name
Test status
Simulation time 89272853 ps
CPU time 1.13 seconds
Started Jun 11 12:47:04 PM PDT 24
Finished Jun 11 12:47:08 PM PDT 24
Peak memory 207832 kb
Host smart-3d0a8c9b-1fb8-435d-a463-6c9c58fc81c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181668551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.4181668551
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.2402801666
Short name T603
Test name
Test status
Simulation time 11398006 ps
CPU time 0.75 seconds
Started Jun 11 12:47:07 PM PDT 24
Finished Jun 11 12:47:10 PM PDT 24
Peak memory 205856 kb
Host smart-351f90b4-b180-4aa6-b955-614d946d55fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402801666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2402801666
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.3073481969
Short name T632
Test name
Test status
Simulation time 418893885 ps
CPU time 2.49 seconds
Started Jun 11 12:47:03 PM PDT 24
Finished Jun 11 12:47:08 PM PDT 24
Peak memory 232936 kb
Host smart-3b4b7b7d-659b-47f3-a778-72108a5c1bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073481969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.3073481969
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.2083158702
Short name T387
Test name
Test status
Simulation time 14653869 ps
CPU time 0.8 seconds
Started Jun 11 12:47:11 PM PDT 24
Finished Jun 11 12:47:15 PM PDT 24
Peak memory 206076 kb
Host smart-d8054e20-f97b-4c89-af6a-16d1cb501bd3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083158702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
2083158702
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.3181133076
Short name T283
Test name
Test status
Simulation time 469835870 ps
CPU time 6.7 seconds
Started Jun 11 12:46:59 PM PDT 24
Finished Jun 11 12:47:08 PM PDT 24
Peak memory 224628 kb
Host smart-8c53e2de-c0c9-4019-9bbc-de3da479096d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181133076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.3181133076
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.1575890616
Short name T13
Test name
Test status
Simulation time 34335126 ps
CPU time 0.77 seconds
Started Jun 11 12:46:58 PM PDT 24
Finished Jun 11 12:47:01 PM PDT 24
Peak memory 207080 kb
Host smart-f59897a9-3623-4f4f-be4d-bb0edc4a3175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575890616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.1575890616
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.2039603646
Short name T648
Test name
Test status
Simulation time 4608479912 ps
CPU time 40.29 seconds
Started Jun 11 12:47:04 PM PDT 24
Finished Jun 11 12:47:47 PM PDT 24
Peak memory 238868 kb
Host smart-e017757c-12d2-4c39-9181-0ecef037f3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039603646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.2039603646
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.4178400734
Short name T37
Test name
Test status
Simulation time 77384368403 ps
CPU time 574.06 seconds
Started Jun 11 12:47:20 PM PDT 24
Finished Jun 11 12:56:58 PM PDT 24
Peak memory 257708 kb
Host smart-e8f4259c-00ff-4cdb-9b66-875cfe546085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178400734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.4178400734
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.141350518
Short name T278
Test name
Test status
Simulation time 158166684132 ps
CPU time 138.56 seconds
Started Jun 11 12:47:13 PM PDT 24
Finished Jun 11 12:49:34 PM PDT 24
Peak memory 255936 kb
Host smart-a5d5225e-96e1-431e-a2bd-68b57833bdc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141350518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle
.141350518
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.4121986656
Short name T957
Test name
Test status
Simulation time 1039916398 ps
CPU time 16.59 seconds
Started Jun 11 12:47:09 PM PDT 24
Finished Jun 11 12:47:29 PM PDT 24
Peak memory 224796 kb
Host smart-36daa349-f505-4e12-af06-e16b1e590a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121986656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.4121986656
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.2452674248
Short name T575
Test name
Test status
Simulation time 254489176 ps
CPU time 7.78 seconds
Started Jun 11 12:47:03 PM PDT 24
Finished Jun 11 12:47:13 PM PDT 24
Peak memory 232996 kb
Host smart-3fb3d1aa-8d2e-49e6-9e95-cc885f881155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452674248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.2452674248
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.1757773921
Short name T287
Test name
Test status
Simulation time 2639808231 ps
CPU time 7.83 seconds
Started Jun 11 12:47:14 PM PDT 24
Finished Jun 11 12:47:24 PM PDT 24
Peak memory 224856 kb
Host smart-1127ceb9-3856-4d44-b62d-7bf51cc29543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757773921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1757773921
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.1894435556
Short name T582
Test name
Test status
Simulation time 3071311177 ps
CPU time 9.36 seconds
Started Jun 11 12:47:10 PM PDT 24
Finished Jun 11 12:47:23 PM PDT 24
Peak memory 249444 kb
Host smart-e221abfb-a2a5-4ef0-8f75-f1a86948dde6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894435556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.1894435556
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.369368693
Short name T645
Test name
Test status
Simulation time 42384641446 ps
CPU time 22.55 seconds
Started Jun 11 12:47:01 PM PDT 24
Finished Jun 11 12:47:26 PM PDT 24
Peak memory 233040 kb
Host smart-cc9a23eb-3fb6-4d65-9962-04cedff5f357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369368693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.369368693
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1670086670
Short name T592
Test name
Test status
Simulation time 1259745273 ps
CPU time 7.84 seconds
Started Jun 11 12:47:15 PM PDT 24
Finished Jun 11 12:47:25 PM PDT 24
Peak memory 219560 kb
Host smart-2cf1796c-b54e-4c71-b381-3a4419455540
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1670086670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1670086670
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.1485059765
Short name T147
Test name
Test status
Simulation time 97361504839 ps
CPU time 208.32 seconds
Started Jun 11 12:47:03 PM PDT 24
Finished Jun 11 12:50:34 PM PDT 24
Peak memory 255484 kb
Host smart-14a859e9-1b05-4418-9580-54869f1d35e9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485059765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.1485059765
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.3434669033
Short name T563
Test name
Test status
Simulation time 1913390005 ps
CPU time 13.98 seconds
Started Jun 11 12:47:12 PM PDT 24
Finished Jun 11 12:47:29 PM PDT 24
Peak memory 216556 kb
Host smart-40e5f9e5-601d-429a-aadf-8251064afb9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434669033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.3434669033
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.274624408
Short name T619
Test name
Test status
Simulation time 2561166023 ps
CPU time 8.96 seconds
Started Jun 11 12:47:00 PM PDT 24
Finished Jun 11 12:47:12 PM PDT 24
Peak memory 216648 kb
Host smart-c594eb10-95a8-457c-8783-69868664b2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274624408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.274624408
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.2807672033
Short name T869
Test name
Test status
Simulation time 51124259 ps
CPU time 1.05 seconds
Started Jun 11 12:47:13 PM PDT 24
Finished Jun 11 12:47:17 PM PDT 24
Peak memory 208052 kb
Host smart-046e0f5d-e93e-4d6b-87e4-8c156a94c884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807672033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.2807672033
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.2935638603
Short name T790
Test name
Test status
Simulation time 111113361 ps
CPU time 0.95 seconds
Started Jun 11 12:47:19 PM PDT 24
Finished Jun 11 12:47:23 PM PDT 24
Peak memory 207080 kb
Host smart-02df9ac3-167a-4b5f-a87f-b41c4e17456e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935638603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.2935638603
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.3162795886
Short name T801
Test name
Test status
Simulation time 716653681 ps
CPU time 4.78 seconds
Started Jun 11 12:47:07 PM PDT 24
Finished Jun 11 12:47:15 PM PDT 24
Peak memory 232912 kb
Host smart-d8423519-74c4-4c63-8ab8-50b3b0612740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162795886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3162795886
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.3505715116
Short name T886
Test name
Test status
Simulation time 64958404 ps
CPU time 0.76 seconds
Started Jun 11 12:47:12 PM PDT 24
Finished Jun 11 12:47:16 PM PDT 24
Peak memory 206104 kb
Host smart-ae187b07-89a2-49aa-baff-ee954c8e1716
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505715116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
3505715116
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.1202378214
Short name T285
Test name
Test status
Simulation time 885247999 ps
CPU time 5.53 seconds
Started Jun 11 12:47:12 PM PDT 24
Finished Jun 11 12:47:20 PM PDT 24
Peak memory 224708 kb
Host smart-cb50feb8-19d2-431d-87f1-ed666a8efac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202378214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.1202378214
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.2793865732
Short name T457
Test name
Test status
Simulation time 23118808 ps
CPU time 0.82 seconds
Started Jun 11 12:47:15 PM PDT 24
Finished Jun 11 12:47:18 PM PDT 24
Peak memory 207052 kb
Host smart-02bb7f7f-392f-4708-8b15-396531d472ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793865732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.2793865732
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.3875155860
Short name T452
Test name
Test status
Simulation time 39564532606 ps
CPU time 80.19 seconds
Started Jun 11 12:47:09 PM PDT 24
Finished Jun 11 12:48:33 PM PDT 24
Peak memory 257616 kb
Host smart-7e3450b2-97a3-49b8-881a-a7f65452a82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875155860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.3875155860
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.1883514956
Short name T756
Test name
Test status
Simulation time 6380797797 ps
CPU time 34.82 seconds
Started Jun 11 12:47:15 PM PDT 24
Finished Jun 11 12:47:52 PM PDT 24
Peak memory 218132 kb
Host smart-aa04dd35-3a77-4eb7-bc49-c83eeb1a9611
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1883514956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.1883514956
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.3776833468
Short name T897
Test name
Test status
Simulation time 52364010750 ps
CPU time 168.75 seconds
Started Jun 11 12:47:05 PM PDT 24
Finished Jun 11 12:49:56 PM PDT 24
Peak memory 265852 kb
Host smart-46bc650b-77a0-4a87-bb3b-d163854ba9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776833468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.3776833468
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.2578507587
Short name T302
Test name
Test status
Simulation time 786878223 ps
CPU time 6.87 seconds
Started Jun 11 12:47:10 PM PDT 24
Finished Jun 11 12:47:20 PM PDT 24
Peak memory 225000 kb
Host smart-7e222866-2275-4f50-b8ed-2cc511418392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578507587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.2578507587
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.3291018317
Short name T284
Test name
Test status
Simulation time 869000294 ps
CPU time 7.59 seconds
Started Jun 11 12:47:11 PM PDT 24
Finished Jun 11 12:47:21 PM PDT 24
Peak memory 224696 kb
Host smart-3ac84cb4-1a2b-4b99-984f-4f5c15031c5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3291018317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.3291018317
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.1668328664
Short name T922
Test name
Test status
Simulation time 6159778584 ps
CPU time 15.19 seconds
Started Jun 11 12:47:07 PM PDT 24
Finished Jun 11 12:47:25 PM PDT 24
Peak memory 233120 kb
Host smart-419adce2-8f26-40b9-839b-e06c3f7bb2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1668328664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.1668328664
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3705781855
Short name T933
Test name
Test status
Simulation time 5304903103 ps
CPU time 18.18 seconds
Started Jun 11 12:47:16 PM PDT 24
Finished Jun 11 12:47:36 PM PDT 24
Peak memory 249484 kb
Host smart-98289994-30a6-4d3d-adb0-cdc367776068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705781855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3705781855
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.1389391327
Short name T912
Test name
Test status
Simulation time 618748926 ps
CPU time 4.3 seconds
Started Jun 11 12:47:09 PM PDT 24
Finished Jun 11 12:47:16 PM PDT 24
Peak memory 224676 kb
Host smart-496e5704-dba5-4378-b05c-bb50562cb503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389391327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1389391327
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.3230899406
Short name T624
Test name
Test status
Simulation time 1571735025 ps
CPU time 14.19 seconds
Started Jun 11 12:47:16 PM PDT 24
Finished Jun 11 12:47:32 PM PDT 24
Peak memory 223300 kb
Host smart-b08a3a79-c685-4151-a0ef-3d416450699c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3230899406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.3230899406
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.2808683968
Short name T16
Test name
Test status
Simulation time 51239048 ps
CPU time 0.98 seconds
Started Jun 11 12:47:03 PM PDT 24
Finished Jun 11 12:47:07 PM PDT 24
Peak memory 215708 kb
Host smart-bdf03fea-20e2-44f6-9754-732a25b63f89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2808683968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.2808683968
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.1297606658
Short name T726
Test name
Test status
Simulation time 1689964000 ps
CPU time 17.79 seconds
Started Jun 11 12:47:20 PM PDT 24
Finished Jun 11 12:47:42 PM PDT 24
Peak memory 216492 kb
Host smart-ec57b366-c60a-48e6-ac82-d4790cb355df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297606658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.1297606658
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.181441431
Short name T909
Test name
Test status
Simulation time 760789612 ps
CPU time 5.85 seconds
Started Jun 11 12:47:09 PM PDT 24
Finished Jun 11 12:47:18 PM PDT 24
Peak memory 216548 kb
Host smart-a41087a3-05f7-4175-aa02-bef9fdcb57cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181441431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.181441431
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.2813260817
Short name T7
Test name
Test status
Simulation time 122515239 ps
CPU time 0.98 seconds
Started Jun 11 12:47:10 PM PDT 24
Finished Jun 11 12:47:14 PM PDT 24
Peak memory 207576 kb
Host smart-7fcd730c-39b5-4ef0-82d7-6165d261d811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813260817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2813260817
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.989076642
Short name T895
Test name
Test status
Simulation time 56707414 ps
CPU time 0.87 seconds
Started Jun 11 12:47:09 PM PDT 24
Finished Jun 11 12:47:13 PM PDT 24
Peak memory 206176 kb
Host smart-fc8cc4ef-0fe5-473c-ae84-3d41159fbf0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989076642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.989076642
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.695142079
Short name T568
Test name
Test status
Simulation time 595076877 ps
CPU time 7.43 seconds
Started Jun 11 12:47:13 PM PDT 24
Finished Jun 11 12:47:23 PM PDT 24
Peak memory 232880 kb
Host smart-33e457e6-018c-4f2e-ab0c-462eb609eb8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695142079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.695142079
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.3390403302
Short name T663
Test name
Test status
Simulation time 58801829 ps
CPU time 0.71 seconds
Started Jun 11 12:47:18 PM PDT 24
Finished Jun 11 12:47:22 PM PDT 24
Peak memory 205168 kb
Host smart-c20f316d-488b-4849-9c49-96137cdc802b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390403302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
3390403302
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3438322277
Short name T817
Test name
Test status
Simulation time 149856270 ps
CPU time 3.94 seconds
Started Jun 11 12:47:14 PM PDT 24
Finished Jun 11 12:47:20 PM PDT 24
Peak memory 224708 kb
Host smart-5d44c67e-a57b-4659-b366-c0f04545b15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438322277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3438322277
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.451114246
Short name T802
Test name
Test status
Simulation time 59978225 ps
CPU time 0.82 seconds
Started Jun 11 12:47:06 PM PDT 24
Finished Jun 11 12:47:10 PM PDT 24
Peak memory 206948 kb
Host smart-a1888f99-cc18-4547-86cf-18eadc875de7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=451114246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.451114246
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.947894681
Short name T237
Test name
Test status
Simulation time 29678904797 ps
CPU time 190.89 seconds
Started Jun 11 12:47:17 PM PDT 24
Finished Jun 11 12:50:30 PM PDT 24
Peak memory 249344 kb
Host smart-960b2cc7-2455-4b8c-b3d5-a560ed7b7dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947894681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.947894681
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.3640697420
Short name T820
Test name
Test status
Simulation time 26080074611 ps
CPU time 142.19 seconds
Started Jun 11 12:47:07 PM PDT 24
Finished Jun 11 12:49:33 PM PDT 24
Peak memory 249460 kb
Host smart-c0247049-06a7-4376-aa69-06e0aed90db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640697420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.3640697420
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.64523636
Short name T260
Test name
Test status
Simulation time 29323678805 ps
CPU time 98.81 seconds
Started Jun 11 12:47:14 PM PDT 24
Finished Jun 11 12:48:55 PM PDT 24
Peak memory 239220 kb
Host smart-d5519284-1222-4c94-8862-e2258f744aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64523636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle.64523636
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.2791083140
Short name T549
Test name
Test status
Simulation time 225941873 ps
CPU time 8.09 seconds
Started Jun 11 12:47:04 PM PDT 24
Finished Jun 11 12:47:14 PM PDT 24
Peak memory 249388 kb
Host smart-191d4f21-a8bb-4765-a8a0-37c7cb1f9345
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791083140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.2791083140
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.223128716
Short name T928
Test name
Test status
Simulation time 4083424913 ps
CPU time 18.18 seconds
Started Jun 11 12:47:12 PM PDT 24
Finished Jun 11 12:47:33 PM PDT 24
Peak memory 233116 kb
Host smart-6c7aea18-5a44-43d6-a121-cbe2d537c698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223128716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.223128716
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.778514820
Short name T292
Test name
Test status
Simulation time 1614897638 ps
CPU time 16.19 seconds
Started Jun 11 12:47:17 PM PDT 24
Finished Jun 11 12:47:35 PM PDT 24
Peak memory 224732 kb
Host smart-8fe4a4a3-d5c4-4b91-a8f8-293d77bdf891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778514820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.778514820
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.3716316344
Short name T241
Test name
Test status
Simulation time 3619505384 ps
CPU time 9.39 seconds
Started Jun 11 12:47:08 PM PDT 24
Finished Jun 11 12:47:20 PM PDT 24
Peak memory 241020 kb
Host smart-5190db08-2908-492a-9727-9204725d4560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716316344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.3716316344
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2370592132
Short name T823
Test name
Test status
Simulation time 34182435 ps
CPU time 2.11 seconds
Started Jun 11 12:47:09 PM PDT 24
Finished Jun 11 12:47:14 PM PDT 24
Peak memory 224628 kb
Host smart-84099444-00ca-4210-809f-623ba0d87963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2370592132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2370592132
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.1038455527
Short name T459
Test name
Test status
Simulation time 511706702 ps
CPU time 6.64 seconds
Started Jun 11 12:47:18 PM PDT 24
Finished Jun 11 12:47:28 PM PDT 24
Peak memory 221248 kb
Host smart-c2f50f61-e8b0-4192-9122-69cbf774e8d4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1038455527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.1038455527
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3100483744
Short name T570
Test name
Test status
Simulation time 5203077450 ps
CPU time 27.4 seconds
Started Jun 11 12:47:03 PM PDT 24
Finished Jun 11 12:47:33 PM PDT 24
Peak memory 216920 kb
Host smart-edd5fb0a-0238-4ded-a1a4-2ce6fdf5e799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100483744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3100483744
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2878189782
Short name T426
Test name
Test status
Simulation time 39992361 ps
CPU time 0.7 seconds
Started Jun 11 12:47:07 PM PDT 24
Finished Jun 11 12:47:10 PM PDT 24
Peak memory 205880 kb
Host smart-f2d8bbc7-b123-4232-9447-ad07b6b8a1bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878189782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2878189782
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.4265489659
Short name T525
Test name
Test status
Simulation time 130804255 ps
CPU time 3 seconds
Started Jun 11 12:47:25 PM PDT 24
Finished Jun 11 12:47:32 PM PDT 24
Peak memory 216604 kb
Host smart-bff1e3a0-fec1-4cc4-b36a-333bbb7ef562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265489659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.4265489659
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.714252967
Short name T639
Test name
Test status
Simulation time 28119476 ps
CPU time 0.75 seconds
Started Jun 11 12:47:08 PM PDT 24
Finished Jun 11 12:47:11 PM PDT 24
Peak memory 205892 kb
Host smart-58c4a383-1d24-4c82-bbc2-bb97c1f094ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714252967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.714252967
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.3919707432
Short name T669
Test name
Test status
Simulation time 13996961548 ps
CPU time 13.96 seconds
Started Jun 11 12:48:15 PM PDT 24
Finished Jun 11 12:48:31 PM PDT 24
Peak memory 232944 kb
Host smart-b7cf8c05-236d-4d12-b600-5d63c1ab6692
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919707432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.3919707432
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.2582848778
Short name T355
Test name
Test status
Simulation time 13823098 ps
CPU time 0.69 seconds
Started Jun 11 12:47:28 PM PDT 24
Finished Jun 11 12:47:34 PM PDT 24
Peak memory 205676 kb
Host smart-b7a8164d-91b3-4b6c-9567-f9f64d14b604
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582848778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
2582848778
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.2690348888
Short name T834
Test name
Test status
Simulation time 189038352 ps
CPU time 3.52 seconds
Started Jun 11 12:47:14 PM PDT 24
Finished Jun 11 12:47:20 PM PDT 24
Peak memory 232924 kb
Host smart-1a2894b6-19dc-424e-851d-05bc3c3f4f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690348888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2690348888
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.2826614965
Short name T338
Test name
Test status
Simulation time 52738376 ps
CPU time 0.81 seconds
Started Jun 11 12:47:10 PM PDT 24
Finished Jun 11 12:47:13 PM PDT 24
Peak memory 206772 kb
Host smart-07deebf7-fd2a-4fea-8843-3ae18b951458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826614965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.2826614965
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.283907817
Short name T690
Test name
Test status
Simulation time 63478435357 ps
CPU time 230.36 seconds
Started Jun 11 12:47:20 PM PDT 24
Finished Jun 11 12:51:14 PM PDT 24
Peak memory 252632 kb
Host smart-a8491ed0-ad47-4e0c-9ee7-a073a214c191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283907817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.283907817
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.171785727
Short name T679
Test name
Test status
Simulation time 35677958919 ps
CPU time 146.88 seconds
Started Jun 11 12:47:15 PM PDT 24
Finished Jun 11 12:49:44 PM PDT 24
Peak memory 252000 kb
Host smart-a369d063-3594-4f0c-9b10-be845e1221ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171785727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.171785727
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.3544690407
Short name T271
Test name
Test status
Simulation time 141455397645 ps
CPU time 231.27 seconds
Started Jun 11 12:47:26 PM PDT 24
Finished Jun 11 12:51:21 PM PDT 24
Peak memory 251048 kb
Host smart-178d089a-0ddc-47a7-b746-fd417a533ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544690407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.3544690407
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.659145921
Short name T270
Test name
Test status
Simulation time 637220091 ps
CPU time 4.28 seconds
Started Jun 11 12:47:16 PM PDT 24
Finished Jun 11 12:47:23 PM PDT 24
Peak memory 241136 kb
Host smart-217977bd-174e-4a69-a8fb-b123843e0d70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659145921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.659145921
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1813774857
Short name T274
Test name
Test status
Simulation time 2230050067 ps
CPU time 17.82 seconds
Started Jun 11 12:47:20 PM PDT 24
Finished Jun 11 12:47:41 PM PDT 24
Peak memory 225040 kb
Host smart-e1ddde77-3849-42be-a309-8723a213e7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813774857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1813774857
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.2167612609
Short name T92
Test name
Test status
Simulation time 1327555908 ps
CPU time 9.49 seconds
Started Jun 11 12:47:26 PM PDT 24
Finished Jun 11 12:47:39 PM PDT 24
Peak memory 232960 kb
Host smart-ac780b29-0105-4a28-9fa4-2175994d168e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167612609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2167612609
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.2235802273
Short name T927
Test name
Test status
Simulation time 239549670 ps
CPU time 3.06 seconds
Started Jun 11 12:47:16 PM PDT 24
Finished Jun 11 12:47:22 PM PDT 24
Peak memory 232940 kb
Host smart-cebd094f-7dc4-450c-b5f4-d76477edee16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235802273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.2235802273
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.507742035
Short name T72
Test name
Test status
Simulation time 39325528265 ps
CPU time 17.55 seconds
Started Jun 11 12:47:26 PM PDT 24
Finished Jun 11 12:47:48 PM PDT 24
Peak memory 219144 kb
Host smart-3687b166-1566-4347-aa3c-44dc7e903172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507742035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.507742035
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.1974911901
Short name T468
Test name
Test status
Simulation time 1518620341 ps
CPU time 5.32 seconds
Started Jun 11 12:47:22 PM PDT 24
Finished Jun 11 12:47:31 PM PDT 24
Peak memory 222900 kb
Host smart-8eb546dd-46d4-4528-ae69-c4af707a79ba
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1974911901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.1974911901
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.2761620041
Short name T33
Test name
Test status
Simulation time 21263881215 ps
CPU time 230.65 seconds
Started Jun 11 12:47:24 PM PDT 24
Finished Jun 11 12:51:18 PM PDT 24
Peak memory 249596 kb
Host smart-55275c7b-c117-4945-9f01-52a8276b18a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761620041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.2761620041
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.2423439773
Short name T24
Test name
Test status
Simulation time 7303158622 ps
CPU time 13.19 seconds
Started Jun 11 12:47:20 PM PDT 24
Finished Jun 11 12:47:37 PM PDT 24
Peak memory 216600 kb
Host smart-3d801176-e7db-413d-9ca8-6157745b8822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423439773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.2423439773
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.2716746245
Short name T636
Test name
Test status
Simulation time 417364049 ps
CPU time 2.67 seconds
Started Jun 11 12:47:20 PM PDT 24
Finished Jun 11 12:47:27 PM PDT 24
Peak memory 216604 kb
Host smart-f6e3ce6b-2581-4e50-ae0d-af37e74d09c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716746245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2716746245
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.237925710
Short name T816
Test name
Test status
Simulation time 79218792 ps
CPU time 1.72 seconds
Started Jun 11 12:47:25 PM PDT 24
Finished Jun 11 12:47:30 PM PDT 24
Peak memory 216604 kb
Host smart-7a3e6996-3a0e-4e1e-b81f-1e205e62257c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237925710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.237925710
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.4114461433
Short name T325
Test name
Test status
Simulation time 45816093 ps
CPU time 0.81 seconds
Started Jun 11 12:47:20 PM PDT 24
Finished Jun 11 12:47:24 PM PDT 24
Peak memory 206164 kb
Host smart-9643539b-6c9d-4d64-a112-e7f4f2dabad2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114461433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.4114461433
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.2553522296
Short name T346
Test name
Test status
Simulation time 21681576153 ps
CPU time 17.33 seconds
Started Jun 11 12:47:19 PM PDT 24
Finished Jun 11 12:47:39 PM PDT 24
Peak memory 240872 kb
Host smart-eb2777ed-6e76-4c90-bf18-545421b50075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553522296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.2553522296
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.1832563423
Short name T711
Test name
Test status
Simulation time 12841784 ps
CPU time 0.76 seconds
Started Jun 11 12:47:29 PM PDT 24
Finished Jun 11 12:47:35 PM PDT 24
Peak memory 205184 kb
Host smart-0a4f35b4-02a6-4ff6-bbf1-32e562bf42b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832563423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
1832563423
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.1979258274
Short name T201
Test name
Test status
Simulation time 402577711 ps
CPU time 3.27 seconds
Started Jun 11 12:47:11 PM PDT 24
Finished Jun 11 12:47:18 PM PDT 24
Peak memory 224804 kb
Host smart-38af063e-90f4-4c11-9ca7-34b11d1119fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979258274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.1979258274
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.3425969604
Short name T439
Test name
Test status
Simulation time 17813522 ps
CPU time 0.81 seconds
Started Jun 11 12:47:20 PM PDT 24
Finished Jun 11 12:47:25 PM PDT 24
Peak memory 206832 kb
Host smart-a7d881c6-3da2-42b8-8b06-7b1ffc885e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425969604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3425969604
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.333630023
Short name T233
Test name
Test status
Simulation time 3334389067 ps
CPU time 75.75 seconds
Started Jun 11 12:47:20 PM PDT 24
Finished Jun 11 12:48:40 PM PDT 24
Peak memory 249544 kb
Host smart-4afc989b-9a33-47cb-a8cd-29ca79ef6773
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=333630023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle
.333630023
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.846373202
Short name T637
Test name
Test status
Simulation time 28880009871 ps
CPU time 23.85 seconds
Started Jun 11 12:47:23 PM PDT 24
Finished Jun 11 12:47:51 PM PDT 24
Peak memory 241288 kb
Host smart-cac5ce8e-d540-49b9-879d-59704ad06267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846373202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.846373202
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.3619625381
Short name T269
Test name
Test status
Simulation time 1213119756 ps
CPU time 13.65 seconds
Started Jun 11 12:47:25 PM PDT 24
Finished Jun 11 12:47:43 PM PDT 24
Peak memory 224724 kb
Host smart-03656830-5498-439c-a670-9e7278726757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3619625381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3619625381
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.2976946016
Short name T42
Test name
Test status
Simulation time 3323195349 ps
CPU time 21.82 seconds
Started Jun 11 12:47:29 PM PDT 24
Finished Jun 11 12:47:56 PM PDT 24
Peak memory 241004 kb
Host smart-5089ddef-f2dd-4022-be6d-086ee3d2563d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976946016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.2976946016
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3136508543
Short name T615
Test name
Test status
Simulation time 15930961475 ps
CPU time 14.05 seconds
Started Jun 11 12:47:25 PM PDT 24
Finished Jun 11 12:47:43 PM PDT 24
Peak memory 232956 kb
Host smart-5f99582d-3688-44ca-b8e6-aa789f91c6c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136508543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.3136508543
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.1128536444
Short name T610
Test name
Test status
Simulation time 356081639 ps
CPU time 4.58 seconds
Started Jun 11 12:47:17 PM PDT 24
Finished Jun 11 12:47:24 PM PDT 24
Peak memory 224648 kb
Host smart-cac34814-c1ff-437f-989a-188886b859a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128536444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.1128536444
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.293513116
Short name T899
Test name
Test status
Simulation time 87993765 ps
CPU time 3.91 seconds
Started Jun 11 12:47:17 PM PDT 24
Finished Jun 11 12:47:23 PM PDT 24
Peak memory 220796 kb
Host smart-483ef602-9a3a-4284-8075-5d4a0e82a02b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=293513116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dire
ct.293513116
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.1475918841
Short name T21
Test name
Test status
Simulation time 46014030122 ps
CPU time 182.79 seconds
Started Jun 11 12:47:22 PM PDT 24
Finished Jun 11 12:50:28 PM PDT 24
Peak memory 273612 kb
Host smart-e8e27c9d-7d7e-4bfd-a8c3-f11d94125e4b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475918841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.1475918841
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.2747342840
Short name T315
Test name
Test status
Simulation time 6988214250 ps
CPU time 22.88 seconds
Started Jun 11 12:47:29 PM PDT 24
Finished Jun 11 12:47:57 PM PDT 24
Peak memory 216668 kb
Host smart-cc9b2a2a-2ea4-40b3-9858-236d680cf658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747342840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.2747342840
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.4103067161
Short name T890
Test name
Test status
Simulation time 6909031576 ps
CPU time 19.82 seconds
Started Jun 11 12:47:19 PM PDT 24
Finished Jun 11 12:47:42 PM PDT 24
Peak memory 216740 kb
Host smart-03b9ce96-df49-41e4-8b52-f5cd68dbd64e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4103067161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.4103067161
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.1430197168
Short name T556
Test name
Test status
Simulation time 276791702 ps
CPU time 8.32 seconds
Started Jun 11 12:47:23 PM PDT 24
Finished Jun 11 12:47:35 PM PDT 24
Peak memory 216616 kb
Host smart-06418df8-902f-491c-962e-981050060f9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430197168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.1430197168
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.4292179913
Short name T510
Test name
Test status
Simulation time 96969817 ps
CPU time 0.87 seconds
Started Jun 11 12:47:24 PM PDT 24
Finished Jun 11 12:47:29 PM PDT 24
Peak memory 206136 kb
Host smart-f8d6704d-10b3-444e-9569-7c9201f9c4d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292179913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.4292179913
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.3752948454
Short name T390
Test name
Test status
Simulation time 52903037 ps
CPU time 2.17 seconds
Started Jun 11 12:47:33 PM PDT 24
Finished Jun 11 12:47:40 PM PDT 24
Peak memory 224532 kb
Host smart-e0100d83-7d07-4319-a6b3-99e2349905c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752948454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.3752948454
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.395069034
Short name T337
Test name
Test status
Simulation time 12617587 ps
CPU time 0.72 seconds
Started Jun 11 12:47:26 PM PDT 24
Finished Jun 11 12:47:31 PM PDT 24
Peak memory 205140 kb
Host smart-33bc6c15-72aa-4d52-a635-8951a33b62d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395069034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.395069034
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.953640970
Short name T86
Test name
Test status
Simulation time 3979150505 ps
CPU time 8.67 seconds
Started Jun 11 12:47:25 PM PDT 24
Finished Jun 11 12:47:37 PM PDT 24
Peak memory 233068 kb
Host smart-5469ea64-496f-493c-8cbd-d4cecf09ad5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953640970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.953640970
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.2803744273
Short name T708
Test name
Test status
Simulation time 33519149 ps
CPU time 0.79 seconds
Started Jun 11 12:47:20 PM PDT 24
Finished Jun 11 12:47:25 PM PDT 24
Peak memory 206848 kb
Host smart-3b85ba7d-6f85-4304-985d-2e4d82dd543c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803744273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2803744273
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.1708778868
Short name T425
Test name
Test status
Simulation time 26161409932 ps
CPU time 44.28 seconds
Started Jun 11 12:47:20 PM PDT 24
Finished Jun 11 12:48:08 PM PDT 24
Peak memory 224808 kb
Host smart-a4922f8b-71bf-4434-a964-26cb5073dc79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708778868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.1708778868
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.409278444
Short name T166
Test name
Test status
Simulation time 62519729664 ps
CPU time 111.52 seconds
Started Jun 11 12:47:10 PM PDT 24
Finished Jun 11 12:49:04 PM PDT 24
Peak memory 256020 kb
Host smart-b7330f86-8ece-405d-b47f-591bf38c3900
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409278444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.409278444
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.4019831228
Short name T209
Test name
Test status
Simulation time 33567608719 ps
CPU time 286.72 seconds
Started Jun 11 12:47:35 PM PDT 24
Finished Jun 11 12:52:26 PM PDT 24
Peak memory 265616 kb
Host smart-963f9e7b-a463-400b-9052-cb39526d9be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019831228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.4019831228
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.2883109333
Short name T905
Test name
Test status
Simulation time 1061326631 ps
CPU time 6.72 seconds
Started Jun 11 12:47:23 PM PDT 24
Finished Jun 11 12:47:33 PM PDT 24
Peak memory 232992 kb
Host smart-7a489536-c171-4c6e-96c0-0371ad0ce2ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883109333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2883109333
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.490042379
Short name T521
Test name
Test status
Simulation time 326657257 ps
CPU time 3.58 seconds
Started Jun 11 12:47:25 PM PDT 24
Finished Jun 11 12:47:32 PM PDT 24
Peak memory 232872 kb
Host smart-3c7d246d-dd1c-4f56-9944-644d876202da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490042379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.490042379
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.4203155400
Short name T704
Test name
Test status
Simulation time 524503408 ps
CPU time 2.78 seconds
Started Jun 11 12:47:21 PM PDT 24
Finished Jun 11 12:47:28 PM PDT 24
Peak memory 224704 kb
Host smart-bb8ba2cb-a0e8-4ac1-a297-e37215d5f777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203155400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.4203155400
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2596695012
Short name T750
Test name
Test status
Simulation time 12822722374 ps
CPU time 20.6 seconds
Started Jun 11 12:47:27 PM PDT 24
Finished Jun 11 12:47:51 PM PDT 24
Peak memory 240980 kb
Host smart-0784aa2f-1d08-4193-bb6b-acec7ca9f922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596695012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2596695012
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.3679277509
Short name T254
Test name
Test status
Simulation time 165730339 ps
CPU time 2.93 seconds
Started Jun 11 12:47:22 PM PDT 24
Finished Jun 11 12:47:28 PM PDT 24
Peak memory 233180 kb
Host smart-d6364bc2-215a-4926-b025-18471d367141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679277509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.3679277509
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.501905059
Short name T135
Test name
Test status
Simulation time 324674187 ps
CPU time 3.73 seconds
Started Jun 11 12:47:30 PM PDT 24
Finished Jun 11 12:47:40 PM PDT 24
Peak memory 220496 kb
Host smart-ada854c9-b8ef-44f4-ad37-67d11828a643
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=501905059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dire
ct.501905059
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.1939551435
Short name T48
Test name
Test status
Simulation time 583004425239 ps
CPU time 690.75 seconds
Started Jun 11 12:47:19 PM PDT 24
Finished Jun 11 12:58:53 PM PDT 24
Peak memory 265960 kb
Host smart-7cab4e93-9ece-4363-b0a7-3776200cf2ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939551435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.1939551435
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.3525188686
Short name T736
Test name
Test status
Simulation time 1439670107 ps
CPU time 4.34 seconds
Started Jun 11 12:47:22 PM PDT 24
Finished Jun 11 12:47:31 PM PDT 24
Peak memory 216552 kb
Host smart-d9997d82-bcc3-4a57-9d46-6e26ad63082f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525188686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3525188686
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2918044797
Short name T916
Test name
Test status
Simulation time 42873774 ps
CPU time 0.7 seconds
Started Jun 11 12:47:22 PM PDT 24
Finished Jun 11 12:47:27 PM PDT 24
Peak memory 205956 kb
Host smart-81883c51-6daf-42d0-bd0b-a1155ae082a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918044797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2918044797
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.251197933
Short name T830
Test name
Test status
Simulation time 12715002 ps
CPU time 0.78 seconds
Started Jun 11 12:47:13 PM PDT 24
Finished Jun 11 12:47:16 PM PDT 24
Peak memory 206792 kb
Host smart-20f3988e-fc46-4259-b281-45537f72f735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251197933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.251197933
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.2444914514
Short name T739
Test name
Test status
Simulation time 139576575 ps
CPU time 0.78 seconds
Started Jun 11 12:47:27 PM PDT 24
Finished Jun 11 12:47:32 PM PDT 24
Peak memory 206200 kb
Host smart-97a17bc6-6ce2-4fb9-ad54-3374d82f5735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444914514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2444914514
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.2798494909
Short name T758
Test name
Test status
Simulation time 125083087 ps
CPU time 2.56 seconds
Started Jun 11 12:47:21 PM PDT 24
Finished Jun 11 12:47:27 PM PDT 24
Peak memory 224584 kb
Host smart-1f40774e-c435-4d37-8157-9c6e8a95af97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798494909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2798494909
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.3890218746
Short name T554
Test name
Test status
Simulation time 93981762 ps
CPU time 0.75 seconds
Started Jun 11 12:47:28 PM PDT 24
Finished Jun 11 12:47:34 PM PDT 24
Peak memory 205056 kb
Host smart-b58b066f-0bac-4906-aa5f-18075aef7807
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890218746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
3890218746
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.1937368277
Short name T676
Test name
Test status
Simulation time 62175759 ps
CPU time 2.64 seconds
Started Jun 11 12:47:27 PM PDT 24
Finished Jun 11 12:47:34 PM PDT 24
Peak memory 232812 kb
Host smart-bf33c33f-e5b9-46d1-9994-07d7b040784d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937368277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.1937368277
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.191342298
Short name T667
Test name
Test status
Simulation time 35080028 ps
CPU time 0.76 seconds
Started Jun 11 12:47:11 PM PDT 24
Finished Jun 11 12:47:15 PM PDT 24
Peak memory 205880 kb
Host smart-f34a3db3-14a5-44bc-8e79-ad7bf76812f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191342298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.191342298
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.1831061617
Short name T572
Test name
Test status
Simulation time 1619823781 ps
CPU time 8.92 seconds
Started Jun 11 12:47:25 PM PDT 24
Finished Jun 11 12:47:37 PM PDT 24
Peak memory 241144 kb
Host smart-77219a8c-06d0-4497-aff0-ee01b4dce82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1831061617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.1831061617
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.1229393712
Short name T926
Test name
Test status
Simulation time 27687555184 ps
CPU time 235 seconds
Started Jun 11 12:47:24 PM PDT 24
Finished Jun 11 12:51:23 PM PDT 24
Peak memory 256964 kb
Host smart-c0243790-02fc-44f5-a761-e7e486f88e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229393712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.1229393712
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.2297940309
Short name T204
Test name
Test status
Simulation time 30261002650 ps
CPU time 117.95 seconds
Started Jun 11 12:47:24 PM PDT 24
Finished Jun 11 12:49:25 PM PDT 24
Peak memory 249540 kb
Host smart-ef3376ba-75da-4cc4-bd4c-4d220b71ee07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297940309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.2297940309
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.3867036690
Short name T300
Test name
Test status
Simulation time 197496364 ps
CPU time 8.2 seconds
Started Jun 11 12:47:25 PM PDT 24
Finished Jun 11 12:47:36 PM PDT 24
Peak memory 232948 kb
Host smart-1b9e77aa-6ce4-4bab-bbcf-30ce07a947d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867036690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.3867036690
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.1499074724
Short name T499
Test name
Test status
Simulation time 1844997145 ps
CPU time 15.76 seconds
Started Jun 11 12:47:28 PM PDT 24
Finished Jun 11 12:47:49 PM PDT 24
Peak memory 232932 kb
Host smart-de078247-be41-4e52-9c19-24bd08b254dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499074724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.1499074724
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.391274733
Short name T868
Test name
Test status
Simulation time 428314275 ps
CPU time 6.43 seconds
Started Jun 11 12:47:26 PM PDT 24
Finished Jun 11 12:47:36 PM PDT 24
Peak memory 228152 kb
Host smart-2b4078a9-998b-4683-bd4a-7ef52efc1850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391274733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.391274733
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.2729448340
Short name T10
Test name
Test status
Simulation time 3500035704 ps
CPU time 4.15 seconds
Started Jun 11 12:47:26 PM PDT 24
Finished Jun 11 12:47:35 PM PDT 24
Peak memory 224864 kb
Host smart-292e0753-f16b-4b75-871c-d45fe9d1b237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729448340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.2729448340
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.2587410257
Short name T786
Test name
Test status
Simulation time 2642004869 ps
CPU time 11.46 seconds
Started Jun 11 12:47:27 PM PDT 24
Finished Jun 11 12:47:42 PM PDT 24
Peak memory 241216 kb
Host smart-0835444b-0ed2-4e49-90e2-1ccbd88e0670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2587410257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.2587410257
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.2219591776
Short name T516
Test name
Test status
Simulation time 516861896 ps
CPU time 4.85 seconds
Started Jun 11 12:47:22 PM PDT 24
Finished Jun 11 12:47:31 PM PDT 24
Peak memory 220308 kb
Host smart-b9ce499a-5a38-4fcc-8248-8584a4267a92
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2219591776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.2219591776
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.1563541347
Short name T638
Test name
Test status
Simulation time 175559149 ps
CPU time 1.01 seconds
Started Jun 11 12:47:28 PM PDT 24
Finished Jun 11 12:47:34 PM PDT 24
Peak memory 207228 kb
Host smart-cda9e0ad-fd31-4ef2-86a2-47304c4bf710
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563541347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.1563541347
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.2480228512
Short name T601
Test name
Test status
Simulation time 816854009 ps
CPU time 4.4 seconds
Started Jun 11 12:47:29 PM PDT 24
Finished Jun 11 12:47:39 PM PDT 24
Peak memory 219216 kb
Host smart-a18aed36-aed3-48cf-843c-77bd86c40dc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2480228512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2480228512
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.1224070558
Short name T348
Test name
Test status
Simulation time 7262401216 ps
CPU time 8.33 seconds
Started Jun 11 12:47:24 PM PDT 24
Finished Jun 11 12:47:36 PM PDT 24
Peak memory 216648 kb
Host smart-c0f403db-5528-47d5-a2de-d34ace322ac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224070558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1224070558
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.2242222133
Short name T547
Test name
Test status
Simulation time 107633974 ps
CPU time 1.09 seconds
Started Jun 11 12:47:20 PM PDT 24
Finished Jun 11 12:47:25 PM PDT 24
Peak memory 215896 kb
Host smart-5bd5f424-29fe-4fec-b9f3-985e485d0a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242222133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.2242222133
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3857051754
Short name T455
Test name
Test status
Simulation time 125180154 ps
CPU time 0.79 seconds
Started Jun 11 12:47:41 PM PDT 24
Finished Jun 11 12:47:45 PM PDT 24
Peak memory 206096 kb
Host smart-e891120a-d8ad-46b3-915f-0e62e5bf9825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857051754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3857051754
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.362649948
Short name T23
Test name
Test status
Simulation time 569453696 ps
CPU time 2.22 seconds
Started Jun 11 12:47:22 PM PDT 24
Finished Jun 11 12:47:28 PM PDT 24
Peak memory 224296 kb
Host smart-923c5b51-9ee3-4e2c-bed2-15a62ec60b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362649948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.362649948
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.3336649067
Short name T693
Test name
Test status
Simulation time 15075236 ps
CPU time 0.73 seconds
Started Jun 11 12:45:47 PM PDT 24
Finished Jun 11 12:45:51 PM PDT 24
Peak memory 205336 kb
Host smart-9d675d65-f131-46f6-931d-030ec7d8002e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336649067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3
336649067
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.3633569369
Short name T350
Test name
Test status
Simulation time 122864291 ps
CPU time 3.08 seconds
Started Jun 11 12:45:41 PM PDT 24
Finished Jun 11 12:45:49 PM PDT 24
Peak memory 224688 kb
Host smart-f16c8370-22f8-4ce9-80f9-68104cf76641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633569369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.3633569369
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.3802874882
Short name T769
Test name
Test status
Simulation time 74467332 ps
CPU time 0.76 seconds
Started Jun 11 12:45:40 PM PDT 24
Finished Jun 11 12:45:45 PM PDT 24
Peak memory 205864 kb
Host smart-25fe951e-ffb5-45e5-b231-36db0d173b67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802874882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.3802874882
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.3321542938
Short name T488
Test name
Test status
Simulation time 71986210 ps
CPU time 0.77 seconds
Started Jun 11 12:45:42 PM PDT 24
Finished Jun 11 12:45:51 PM PDT 24
Peak memory 215896 kb
Host smart-687a9db1-c9d7-4366-8e94-9ea8440f30de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321542938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.3321542938
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.1602975654
Short name T52
Test name
Test status
Simulation time 68225194825 ps
CPU time 520.66 seconds
Started Jun 11 12:45:38 PM PDT 24
Finished Jun 11 12:54:23 PM PDT 24
Peak memory 266240 kb
Host smart-fab3710b-0d5b-477a-9869-8551920659ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602975654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.1602975654
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.2552594307
Short name T892
Test name
Test status
Simulation time 17350719421 ps
CPU time 150.57 seconds
Started Jun 11 12:45:36 PM PDT 24
Finished Jun 11 12:48:09 PM PDT 24
Peak memory 249580 kb
Host smart-86fd02f2-d776-4721-bf5d-81e1862dcb20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552594307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.2552594307
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.2633956430
Short name T351
Test name
Test status
Simulation time 1282841240 ps
CPU time 19.64 seconds
Started Jun 11 12:45:39 PM PDT 24
Finished Jun 11 12:46:03 PM PDT 24
Peak memory 232884 kb
Host smart-6dc3ce93-d9de-4d70-9856-fe71365a4535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633956430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2633956430
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.287951457
Short name T661
Test name
Test status
Simulation time 442337652 ps
CPU time 2.64 seconds
Started Jun 11 12:45:50 PM PDT 24
Finished Jun 11 12:45:55 PM PDT 24
Peak memory 224752 kb
Host smart-ba357cc6-d9d5-4fee-a7e0-8f175d4648d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287951457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.287951457
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.606568365
Short name T723
Test name
Test status
Simulation time 4011043329 ps
CPU time 28.61 seconds
Started Jun 11 12:45:42 PM PDT 24
Finished Jun 11 12:46:15 PM PDT 24
Peak memory 233124 kb
Host smart-039f03cd-7a81-4a3b-8e18-ce1e38671e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606568365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.606568365
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.4117068649
Short name T196
Test name
Test status
Simulation time 6370240244 ps
CPU time 19.66 seconds
Started Jun 11 12:45:41 PM PDT 24
Finished Jun 11 12:46:05 PM PDT 24
Peak memory 224928 kb
Host smart-a7e33827-70eb-4ba6-91da-8d054acab74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117068649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.4117068649
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.2147433336
Short name T614
Test name
Test status
Simulation time 1480616783 ps
CPU time 9.37 seconds
Started Jun 11 12:45:39 PM PDT 24
Finished Jun 11 12:45:54 PM PDT 24
Peak memory 224764 kb
Host smart-ab88e8d8-3556-4400-9f22-cd92ca5dd5f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147433336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.2147433336
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.1496796062
Short name T612
Test name
Test status
Simulation time 221032632 ps
CPU time 4.14 seconds
Started Jun 11 12:45:39 PM PDT 24
Finished Jun 11 12:45:48 PM PDT 24
Peak memory 223408 kb
Host smart-1b69156d-e83a-467c-8eeb-f6b5a93eb3bc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1496796062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.1496796062
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.153046038
Short name T451
Test name
Test status
Simulation time 34312435 ps
CPU time 0.98 seconds
Started Jun 11 12:45:34 PM PDT 24
Finished Jun 11 12:45:38 PM PDT 24
Peak memory 206012 kb
Host smart-9e65e2b3-74a2-4dca-8ab9-7df8c25f10af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153046038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress
_all.153046038
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2038658863
Short name T840
Test name
Test status
Simulation time 25599768 ps
CPU time 0.73 seconds
Started Jun 11 12:45:38 PM PDT 24
Finished Jun 11 12:45:43 PM PDT 24
Peak memory 205932 kb
Host smart-093321b1-d245-4078-a0ae-7774e23d8e73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038658863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2038658863
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.951841934
Short name T845
Test name
Test status
Simulation time 1992409994 ps
CPU time 5.33 seconds
Started Jun 11 12:45:35 PM PDT 24
Finished Jun 11 12:45:44 PM PDT 24
Peak memory 216520 kb
Host smart-c6642611-8d2a-40a3-8ed2-498bff33ccf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951841934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.951841934
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.2980632393
Short name T551
Test name
Test status
Simulation time 110719059 ps
CPU time 1.45 seconds
Started Jun 11 12:45:43 PM PDT 24
Finished Jun 11 12:45:49 PM PDT 24
Peak memory 216468 kb
Host smart-565339c9-ab13-453b-b7c8-aaf400fd4685
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980632393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2980632393
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.3999439683
Short name T460
Test name
Test status
Simulation time 29189059 ps
CPU time 0.83 seconds
Started Jun 11 12:45:43 PM PDT 24
Finished Jun 11 12:45:48 PM PDT 24
Peak memory 205924 kb
Host smart-54a0ea53-d5b5-4f97-9222-ee1fa44192e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999439683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3999439683
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.3096176540
Short name T255
Test name
Test status
Simulation time 1236516558 ps
CPU time 4.37 seconds
Started Jun 11 12:45:31 PM PDT 24
Finished Jun 11 12:45:38 PM PDT 24
Peak memory 224644 kb
Host smart-24eeee43-3bd7-4a86-9612-e065e4f50499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096176540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3096176540
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.3456573272
Short name T406
Test name
Test status
Simulation time 18787209 ps
CPU time 0.76 seconds
Started Jun 11 12:45:42 PM PDT 24
Finished Jun 11 12:45:47 PM PDT 24
Peak memory 205724 kb
Host smart-8d209bb8-3ed6-418d-95c4-4739b0a91ed9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456573272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.3
456573272
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3100874354
Short name T163
Test name
Test status
Simulation time 4440449480 ps
CPU time 4.99 seconds
Started Jun 11 12:45:41 PM PDT 24
Finished Jun 11 12:45:50 PM PDT 24
Peak memory 224892 kb
Host smart-3164a7b8-1d27-4617-9506-b32d65e472d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100874354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3100874354
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.1183247206
Short name T724
Test name
Test status
Simulation time 13770122 ps
CPU time 0.74 seconds
Started Jun 11 12:45:47 PM PDT 24
Finished Jun 11 12:45:52 PM PDT 24
Peak memory 206164 kb
Host smart-3e61db25-886f-483a-8f57-e2e4ff201f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183247206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1183247206
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1159203363
Short name T176
Test name
Test status
Simulation time 6680480375 ps
CPU time 38.17 seconds
Started Jun 11 12:45:45 PM PDT 24
Finished Jun 11 12:46:27 PM PDT 24
Peak memory 265892 kb
Host smart-34cd5cff-f9fc-4593-9e57-f16e5bd02fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159203363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1159203363
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.1417285312
Short name T234
Test name
Test status
Simulation time 30024663027 ps
CPU time 263.75 seconds
Started Jun 11 12:45:43 PM PDT 24
Finished Jun 11 12:50:11 PM PDT 24
Peak memory 254168 kb
Host smart-7d8bdf4b-cece-4a3b-9fa2-442128a8d33f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417285312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.1417285312
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.126885888
Short name T675
Test name
Test status
Simulation time 1147863862 ps
CPU time 21.37 seconds
Started Jun 11 12:45:37 PM PDT 24
Finished Jun 11 12:46:02 PM PDT 24
Peak memory 241212 kb
Host smart-9ce2fa7f-992c-46bb-a461-3a7ba64e124d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126885888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.
126885888
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.1014854010
Short name T584
Test name
Test status
Simulation time 1133958451 ps
CPU time 17.85 seconds
Started Jun 11 12:45:40 PM PDT 24
Finished Jun 11 12:46:02 PM PDT 24
Peak memory 224748 kb
Host smart-8f7cb401-76e0-4337-a2b4-0e14c6c008d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014854010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.1014854010
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2902477409
Short name T598
Test name
Test status
Simulation time 2634801001 ps
CPU time 23.56 seconds
Started Jun 11 12:45:40 PM PDT 24
Finished Jun 11 12:46:08 PM PDT 24
Peak memory 233084 kb
Host smart-d97de0b0-8f8a-4e8d-b0ab-24008a016245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902477409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2902477409
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.2321664383
Short name T336
Test name
Test status
Simulation time 31306892 ps
CPU time 2.73 seconds
Started Jun 11 12:45:39 PM PDT 24
Finished Jun 11 12:45:47 PM PDT 24
Peak memory 232804 kb
Host smart-da053e5e-77f1-4903-a22f-77a05cdd0f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321664383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.2321664383
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.739456410
Short name T194
Test name
Test status
Simulation time 690263699 ps
CPU time 5.58 seconds
Started Jun 11 12:45:35 PM PDT 24
Finished Jun 11 12:45:43 PM PDT 24
Peak memory 224792 kb
Host smart-637611aa-7147-4de4-a259-0701f3e78b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739456410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.
739456410
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.1360240602
Short name T806
Test name
Test status
Simulation time 24072494257 ps
CPU time 6.33 seconds
Started Jun 11 12:45:39 PM PDT 24
Finished Jun 11 12:45:49 PM PDT 24
Peak memory 224900 kb
Host smart-c855b0b9-a8b2-429f-b084-e149f6a1d512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360240602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1360240602
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.3255728225
Short name T380
Test name
Test status
Simulation time 662613300 ps
CPU time 3.82 seconds
Started Jun 11 12:45:39 PM PDT 24
Finished Jun 11 12:45:47 PM PDT 24
Peak memory 220948 kb
Host smart-36824f8c-b8fd-4b39-90e7-7c0d429be3e9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3255728225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.3255728225
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.3419819084
Short name T17
Test name
Test status
Simulation time 161602043021 ps
CPU time 383.36 seconds
Started Jun 11 12:45:28 PM PDT 24
Finished Jun 11 12:51:54 PM PDT 24
Peak memory 266472 kb
Host smart-192bbeaf-cead-4513-a7ac-b66a9ecb6c2b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419819084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.3419819084
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.1531360297
Short name T734
Test name
Test status
Simulation time 3875821963 ps
CPU time 20.12 seconds
Started Jun 11 12:45:58 PM PDT 24
Finished Jun 11 12:46:19 PM PDT 24
Peak memory 216648 kb
Host smart-847e7082-0e2e-4ae3-b9df-e29c501ff39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531360297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.1531360297
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.2642607963
Short name T565
Test name
Test status
Simulation time 2483322138 ps
CPU time 2.23 seconds
Started Jun 11 12:45:49 PM PDT 24
Finished Jun 11 12:45:54 PM PDT 24
Peak memory 207640 kb
Host smart-b49f4624-c8c7-4b6d-bae6-3b70467c997a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642607963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.2642607963
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.3640593615
Short name T755
Test name
Test status
Simulation time 31353113 ps
CPU time 0.88 seconds
Started Jun 11 12:45:46 PM PDT 24
Finished Jun 11 12:45:51 PM PDT 24
Peak memory 206724 kb
Host smart-1fe92122-24bb-4419-a4f2-c48662f309e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640593615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3640593615
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.736822699
Short name T623
Test name
Test status
Simulation time 302501928 ps
CPU time 0.92 seconds
Started Jun 11 12:45:33 PM PDT 24
Finished Jun 11 12:45:37 PM PDT 24
Peak memory 207152 kb
Host smart-f7919e4e-81a5-4306-a349-ca884c12a82d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736822699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.736822699
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.1860306240
Short name T826
Test name
Test status
Simulation time 117581468 ps
CPU time 2.23 seconds
Started Jun 11 12:45:32 PM PDT 24
Finished Jun 11 12:45:37 PM PDT 24
Peak memory 223412 kb
Host smart-2e5a5b8f-b88b-478b-9cd1-d2eaa546f4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860306240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1860306240
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.698628561
Short name T59
Test name
Test status
Simulation time 12303467 ps
CPU time 0.71 seconds
Started Jun 11 12:45:35 PM PDT 24
Finished Jun 11 12:45:39 PM PDT 24
Peak memory 206056 kb
Host smart-f856ea54-edff-4c2d-98b5-39cc47bc8642
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698628561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.698628561
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.3779518508
Short name T578
Test name
Test status
Simulation time 397221309 ps
CPU time 5.67 seconds
Started Jun 11 12:45:44 PM PDT 24
Finished Jun 11 12:45:54 PM PDT 24
Peak memory 232932 kb
Host smart-ebeceb7d-c4de-4bcb-86d7-6e95ca896c37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779518508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.3779518508
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.102198612
Short name T498
Test name
Test status
Simulation time 43628317 ps
CPU time 0.77 seconds
Started Jun 11 12:45:31 PM PDT 24
Finished Jun 11 12:45:34 PM PDT 24
Peak memory 207188 kb
Host smart-e2b8808d-ceae-4141-9214-79f8b849d27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=102198612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.102198612
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.1132620262
Short name T471
Test name
Test status
Simulation time 4120300207 ps
CPU time 35.45 seconds
Started Jun 11 12:45:55 PM PDT 24
Finished Jun 11 12:46:32 PM PDT 24
Peak memory 241280 kb
Host smart-c272cbc6-8222-459b-9aff-75dbb4649699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132620262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.1132620262
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.1754870088
Short name T851
Test name
Test status
Simulation time 13393649265 ps
CPU time 27.92 seconds
Started Jun 11 12:45:36 PM PDT 24
Finished Jun 11 12:46:07 PM PDT 24
Peak memory 241296 kb
Host smart-75c8710b-5dee-46d1-b8e2-6d27748d374f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754870088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.1754870088
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.52350771
Short name T867
Test name
Test status
Simulation time 579339953 ps
CPU time 3.19 seconds
Started Jun 11 12:45:32 PM PDT 24
Finished Jun 11 12:45:38 PM PDT 24
Peak memory 232988 kb
Host smart-028d9322-0707-4e86-82bf-28ee8d27ea51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52350771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.52350771
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.676840101
Short name T424
Test name
Test status
Simulation time 185902083 ps
CPU time 3.7 seconds
Started Jun 11 12:45:41 PM PDT 24
Finished Jun 11 12:45:49 PM PDT 24
Peak memory 232980 kb
Host smart-43eb7970-778f-4f52-9f65-1dbca183b968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676840101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.676840101
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.111509337
Short name T171
Test name
Test status
Simulation time 41313897397 ps
CPU time 79.58 seconds
Started Jun 11 12:45:42 PM PDT 24
Finished Jun 11 12:47:06 PM PDT 24
Peak memory 240540 kb
Host smart-1a084e16-b22b-435d-9843-833ce7a36b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111509337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.111509337
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.4033948907
Short name T536
Test name
Test status
Simulation time 1402625125 ps
CPU time 7.98 seconds
Started Jun 11 12:45:55 PM PDT 24
Finished Jun 11 12:46:04 PM PDT 24
Peak memory 232984 kb
Host smart-919bf6af-e0d4-4999-af0e-e0d06095fdbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033948907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.4033948907
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.1960861546
Short name T754
Test name
Test status
Simulation time 4751084253 ps
CPU time 7.33 seconds
Started Jun 11 12:45:38 PM PDT 24
Finished Jun 11 12:45:50 PM PDT 24
Peak memory 224852 kb
Host smart-07e89375-5227-4540-85b8-76840c2f4d57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960861546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.1960861546
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.1850840471
Short name T30
Test name
Test status
Simulation time 95351853 ps
CPU time 3.92 seconds
Started Jun 11 12:45:40 PM PDT 24
Finished Jun 11 12:45:48 PM PDT 24
Peak memory 220888 kb
Host smart-0c961cc8-5164-4dbc-8270-fe2a89f40501
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1850840471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.1850840471
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.3842720917
Short name T821
Test name
Test status
Simulation time 7862971465 ps
CPU time 44.17 seconds
Started Jun 11 12:45:36 PM PDT 24
Finished Jun 11 12:46:24 PM PDT 24
Peak memory 224924 kb
Host smart-28f0fe1d-b6e6-4bfd-9f82-90679d3f7a75
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842720917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.3842720917
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.1414511368
Short name T783
Test name
Test status
Simulation time 636133460 ps
CPU time 7.21 seconds
Started Jun 11 12:45:38 PM PDT 24
Finished Jun 11 12:45:49 PM PDT 24
Peak memory 216672 kb
Host smart-25d4600e-7a1a-414e-8556-3493aa0022ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414511368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.1414511368
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3482349770
Short name T427
Test name
Test status
Simulation time 318185680 ps
CPU time 2.49 seconds
Started Jun 11 12:45:30 PM PDT 24
Finished Jun 11 12:45:34 PM PDT 24
Peak memory 216596 kb
Host smart-9d1828e2-3343-4eb6-8b00-3b098a3aa505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482349770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3482349770
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.1515226804
Short name T710
Test name
Test status
Simulation time 281035622 ps
CPU time 13.5 seconds
Started Jun 11 12:45:42 PM PDT 24
Finished Jun 11 12:46:00 PM PDT 24
Peak memory 216096 kb
Host smart-627ebd33-6032-4dea-8652-20a107b304d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515226804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1515226804
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.280676471
Short name T398
Test name
Test status
Simulation time 63557041 ps
CPU time 0.89 seconds
Started Jun 11 12:45:56 PM PDT 24
Finished Jun 11 12:45:58 PM PDT 24
Peak memory 206428 kb
Host smart-68826143-605f-42ad-844d-da33697501e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280676471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.280676471
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.2373742386
Short name T259
Test name
Test status
Simulation time 5430179883 ps
CPU time 7.85 seconds
Started Jun 11 12:45:37 PM PDT 24
Finished Jun 11 12:45:49 PM PDT 24
Peak memory 233108 kb
Host smart-bd41fa68-2c31-465c-bd2a-088866235282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373742386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2373742386
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.908880394
Short name T649
Test name
Test status
Simulation time 43443637 ps
CPU time 0.77 seconds
Started Jun 11 12:45:45 PM PDT 24
Finished Jun 11 12:45:49 PM PDT 24
Peak memory 205136 kb
Host smart-fec34fdc-2bf2-4ca7-ad23-cbf8ba76cd7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908880394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.908880394
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.1826178481
Short name T85
Test name
Test status
Simulation time 654461877 ps
CPU time 4.39 seconds
Started Jun 11 12:45:38 PM PDT 24
Finished Jun 11 12:45:47 PM PDT 24
Peak memory 224780 kb
Host smart-6fb42f52-a14d-4567-ae1a-abdc6cb946ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826178481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.1826178481
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.3138935248
Short name T423
Test name
Test status
Simulation time 22437181 ps
CPU time 0.79 seconds
Started Jun 11 12:45:40 PM PDT 24
Finished Jun 11 12:45:46 PM PDT 24
Peak memory 207204 kb
Host smart-c4bf736b-996a-4c5d-82bb-e4c0e0da7b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138935248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.3138935248
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1876152284
Short name T720
Test name
Test status
Simulation time 142488147202 ps
CPU time 228.37 seconds
Started Jun 11 12:45:39 PM PDT 24
Finished Jun 11 12:49:32 PM PDT 24
Peak memory 240412 kb
Host smart-a10cd4db-988d-4fca-be86-9546c9f3efbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876152284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1876152284
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.544924438
Short name T571
Test name
Test status
Simulation time 31181712313 ps
CPU time 154.13 seconds
Started Jun 11 12:45:57 PM PDT 24
Finished Jun 11 12:48:33 PM PDT 24
Peak memory 257724 kb
Host smart-e976c9b4-b66c-4634-8223-f4446c23bf12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544924438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.544924438
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2966952869
Short name T192
Test name
Test status
Simulation time 51402644480 ps
CPU time 68.82 seconds
Started Jun 11 12:45:42 PM PDT 24
Finished Jun 11 12:46:55 PM PDT 24
Peak memory 251948 kb
Host smart-3ba6a4fc-d2b1-4e04-b30b-3f615131a6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2966952869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.2966952869
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.449422124
Short name T597
Test name
Test status
Simulation time 405735675 ps
CPU time 4.1 seconds
Started Jun 11 12:45:47 PM PDT 24
Finished Jun 11 12:45:54 PM PDT 24
Peak memory 224800 kb
Host smart-ba407f2c-3e52-410d-a0b8-8ca9531efc6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449422124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.449422124
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.3517789483
Short name T444
Test name
Test status
Simulation time 477856645 ps
CPU time 2.71 seconds
Started Jun 11 12:45:46 PM PDT 24
Finished Jun 11 12:45:52 PM PDT 24
Peak memory 224712 kb
Host smart-00f81cc0-73ee-4385-aa02-2c70c44343c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517789483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.3517789483
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.916351629
Short name T779
Test name
Test status
Simulation time 635728703 ps
CPU time 4.31 seconds
Started Jun 11 12:45:40 PM PDT 24
Finished Jun 11 12:45:49 PM PDT 24
Peak memory 232960 kb
Host smart-7b2ffb35-672d-4f73-9c41-6a7e077bc27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916351629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.916351629
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.623384747
Short name T446
Test name
Test status
Simulation time 821367695 ps
CPU time 6.92 seconds
Started Jun 11 12:45:37 PM PDT 24
Finished Jun 11 12:45:48 PM PDT 24
Peak memory 218836 kb
Host smart-1cf279a0-2cb2-405a-aa0c-1a1264803712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623384747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.
623384747
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.1562586849
Short name T729
Test name
Test status
Simulation time 3434206120 ps
CPU time 5.73 seconds
Started Jun 11 12:45:59 PM PDT 24
Finished Jun 11 12:46:06 PM PDT 24
Peak memory 232948 kb
Host smart-25725609-c03a-45bc-96c6-a41676c83d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562586849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.1562586849
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1368321909
Short name T586
Test name
Test status
Simulation time 5520226544 ps
CPU time 7.43 seconds
Started Jun 11 12:45:38 PM PDT 24
Finished Jun 11 12:45:49 PM PDT 24
Peak memory 223400 kb
Host smart-d67d26cc-514e-424f-bc2d-3746a09eadac
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1368321909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1368321909
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.2890286035
Short name T207
Test name
Test status
Simulation time 15035937980 ps
CPU time 81.25 seconds
Started Jun 11 12:45:50 PM PDT 24
Finished Jun 11 12:47:14 PM PDT 24
Peak memory 253364 kb
Host smart-e40d89df-b51e-492c-8186-835e542957b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890286035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.2890286035
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.1138664086
Short name T604
Test name
Test status
Simulation time 3429895842 ps
CPU time 17.04 seconds
Started Jun 11 12:45:36 PM PDT 24
Finished Jun 11 12:45:56 PM PDT 24
Peak memory 216604 kb
Host smart-cd51d7bd-4b27-4674-963c-2cea55a3fcc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138664086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.1138664086
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.4183994700
Short name T846
Test name
Test status
Simulation time 14385121 ps
CPU time 0.71 seconds
Started Jun 11 12:45:32 PM PDT 24
Finished Jun 11 12:45:35 PM PDT 24
Peak memory 205928 kb
Host smart-7a9d07a3-b7a2-473e-8543-a3f2e9f63a14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183994700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.4183994700
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.496629400
Short name T540
Test name
Test status
Simulation time 107984149 ps
CPU time 0.92 seconds
Started Jun 11 12:45:38 PM PDT 24
Finished Jun 11 12:45:43 PM PDT 24
Peak memory 206848 kb
Host smart-61104f19-53b9-4241-8c15-b0d18b9304df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496629400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.496629400
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.963961888
Short name T633
Test name
Test status
Simulation time 147764568 ps
CPU time 1.06 seconds
Started Jun 11 12:45:37 PM PDT 24
Finished Jun 11 12:45:42 PM PDT 24
Peak memory 206104 kb
Host smart-ec228c09-1e31-40f8-b1bd-12ca10ab413a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963961888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.963961888
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.1923181287
Short name T476
Test name
Test status
Simulation time 41289669 ps
CPU time 2.59 seconds
Started Jun 11 12:45:39 PM PDT 24
Finished Jun 11 12:45:46 PM PDT 24
Peak memory 224556 kb
Host smart-c4467b9f-3344-41f8-b2de-ce06ec6c9087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923181287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1923181287
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.2015852839
Short name T848
Test name
Test status
Simulation time 38010014 ps
CPU time 0.72 seconds
Started Jun 11 12:45:53 PM PDT 24
Finished Jun 11 12:45:55 PM PDT 24
Peak memory 205772 kb
Host smart-9d0e4778-90ef-4cb5-a57c-6459358a6976
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015852839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.2
015852839
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.2560279108
Short name T827
Test name
Test status
Simulation time 6116561498 ps
CPU time 6.21 seconds
Started Jun 11 12:45:45 PM PDT 24
Finished Jun 11 12:45:55 PM PDT 24
Peak memory 224784 kb
Host smart-d9ffd741-ae79-4118-b03d-b2e57088e3b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560279108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2560279108
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.734656972
Short name T587
Test name
Test status
Simulation time 14097182 ps
CPU time 0.77 seconds
Started Jun 11 12:45:51 PM PDT 24
Finished Jun 11 12:45:54 PM PDT 24
Peak memory 207196 kb
Host smart-22826453-f576-4ca0-b42b-f6a55ca79265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734656972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.734656972
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.707943500
Short name T78
Test name
Test status
Simulation time 12529125720 ps
CPU time 57.47 seconds
Started Jun 11 12:46:11 PM PDT 24
Finished Jun 11 12:47:11 PM PDT 24
Peak memory 249508 kb
Host smart-c86d25e4-8f14-4fb4-b267-7833eae8e3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707943500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.707943500
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.2267005260
Short name T566
Test name
Test status
Simulation time 23058129015 ps
CPU time 91.39 seconds
Started Jun 11 12:45:46 PM PDT 24
Finished Jun 11 12:47:21 PM PDT 24
Peak memory 249816 kb
Host smart-72fdae0e-c68f-41ca-a783-57fe09e295ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267005260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.2267005260
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.656495352
Short name T268
Test name
Test status
Simulation time 1307452062 ps
CPU time 15.5 seconds
Started Jun 11 12:45:43 PM PDT 24
Finished Jun 11 12:46:02 PM PDT 24
Peak memory 240952 kb
Host smart-dd84ee86-b19a-46ad-baf6-ce87e6d6230f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=656495352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.
656495352
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.3746168143
Short name T305
Test name
Test status
Simulation time 3398113915 ps
CPU time 16.92 seconds
Started Jun 11 12:45:40 PM PDT 24
Finished Jun 11 12:46:02 PM PDT 24
Peak memory 224880 kb
Host smart-3beb7842-9fdc-4ad0-a001-af7d591870d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746168143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.3746168143
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.2648951692
Short name T681
Test name
Test status
Simulation time 2350198197 ps
CPU time 18.71 seconds
Started Jun 11 12:45:50 PM PDT 24
Finished Jun 11 12:46:11 PM PDT 24
Peak memory 224828 kb
Host smart-f1bc4c62-68f9-4c12-947a-b8e0f51f1209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648951692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2648951692
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.985797647
Short name T666
Test name
Test status
Simulation time 23534277828 ps
CPU time 51.24 seconds
Started Jun 11 12:45:47 PM PDT 24
Finished Jun 11 12:46:42 PM PDT 24
Peak memory 240320 kb
Host smart-a210d400-d8b8-4bc7-b0af-d86f713bb185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985797647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.985797647
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.3391616567
Short name T151
Test name
Test status
Simulation time 526034269 ps
CPU time 2.41 seconds
Started Jun 11 12:45:43 PM PDT 24
Finished Jun 11 12:45:50 PM PDT 24
Peak memory 224712 kb
Host smart-a5f184e8-099d-4991-a900-af2806b4aae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391616567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.3391616567
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.1356451314
Short name T509
Test name
Test status
Simulation time 4954647212 ps
CPU time 9.63 seconds
Started Jun 11 12:45:46 PM PDT 24
Finished Jun 11 12:45:59 PM PDT 24
Peak memory 241148 kb
Host smart-71fdb9d2-b1b1-491e-8bb7-65e361620381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356451314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1356451314
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.1656817386
Short name T735
Test name
Test status
Simulation time 262695135 ps
CPU time 4.65 seconds
Started Jun 11 12:45:56 PM PDT 24
Finished Jun 11 12:46:02 PM PDT 24
Peak memory 223052 kb
Host smart-df6867f8-c733-417a-ac79-4654e7af4d4f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1656817386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.1656817386
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.1615216492
Short name T57
Test name
Test status
Simulation time 13541980180 ps
CPU time 142.72 seconds
Started Jun 11 12:46:00 PM PDT 24
Finished Jun 11 12:48:25 PM PDT 24
Peak memory 255560 kb
Host smart-546120a8-e703-4922-9101-a74cfa3b80dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615216492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.1615216492
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.924882119
Short name T583
Test name
Test status
Simulation time 2648566546 ps
CPU time 22.31 seconds
Started Jun 11 12:46:06 PM PDT 24
Finished Jun 11 12:46:30 PM PDT 24
Peak memory 220020 kb
Host smart-196b4221-b6fd-4869-b58c-1599782d9487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924882119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.924882119
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.2426125592
Short name T627
Test name
Test status
Simulation time 4631837399 ps
CPU time 3.07 seconds
Started Jun 11 12:45:41 PM PDT 24
Finished Jun 11 12:45:49 PM PDT 24
Peak memory 208472 kb
Host smart-28e51d3d-09a8-40b9-8980-fd0c07f3b4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426125592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.2426125592
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.3066771708
Short name T718
Test name
Test status
Simulation time 74228309 ps
CPU time 0.89 seconds
Started Jun 11 12:45:45 PM PDT 24
Finished Jun 11 12:45:49 PM PDT 24
Peak memory 207492 kb
Host smart-8d6ccff9-abbd-44d9-9289-1a5473454058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066771708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3066771708
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.3914319193
Short name T526
Test name
Test status
Simulation time 45435933 ps
CPU time 0.84 seconds
Started Jun 11 12:45:40 PM PDT 24
Finished Jun 11 12:45:46 PM PDT 24
Peak memory 206140 kb
Host smart-d79e39e3-4130-4054-8be6-72dab711a11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3914319193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.3914319193
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.3567725896
Short name T811
Test name
Test status
Simulation time 9534579469 ps
CPU time 16.83 seconds
Started Jun 11 12:46:01 PM PDT 24
Finished Jun 11 12:46:20 PM PDT 24
Peak memory 250408 kb
Host smart-3c4e0322-667f-4fc7-9726-b57caabd3cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567725896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3567725896
Directory /workspace/9.spi_device_upload/latest
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