Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2267581	1			T1	1		T3	81356		T4	1
all_values[1]	2267581	1			T1	1		T3	81356		T4	1
all_values[2]	2267581	1			T1	1		T3	81356		T4	1
all_values[3]	2267581	1			T1	1		T3	81356		T4	1
all_values[4]	2267581	1			T1	1		T3	81356		T4	1
all_values[5]	2267581	1			T1	1		T3	81356		T4	1
all_values[6]	2267581	1			T1	1		T3	81356		T4	1
all_values[7]	2267581	1			T1	1		T3	81356		T4	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17844726

1

T1

8

T3

650848

T4

8

auto[1]

295922

1

T17

44

T18

31

T19

25

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18120808

1

T1

8

T3

650546

T4

8

auto[1]

19840

1

T3

302

T9

97

T45

214

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2243463	1			T1	1		T3	81158		T4	1
all_values[0]	auto[0]	auto[1]	9911	1			T3	198		T9	61		T45	113
all_values[0]	auto[1]	auto[0]	13982	1			T17	4		T18	2		T19	4
all_values[0]	auto[1]	auto[1]	225	1			T17	2		T18	1		T20	7
all_values[1]	auto[0]	auto[0]	2249522	1			T1	1		T3	81268		T4	1
all_values[1]	auto[0]	auto[1]	4981	1			T3	88		T9	18		T45	76
all_values[1]	auto[1]	auto[0]	12747	1			T18	1		T19	1		T20	3
all_values[1]	auto[1]	auto[1]	331	1			T17	1		T18	1		T19	2
all_values[2]	auto[0]	auto[0]	2194923	1			T1	1		T3	81340		T4	1
all_values[2]	auto[0]	auto[1]	1971	1			T3	16		T9	18		T45	25
all_values[2]	auto[1]	auto[0]	70371	1			T17	5		T18	1		T19	3
all_values[2]	auto[1]	auto[1]	316	1			T17	2		T18	3		T20	6
all_values[3]	auto[0]	auto[0]	2190150	1			T1	1		T3	81356		T4	1
all_values[3]	auto[0]	auto[1]	200	1			T17	1		T20	6		T21	3
all_values[3]	auto[1]	auto[0]	77018	1			T17	4		T18	4		T19	1
all_values[3]	auto[1]	auto[1]	213	1			T18	3		T19	4		T20	4
all_values[4]	auto[0]	auto[0]	2220880	1			T1	1		T3	81356		T4	1
all_values[4]	auto[0]	auto[1]	200	1			T140	3		T19	1		T20	4
all_values[4]	auto[1]	auto[0]	46276	1			T17	6		T18	3		T19	1
all_values[4]	auto[1]	auto[1]	225	1			T17	2		T18	2		T20	2
all_values[5]	auto[0]	auto[0]	2232385	1			T1	1		T3	81356		T4	1
all_values[5]	auto[0]	auto[1]	294	1			T46	6		T47	8		T240	5
all_values[5]	auto[1]	auto[0]	34720	1			T17	2		T18	2		T19	3
all_values[5]	auto[1]	auto[1]	182	1			T17	2		T18	4		T19	2
all_values[6]	auto[0]	auto[0]	2240884	1			T1	1		T3	81356		T4	1
all_values[6]	auto[0]	auto[1]	175	1			T18	1		T19	1		T20	3
all_values[6]	auto[1]	auto[0]	26328	1			T17	7		T18	2		T19	2
all_values[6]	auto[1]	auto[1]	194	1			T17	1		T19	2		T20	5
all_values[7]	auto[0]	auto[0]	2254567	1			T1	1		T3	81356		T4	1
all_values[7]	auto[0]	auto[1]	220	1			T17	2		T18	5		T19	4
all_values[7]	auto[1]	auto[0]	12592	1			T17	5		T18	2		T20	5
all_values[7]	auto[1]	auto[1]	202	1			T17	1		T20	4		T21	4