Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	28354	1			T3	114		T5	287		T9	119
auto[SpiFlashAddrCfg]	5810	1			T3	42		T5	31		T8	6
auto[SpiFlashAddr3b]	7358	1			T3	68		T5	39		T8	8
auto[SpiFlashAddr4b]	5809	1			T3	57		T5	28		T8	2

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26891

1

T3

143

T5

211

T9

155

auto[1]

20440

1

T3

138

T5

174

T8

16

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

25734

1

T3

161

T5

160

T8

10

auto[1]

21597

1

T3

120

T5

225

T8

6

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	31990	1			T3	151		T5	310		T8	2
values[1]	836	1			T3	8		T5	5		T9	2
values[2]	1145	1			T3	12		T5	3		T9	4
values[3]	1216	1			T3	14		T5	5		T9	10
values[4]	1077	1			T3	12		T8	2		T9	5
values[5]	1055	1			T3	4		T5	3		T9	8
values[6]	1234	1			T3	18		T5	18		T9	5
values[7]	1154	1			T3	8		T5	4		T9	5
values[8]	7624	1			T3	54		T5	37		T8	12

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23963

1

T3

281

T5

385

T8

16

auto[1]

23368

1

T14

2

T140

2

T39

20

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

45684

1

T3

268

T5

379

T8

14

write

1647

1

T3

13

T5

6

T8

2

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

15344

1

T3

116

T5

64

T8

8

valids[0x1]

31987

1

T3

165

T5

321

T8

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1279	1			T3	3		T5	3		T9	6
internal_process_ops[0x5a]	1212	1			T3	10		T5	5		T8	2
internal_process_ops[0x05]	17572	1			T3	33		T5	248		T9	35
internal_process_ops[0x35]	1291	1			T3	7		T5	7		T9	9
internal_process_ops[0x15]	1159	1			T3	10		T5	11		T9	9
internal_process_ops[0x03]	870	1			T3	9		T5	5		T9	7
internal_process_ops[0x0b]	882	1			T3	12		T5	4		T9	6
internal_process_ops[0x3b]	832	1			T3	11		T5	2		T9	6
internal_process_ops[0x6b]	844	1			T3	8		T5	9		T9	9
internal_process_ops[0xbb]	777	1			T3	8		T5	9		T8	2
internal_process_ops[0xeb]	791	1			T3	10		T5	4		T8	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46518

1

T3

273

T5

382

T8

14

auto[1]

813

1

T3

8

T5

3

T8

2

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45754

1

T3

268

T5

375

T8

16

auto[1]

1577

1

T3

13

T5

10

T9

11

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

7896

1

T3

67

T5

162

T9

88

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5086

1

T3

42

T5

125

T9

30

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1615

1

T3

21

T5

11

T9

21

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1468

1

T3

18

T5

17

T8

4

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2158

1

T3

31

T5

21

T9

25

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1820

1

T3

34

T5

16

T8

8

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1603

1

T3

20

T5

11

T9

18

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1459

1

T3

35

T5

16

T8

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

66

1

T3

1

T45

1

T18

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

55

1

T3

2

T9

1

T16

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

43

1

T49

1

T156

1

T21

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

33

1

T3

2

T18

1

T162

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

70

1

T15

2

T16

1

T18

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

49

1

T5

3

T15

1

T45

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

51

1

T3

3

T15

1

T18

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

49

1

T8

2

T9

1

T16

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

72

1

T5

2

T9

2

T15

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

45

1

T45

3

T49

1

T19

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

62

1

T15

2

T16

1

T18

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

61

1

T3

3

T16

2

T48

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

56

1

T3

1

T5

1

T15

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

43

1

T45

1

T163

2

T22

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

43

1

T15

2

T19

1

T162

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

60

1

T3

1

T9

2

T15

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8859

1

T39

5

T44

79

T50

52

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6125

1

T39

2

T44

183

T50

26

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1181

1

T140

2

T39

1

T44

6

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1126

1

T39

3

T44

10

T50

7

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1513

1

T14

1

T39

4

T44

17

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1414

1

T39

2

T44

14

T50

13

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1198

1

T14

1

T39

2

T44

17

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1163

1

T44

12

T50

12

T23

6

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

47

1

T44

3

T40

1

T56

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

60

1

T164

2

T84

6

T40

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

52

1

T165

1

T84

1

T166

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

32

1

T165

3

T84

3

T41

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

49

1

T44

1

T50

1

T84

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

50

1

T23

3

T165

1

T84

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

40

1

T50

1

T19

2

T165

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

62

1

T39

1

T50

1

T23

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

42

1

T41

2

T167

1

T168

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

79

1

T41

2

T167

2

T169

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

49

1

T50

4

T84

2

T40

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

43

1

T20

1

T164

1

T170

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

36

1

T19

2

T40

1

T56

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

49

1

T44

2

T19

3

T40

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

56

1

T44

1

T50

1

T20

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

43

1

T165

2

T84

1

T41

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3375	1			T3	47		T5	20		T9	60
auto[0]	values[0]	valids[0x1]	11844	1			T3	104		T5	290		T8	2
auto[0]	values[1]	valids[0x1]	437	1			T3	8		T5	5		T9	2
auto[0]	values[2]	valids[0x0]	432	1			T3	5		T5	2		T9	4
auto[0]	values[2]	valids[0x1]	238	1			T3	7		T5	1		T15	4
auto[0]	values[3]	valids[0x0]	469	1			T3	8		T5	4		T9	7
auto[0]	values[3]	valids[0x1]	265	1			T3	6		T5	1		T9	3
auto[0]	values[4]	valids[0x0]	389	1			T3	4		T9	5		T16	7
auto[0]	values[4]	valids[0x1]	234	1			T3	8		T8	2		T15	2
auto[0]	values[5]	valids[0x0]	367	1			T3	1		T5	1		T9	4
auto[0]	values[5]	valids[0x1]	226	1			T3	3		T5	2		T9	4
auto[0]	values[6]	valids[0x0]	458	1			T3	9		T5	11		T9	5
auto[0]	values[6]	valids[0x1]	242	1			T3	9		T5	7		T15	2
auto[0]	values[7]	valids[0x0]	435	1			T3	8		T5	1		T9	5
auto[0]	values[7]	valids[0x1]	235	1			T5	3		T15	2		T16	4
auto[0]	values[8]	valids[0x0]	2672	1			T3	34		T5	25		T8	8
auto[0]	values[8]	valids[0x1]	1645	1			T3	20		T5	12		T8	4
auto[1]	values[0]	valids[0x0]	3103	1			T39	6		T44	22		T50	37
auto[1]	values[0]	valids[0x1]	13668	1			T39	5		T44	264		T50	61
auto[1]	values[1]	valids[0x1]	399	1			T44	8		T50	3		T23	1
auto[1]	values[2]	valids[0x0]	297	1			T44	6		T23	1		T19	4
auto[1]	values[2]	valids[0x1]	178	1			T23	3		T19	1		T171	3
auto[1]	values[3]	valids[0x0]	275	1			T44	2		T50	1		T23	1
auto[1]	values[3]	valids[0x1]	207	1			T14	1		T44	5		T50	2
auto[1]	values[4]	valids[0x0]	257	1			T50	2		T18	4		T20	1
auto[1]	values[4]	valids[0x1]	197	1			T39	2		T23	1		T18	1
auto[1]	values[5]	valids[0x0]	266	1			T44	3		T50	1		T19	2
auto[1]	values[5]	valids[0x1]	196	1			T44	6		T50	1		T23	1
auto[1]	values[6]	valids[0x0]	326	1			T44	1		T23	2		T18	2
auto[1]	values[6]	valids[0x1]	208	1			T39	2		T44	1		T50	4
auto[1]	values[7]	valids[0x0]	283	1			T44	2		T50	5		T23	1
auto[1]	values[7]	valids[0x1]	201	1			T50	4		T18	3		T19	2
auto[1]	values[8]	valids[0x0]	1940	1			T14	1		T140	1		T44	17
auto[1]	values[8]	valids[0x1]	1367	1			T140	1		T39	5		T44	8