Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2752095

1

T3

26283

T5

19938

T8

1

auto[1]

16359

1

T3

21

T5

245

T9

27

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

914049

1

T3

82

T5

47

T8

1

auto[1]

1854405

1

T3

26222

T5

20136

T9

25188

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	548957	1			T3	6462		T5	6995		T8	1
auto[524288:1048575]	299348	1			T3	7294		T5	6401		T9	10729
auto[1048576:1572863]	336400	1			T3	10		T5	2037		T12	5
auto[1572864:2097151]	345573	1			T3	3541		T9	3040		T14	5855
auto[2097152:2621439]	286089	1			T3	754		T5	1		T9	2756
auto[2621440:3145727]	270817	1			T3	2976		T5	1606		T9	1556
auto[3145728:3670015]	373441	1			T3	3251		T5	6		T9	193
auto[3670016:4194303]	307829	1			T3	2016		T5	3137		T9	2445

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1872577

1

T3

26304

T5

20177

T8

1

auto[1]

895877

1

T5

6

T9

2

T12

78

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2421081

1

T3

23149

T5

17199

T8

1

auto[1]

347373

1

T3

3155

T5

2984

T9

268

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	203590	1			T3	7		T5	4		T8	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	296503	1			T3	3433		T5	6990		T9	4530
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	92153	1			T3	6		T5	4		T9	15
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	165144	1			T3	7286		T5	3353		T9	10701
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	126867	1			T3	6		T5	4		T12	5
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	178840	1			T3	2		T5	1980		T15	257
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	120102	1			T3	5		T9	9		T14	5855
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	186056	1			T3	3404		T9	2774		T15	59
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	61458	1			T3	2		T5	1		T9	4
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	177315	1			T3	750		T9	2748		T15	8041
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	58931	1			T3	8		T5	5		T9	7
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	159803	1			T3	2963		T5	1600		T9	1538
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	124274	1			T3	2		T5	1		T9	3
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	194227	1			T3	3249		T5	5		T9	184
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	113892	1			T3	20		T5	12		T9	4
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	149088	1			T3	1987		T5	3002		T9	2440
auto[0]	auto[1]	auto[0:524287]	auto[0]	321	1			T3	10		T9	2		T23	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	45606	1			T3	3011		T23	128		T84	1
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	1471	1			T5	6		T9	4		T15	4
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	38799	1			T5	2971		T9	1		T15	2
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	209	1			T49	2		T50	6		T162	2
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	28087	1			T16	256		T49	640		T50	430
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	485	1			T3	2		T9	1		T15	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	37136	1			T3	129		T9	256		T45	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	3367	1			T16	4		T45	1		T39	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	42318	1			T45	1		T39	512		T49	3988
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	4707	1			T15	1		T16	3		T45	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	45143	1			T15	1		T16	261		T45	1742
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	338	1			T9	3		T16	2		T45	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	53089	1			T16	256		T164	4		T165	87
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	304	1			T3	1		T18	4		T19	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	42472	1			T16	17		T163	1878		T84	1807
auto[1]	auto[0]	auto[0:524287]	auto[0]	214	1			T5	1		T15	1		T16	3
auto[1]	auto[0]	auto[0:524287]	auto[1]	1937	1			T15	4		T16	42		T44	61
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	155	1			T3	1		T5	2		T9	4
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1262	1			T3	1		T5	58		T9	3
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	174	1			T3	2		T5	1		T15	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1673	1			T5	52		T15	1		T16	23
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	142	1			T15	5		T44	3		T49	4
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1331	1			T15	58		T44	46		T49	17
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	140	1			T3	1		T9	1		T15	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1226	1			T3	1		T9	3		T15	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	153	1			T3	4		T5	1		T9	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1726	1			T3	1		T9	9		T15	20
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	134	1			T9	2		T15	1		T18	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	997	1			T9	1		T15	15		T18	13
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	168	1			T3	3		T5	4		T9	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1406	1			T3	5		T5	119		T16	66
auto[1]	auto[1]	auto[0:524287]	auto[0]	51	1			T3	1		T84	1		T59	2
auto[1]	auto[1]	auto[0:524287]	auto[1]	735	1			T84	50		T59	5		T78	14
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	32	1			T5	1		T9	1		T15	2
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	332	1			T5	6		T15	14		T50	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	39	1			T162	1		T84	2		T166	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	511	1			T162	5		T84	14		T166	4
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	29	1			T3	1		T45	1		T49	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	292	1			T45	1		T49	2		T18	8
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	30	1			T45	1		T156	1		T165	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	235	1			T165	33		T163	7		T84	90
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	35	1			T15	1		T45	1		T175	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	319	1			T15	8		T175	6		T31	15
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	36	1			T164	1		T165	1		T175	3
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	346	1			T165	27		T175	10		T174	8
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	48	1			T163	3		T84	1		T181	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	451	1			T163	27		T84	5		T181	12

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1521935	1			T3	23130		T5	16957		T8	1
auto[0]	auto[0]	auto[1]	886308	1			T5	4		T9	1		T12	78
auto[0]	auto[1]	auto[0]	334557	1			T3	3153		T5	2976		T9	267
auto[0]	auto[1]	auto[1]	9295	1			T5	1		T15	1		T23	1
auto[1]	auto[0]	auto[0]	12608	1			T3	19		T5	237		T9	25
auto[1]	auto[0]	auto[1]	230	1			T5	1		T9	1		T15	10
auto[1]	auto[1]	auto[0]	3477	1			T3	2		T5	7		T9	1
auto[1]	auto[1]	auto[1]	44	1			T15	2		T164	1		T163	2