Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13728

1

T3

143

T5

211

T9

155

auto[1]

10235

1

T3

138

T5

174

T8

16

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2529	1			T3	26		T5	20		T9	20
values[1]	3231	1			T3	40		T9	63		T15	76
values[2]	2829	1			T3	20		T9	42		T15	45
values[3]	2977	1			T3	49		T9	49		T16	61
values[4]	3009	1			T5	21		T8	16		T9	32
values[5]	2960	1			T3	42		T5	139		T9	20
values[6]	3105	1			T3	44		T5	20		T12	4
values[7]	3323	1			T3	60		T5	185		T9	21

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3175	1			T3	70		T5	40		T9	52
values[1]	2684	1			T3	20		T5	115		T12	4
values[2]	2942	1			T9	105		T15	40		T16	81
values[3]	3151	1			T5	40		T8	16		T9	40
values[4]	3440	1			T3	69		T9	29		T16	80
values[5]	2762	1			T3	40		T5	30		T15	45
values[6]	2774	1			T3	62		T5	139		T15	20
values[7]	3035	1			T3	20		T5	21		T9	21

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	248	1			T3	5		T5	12		T174	14
auto[0]	values[0]	values[1]	149	1			T49	17		T105	2		T175	28
auto[0]	values[0]	values[2]	155	1			T9	12		T21	12		T31	13
auto[0]	values[0]	values[3]	265	1			T156	27		T177	12		T59	6
auto[0]	values[0]	values[4]	196	1			T18	12		T22	9		T176	8
auto[0]	values[0]	values[5]	124	1			T16	15		T163	13		T230	10
auto[0]	values[0]	values[6]	139	1			T174	10		T274	8		T31	9
auto[0]	values[0]	values[7]	216	1			T15	14		T16	12		T49	14
auto[0]	values[1]	values[0]	147	1			T15	11		T48	12		T250	6
auto[0]	values[1]	values[1]	118	1			T22	15		T32	10		T77	2
auto[0]	values[1]	values[2]	260	1			T9	21		T15	28		T156	15
auto[0]	values[1]	values[3]	262	1			T9	13		T156	10		T175	13
auto[0]	values[1]	values[4]	302	1			T3	12		T175	15		T192	23
auto[0]	values[1]	values[5]	195	1			T156	10		T198	8		T59	7
auto[0]	values[1]	values[6]	133	1			T45	12		T49	11		T177	8
auto[0]	values[1]	values[7]	254	1			T3	11		T18	30		T163	40
auto[0]	values[2]	values[0]	142	1			T49	13		T162	12		T175	9
auto[0]	values[2]	values[1]	160	1			T18	13		T275	14		T78	12
auto[0]	values[2]	values[2]	190	1			T9	12		T21	22		T180	10
auto[0]	values[2]	values[3]	237	1			T9	14		T49	15		T176	25
auto[0]	values[2]	values[4]	294	1			T37	8		T45	12		T193	2
auto[0]	values[2]	values[5]	101	1			T3	11		T15	14		T276	14
auto[0]	values[2]	values[6]	154	1			T21	18		T181	8		T97	12
auto[0]	values[2]	values[7]	315	1			T139	20		T45	14		T177	12
auto[0]	values[3]	values[0]	320	1			T9	11		T16	38		T177	9
auto[0]	values[3]	values[1]	139	1			T18	10		T176	13		T185	8
auto[0]	values[3]	values[2]	349	1			T45	10		T21	6		T78	7
auto[0]	values[3]	values[3]	157	1			T48	9		T21	15		T31	7
auto[0]	values[3]	values[4]	178	1			T3	24		T9	25		T277	11
auto[0]	values[3]	values[5]	300	1			T52	49		T18	35		T163	22
auto[0]	values[3]	values[6]	109	1			T18	9		T278	8		T279	10
auto[0]	values[3]	values[7]	201	1			T187	10		T49	60		T156	14
auto[0]	values[4]	values[0]	327	1			T9	24		T18	12		T177	15
auto[0]	values[4]	values[1]	162	1			T78	55		T172	8		T239	12
auto[0]	values[4]	values[2]	198	1			T49	11		T175	17		T31	12
auto[0]	values[4]	values[3]	243	1			T163	29		T175	16		T174	28
auto[0]	values[4]	values[4]	363	1			T16	71		T198	9		T152	11
auto[0]	values[4]	values[5]	329	1			T25	8		T159	8		T177	12
auto[0]	values[4]	values[6]	132	1			T49	11		T19	5		T163	17
auto[0]	values[4]	values[7]	196	1			T5	14		T15	22		T49	13
auto[0]	values[5]	values[0]	165	1			T3	10		T15	14		T18	15
auto[0]	values[5]	values[1]	191	1			T45	11		T36	20		T163	13
auto[0]	values[5]	values[2]	143	1			T9	12		T31	11		T236	14
auto[0]	values[5]	values[3]	158	1			T175	6		T280	8		T281	4
auto[0]	values[5]	values[4]	112	1			T19	6		T180	15		T282	8
auto[0]	values[5]	values[5]	264	1			T22	13		T174	10		T283	12
auto[0]	values[5]	values[6]	390	1			T3	10		T5	134		T49	10
auto[0]	values[5]	values[7]	221	1			T15	9		T16	9		T104	28
auto[0]	values[6]	values[0]	216	1			T3	12		T5	5		T15	17
auto[0]	values[6]	values[1]	303	1			T12	4		T16	33		T152	14
auto[0]	values[6]	values[2]	320	1			T16	72		T33	6		T194	2
auto[0]	values[6]	values[3]	265	1			T18	13		T284	6		T196	16
auto[0]	values[6]	values[4]	118	1			T277	13		T85	13		T180	12
auto[0]	values[6]	values[5]	141	1			T156	10		T32	9		T79	2
auto[0]	values[6]	values[6]	303	1			T3	15		T163	8		T170	13
auto[0]	values[6]	values[7]	132	1			T285	2		T78	17		T224	12
auto[0]	values[7]	values[0]	140	1			T21	12		T152	12		T202	13
auto[0]	values[7]	values[1]	188	1			T3	13		T5	8		T159	6
auto[0]	values[7]	values[2]	102	1			T162	7		T59	8		T286	8
auto[0]	values[7]	values[3]	261	1			T5	16		T16	12		T156	8
auto[0]	values[7]	values[4]	438	1			T49	11		T21	34		T287	76
auto[0]	values[7]	values[5]	116	1			T3	10		T5	22		T162	8
auto[0]	values[7]	values[6]	293	1			T3	10		T15	10		T16	12
auto[0]	values[7]	values[7]	289	1			T9	11		T35	14		T31	38
auto[1]	values[0]	values[0]	119	1			T3	21		T5	8		T174	11
auto[1]	values[0]	values[1]	114	1			T49	3		T175	13		T152	7
auto[1]	values[0]	values[2]	125	1			T9	8		T21	9		T31	15
auto[1]	values[0]	values[3]	107	1			T156	13		T177	27		T59	14
auto[1]	values[0]	values[4]	155	1			T18	8		T22	11		T176	19
auto[1]	values[0]	values[5]	107	1			T16	15		T163	31		T288	6
auto[1]	values[0]	values[6]	146	1			T265	18		T174	10		T31	11
auto[1]	values[0]	values[7]	164	1			T15	65		T16	18		T49	6
auto[1]	values[1]	values[0]	210	1			T15	25		T48	8		T235	20
auto[1]	values[1]	values[1]	176	1			T22	5		T32	10		T209	12
auto[1]	values[1]	values[2]	154	1			T9	22		T15	12		T156	7
auto[1]	values[1]	values[3]	183	1			T9	7		T156	13		T175	40
auto[1]	values[1]	values[4]	172	1			T3	8		T175	5		T192	20
auto[1]	values[1]	values[5]	260	1			T156	13		T198	112		T59	13
auto[1]	values[1]	values[6]	244	1			T45	13		T49	12		T177	12
auto[1]	values[1]	values[7]	161	1			T3	9		T18	8		T163	7
auto[1]	values[2]	values[0]	84	1			T49	7		T162	10		T175	15
auto[1]	values[2]	values[1]	102	1			T18	7		T78	9		T289	11
auto[1]	values[2]	values[2]	213	1			T9	10		T21	19		T180	25
auto[1]	values[2]	values[3]	255	1			T9	6		T49	8		T176	17
auto[1]	values[2]	values[4]	146	1			T45	9		T21	14		T59	15
auto[1]	values[2]	values[5]	86	1			T3	9		T15	31		T290	4
auto[1]	values[2]	values[6]	93	1			T21	24		T181	18		T78	7
auto[1]	values[2]	values[7]	257	1			T45	6		T177	9		T181	53
auto[1]	values[3]	values[0]	258	1			T9	9		T16	23		T177	18
auto[1]	values[3]	values[1]	91	1			T18	25		T176	7		T197	14
auto[1]	values[3]	values[2]	250	1			T45	10		T21	14		T78	13
auto[1]	values[3]	values[3]	122	1			T48	11		T21	7		T31	13
auto[1]	values[3]	values[4]	220	1			T3	25		T9	4		T277	9
auto[1]	values[3]	values[5]	123	1			T18	5		T163	5		T22	7
auto[1]	values[3]	values[6]	49	1			T18	11		T134	6		T222	7
auto[1]	values[3]	values[7]	111	1			T49	23		T156	9		T19	10
auto[1]	values[4]	values[0]	190	1			T9	8		T18	46		T177	5
auto[1]	values[4]	values[1]	137	1			T78	8		T172	15		T239	8
auto[1]	values[4]	values[2]	142	1			T49	11		T175	10		T31	8
auto[1]	values[4]	values[3]	150	1			T8	16		T163	24		T175	9
auto[1]	values[4]	values[4]	141	1			T16	9		T198	11		T152	25
auto[1]	values[4]	values[5]	106	1			T159	12		T177	8		T31	8
auto[1]	values[4]	values[6]	64	1			T49	11		T19	15		T163	3
auto[1]	values[4]	values[7]	129	1			T5	7		T15	7		T49	7
auto[1]	values[5]	values[0]	224	1			T3	12		T15	10		T18	28
auto[1]	values[5]	values[1]	135	1			T45	12		T163	7		T183	22
auto[1]	values[5]	values[2]	116	1			T9	8		T31	9		T236	9
auto[1]	values[5]	values[3]	101	1			T175	19		T216	7		T205	8
auto[1]	values[5]	values[4]	49	1			T19	21		T180	5		T204	5
auto[1]	values[5]	values[5]	262	1			T22	7		T174	10		T78	4
auto[1]	values[5]	values[6]	226	1			T3	10		T5	5		T49	10
auto[1]	values[5]	values[7]	203	1			T15	11		T16	18		T162	42
auto[1]	values[6]	values[0]	229	1			T3	10		T5	15		T15	46
auto[1]	values[6]	values[1]	130	1			T16	11		T38	10		T152	6
auto[1]	values[6]	values[2]	137	1			T16	9		T59	11		T182	6
auto[1]	values[6]	values[3]	107	1			T18	10		T196	4		T199	23
auto[1]	values[6]	values[4]	356	1			T277	10		T85	256		T180	8
auto[1]	values[6]	values[5]	144	1			T156	11		T32	11		T291	14
auto[1]	values[6]	values[6]	141	1			T3	7		T163	45		T170	10
auto[1]	values[6]	values[7]	63	1			T78	7		T292	4		T224	14
auto[1]	values[7]	values[0]	156	1			T21	8		T152	8		T293	10
auto[1]	values[7]	values[1]	389	1			T3	7		T5	107		T159	94
auto[1]	values[7]	values[2]	88	1			T162	13		T59	13		T236	8
auto[1]	values[7]	values[3]	278	1			T5	24		T16	8		T156	12
auto[1]	values[7]	values[4]	200	1			T49	10		T21	13		T59	10
auto[1]	values[7]	values[5]	104	1			T3	10		T5	8		T157	14
auto[1]	values[7]	values[6]	158	1			T3	10		T15	10		T16	8
auto[1]	values[7]	values[7]	123	1			T9	10		T31	11		T256	18