Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2267581	1			T1	1		T3	81356		T4	1
all_pins[1]	2267581	1			T1	1		T3	81356		T4	1
all_pins[2]	2267581	1			T1	1		T3	81356		T4	1
all_pins[3]	2267581	1			T1	1		T3	81356		T4	1
all_pins[4]	2267581	1			T1	1		T3	81356		T4	1
all_pins[5]	2267581	1			T1	1		T3	81356		T4	1
all_pins[6]	2267581	1			T1	1		T3	81356		T4	1
all_pins[7]	2267581	1			T1	1		T3	81356		T4	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	18112187	1			T1	8		T3	650848		T4	8
values[0x1]	28461	1			T17	11		T18	14		T19	10
transitions[0x0=>0x1]	27745	1			T17	10		T18	9		T19	9
transitions[0x1=>0x0]	27762	1			T17	10		T18	9		T19	9

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2267348	1			T1	1		T3	81356		T4	1
all_pins[0]	values[0x1]	233	1			T17	2		T18	1		T20	7
all_pins[0]	transitions[0x0=>0x1]	168	1			T17	2		T18	1		T20	6
all_pins[0]	transitions[0x1=>0x0]	277	1			T17	1		T18	1		T19	2
all_pins[1]	values[0x0]	2267239	1			T1	1		T3	81356		T4	1
all_pins[1]	values[0x1]	342	1			T17	1		T18	1		T19	2
all_pins[1]	transitions[0x0=>0x1]	217	1			T17	1		T19	2		T20	2
all_pins[1]	transitions[0x1=>0x0]	208	1			T17	2		T18	2		T20	6
all_pins[2]	values[0x0]	2267248	1			T1	1		T3	81356		T4	1
all_pins[2]	values[0x1]	333	1			T17	2		T18	3		T20	6
all_pins[2]	transitions[0x0=>0x1]	280	1			T17	2		T18	1		T20	6
all_pins[2]	transitions[0x1=>0x0]	160	1			T18	1		T19	4		T20	4
all_pins[3]	values[0x0]	2267368	1			T1	1		T3	81356		T4	1
all_pins[3]	values[0x1]	213	1			T18	3		T19	4		T20	4
all_pins[3]	transitions[0x0=>0x1]	155	1			T18	2		T19	4		T20	3
all_pins[3]	transitions[0x1=>0x0]	167	1			T17	2		T18	1		T20	1
all_pins[4]	values[0x0]	2267356	1			T1	1		T3	81356		T4	1
all_pins[4]	values[0x1]	225	1			T17	2		T18	2		T20	2
all_pins[4]	transitions[0x0=>0x1]	175	1			T17	2		T18	1		T20	1
all_pins[4]	transitions[0x1=>0x0]	704	1			T17	2		T18	3		T19	2
all_pins[5]	values[0x0]	2266827	1			T1	1		T3	81356		T4	1
all_pins[5]	values[0x1]	754	1			T17	2		T18	4		T19	2
all_pins[5]	transitions[0x0=>0x1]	490	1			T17	2		T18	4		T19	1
all_pins[5]	transitions[0x1=>0x0]	25895	1			T17	1		T19	1		T20	5
all_pins[6]	values[0x0]	2241422	1			T1	1		T3	81356		T4	1
all_pins[6]	values[0x1]	26159	1			T17	1		T19	2		T20	5
all_pins[6]	transitions[0x0=>0x1]	26118	1			T17	1		T19	2		T20	5
all_pins[6]	transitions[0x1=>0x0]	161	1			T17	1		T20	4		T21	2
all_pins[7]	values[0x0]	2267379	1			T1	1		T3	81356		T4	1
all_pins[7]	values[0x1]	202	1			T17	1		T20	4		T21	4
all_pins[7]	transitions[0x0=>0x1]	142	1			T20	3		T21	2		T22	5
all_pins[7]	transitions[0x1=>0x0]	190	1			T17	1		T18	1		T20	6