Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	247	1			T3	5		T5	1		T15	8
auto[ReadAddrCrossIntoMailbox]	232	1			T3	2		T5	3		T9	2
auto[ReadAddrCrossOutOfMailbox]	269	1			T3	6		T5	1		T9	6
auto[ReadAddrCrossAllMailbox]	128	1			T3	1		T5	1		T9	1
auto[ReadAddrOutsideMailbox]	2876	1			T3	44		T5	27		T8	4

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1863

1

T3

29

T5

25

T8

2

auto[1]

1889

1

T3

29

T5

8

T8

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	643	1			T3	9		T5	5		T9	7
read_ops[0x0b]	650	1			T3	12		T5	4		T9	6
read_ops[0x3b]	659	1			T3	11		T5	2		T9	6
read_ops[0x6b]	639	1			T3	8		T5	9		T9	9
read_ops[0xbb]	576	1			T3	8		T5	9		T8	2
read_ops[0xeb]	585	1			T3	10		T5	4		T8	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	24	1			T15	2		T48	1		T19	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	18	1			T3	1		T15	1		T49	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	18	1			T19	1		T177	1		T277	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T5	1		T15	1		T49	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	17	1			T9	1		T16	2		T274	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	19	1			T22	1		T59	2		T274	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	11	1			T49	1		T163	1		T197	2
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T9	1		T49	1		T156	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	240	1			T3	4		T5	3		T15	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	251	1			T3	4		T5	1		T9	5
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	20	1			T16	1		T162	1		T59	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	30	1			T3	2		T15	2		T45	2
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T3	1		T5	2		T9	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	16	1			T15	1		T159	1		T54	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T3	1		T162	1		T163	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T9	1		T15	1		T16	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	9	1			T16	1		T49	1		T18	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	8	1			T3	1		T18	1		T180	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	253	1			T3	3		T5	1		T9	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	243	1			T3	4		T5	1		T9	3
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	20	1			T49	1		T163	1		T181	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	17	1			T18	1		T32	1		T76	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	17	1			T16	1		T18	1		T21	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	20	1			T15	1		T16	1		T49	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T49	1		T19	2		T163	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T9	1		T16	1		T22	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T16	1		T49	1		T286	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T16	1		T49	1		T21	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	251	1			T3	7		T5	2		T9	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	254	1			T3	4		T9	4		T15	3
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	27	1			T16	1		T162	1		T163	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	26	1			T3	1		T15	1		T16	3
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	13	1			T49	2		T163	1		T294	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	11	1			T15	1		T45	1		T48	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T5	1		T163	1		T294	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	33	1			T3	2		T9	1		T159	2
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	10	1			T5	1		T49	1		T21	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T163	2		T59	1		T31	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	234	1			T3	2		T5	5		T9	3
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	246	1			T3	3		T5	2		T9	5
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	22	1			T5	1		T15	1		T16	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	16	1			T3	1		T15	1		T197	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T156	1		T159	1		T175	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	15	1			T49	2		T19	1		T162	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	19	1			T3	2		T49	1		T31	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T9	1		T19	1		T162	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	8	1			T45	1		T156	1		T59	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	4	1			T197	1		T230	1		T134	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	236	1			T3	4		T5	7		T8	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	213	1			T3	1		T5	1		T8	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	14	1			T16	1		T49	1		T18	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	13	1			T48	1		T156	1		T172	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	29	1			T3	1		T156	2		T163	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T9	1		T32	1		T185	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	13	1			T9	1		T159	1		T198	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T3	1		T162	1		T175	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	8	1			T31	1		T152	1		T295	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T177	2		T59	2		T277	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	216	1			T3	4		T5	2		T8	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	239	1			T3	4		T5	2		T8	1