Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.63	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	2	126	98.44

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	2	126	98.44	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2933	1			T5	135		T9	43		T37	8
values[1]	2717	1			T3	40		T5	21		T9	71
values[2]	3711	1			T3	44		T5	40		T8	16
values[3]	2863	1			T3	64		T5	139		T15	91
values[4]	2330	1			T3	25		T5	30		T9	72
values[5]	3542	1			T3	22		T9	21		T15	20
values[6]	2796	1			T3	40		T15	65		T16	50
values[7]	3071	1			T3	46		T5	20		T9	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2528	1			T3	20		T5	21		T9	63
values[1]	3039	1			T3	22		T5	115		T9	20
values[2]	2787	1			T3	20		T5	20		T9	20
values[3]	3408	1			T3	49		T8	16		T9	52
values[4]	3054	1			T3	40		T12	4		T15	65
values[5]	2927	1			T3	22		T5	30		T9	43
values[6]	2708	1			T5	60		T9	29		T15	20
values[7]	3512	1			T3	108		T5	139		T9	20

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23568

1

T3

273

T5

382

T8

14

auto[1]

395

1

T3

8

T5

3

T8

2

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	2	126	98.44	2

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[1]]	[values[5]]	0	1	1
[auto[1]]	[values[3]]	[values[7]]	0	1	1

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	227	1			T162	29		T172	20		T173	34
auto[0]	values[0]	values[1]	654	1			T5	115		T9	20		T21	20
auto[0]	values[0]	values[2]	423	1			T5	19		T37	8		T163	53
auto[0]	values[0]	values[3]	358	1			T156	17		T174	18		T78	60
auto[0]	values[0]	values[4]	201	1			T45	17		T175	24		T176	18
auto[0]	values[0]	values[5]	353	1			T9	23		T177	21		T178	4
auto[0]	values[0]	values[6]	201	1			T174	19		T179	12		T180	20
auto[0]	values[0]	values[7]	461	1			T163	20		T174	25		T78	20
auto[0]	values[1]	values[0]	419	1			T5	21		T9	22		T181	61
auto[0]	values[1]	values[1]	381	1			T15	115		T31	39		T182	6
auto[0]	values[1]	values[2]	143	1			T183	22		T134	21		T184	14
auto[0]	values[1]	values[3]	253	1			T18	20		T156	20		T185	8
auto[0]	values[1]	values[4]	315	1			T49	20		T162	22		T22	20
auto[0]	values[1]	values[5]	250	1			T16	44		T18	20		T186	20
auto[0]	values[1]	values[6]	464	1			T9	28		T162	40		T175	24
auto[0]	values[1]	values[7]	444	1			T3	38		T9	20		T49	21
auto[0]	values[2]	values[0]	355	1			T9	20		T16	30		T177	39
auto[0]	values[2]	values[1]	547	1			T3	22		T159	20		T22	40
auto[0]	values[2]	values[2]	443	1			T49	20		T18	58		T156	23
auto[0]	values[2]	values[3]	509	1			T8	14		T49	22		T18	36
auto[0]	values[2]	values[4]	543	1			T15	45		T187	10		T105	2
auto[0]	values[2]	values[5]	259	1			T18	40		T32	20		T188	14
auto[0]	values[2]	values[6]	394	1			T5	38		T48	19		T18	23
auto[0]	values[2]	values[7]	585	1			T3	21		T16	81		T163	43
auto[0]	values[3]	values[0]	241	1			T3	20		T16	20		T59	20
auto[0]	values[3]	values[1]	297	1			T16	78		T45	20		T21	22
auto[0]	values[3]	values[2]	463	1			T15	20		T177	18		T189	6
auto[0]	values[3]	values[3]	534	1			T3	24		T49	55		T34	4
auto[0]	values[3]	values[4]	332	1			T48	18		T25	8		T190	4
auto[0]	values[3]	values[5]	429	1			T15	51		T21	20		T176	20
auto[0]	values[3]	values[6]	266	1			T15	20		T159	99		T19	26
auto[0]	values[3]	values[7]	262	1			T3	20		T5	139		T177	20
auto[0]	values[4]	values[0]	168	1			T18	42		T191	14		T172	20
auto[0]	values[4]	values[1]	236	1			T177	20		T21	20		T97	12
auto[0]	values[4]	values[2]	235	1			T21	23		T59	20		T31	20
auto[0]	values[4]	values[3]	283	1			T3	23		T9	50		T16	20
auto[0]	values[4]	values[4]	266	1			T15	19		T177	27		T59	20
auto[0]	values[4]	values[5]	495	1			T5	30		T9	20		T16	26
auto[0]	values[4]	values[6]	268	1			T163	20		T22	29		T59	26
auto[0]	values[4]	values[7]	329	1			T49	26		T59	16		T192	32
auto[0]	values[5]	values[0]	437	1			T9	20		T18	55		T31	20
auto[0]	values[5]	values[1]	212	1			T193	2		T21	21		T173	20
auto[0]	values[5]	values[2]	497	1			T15	20		T16	19		T45	20
auto[0]	values[5]	values[3]	499	1			T49	20		T35	14		T194	2
auto[0]	values[5]	values[4]	365	1			T195	4		T196	27		T197	20
auto[0]	values[5]	values[5]	398	1			T3	22		T36	20		T162	57
auto[0]	values[5]	values[6]	488	1			T16	20		T45	45		T19	25
auto[0]	values[5]	values[7]	602	1			T163	37		T78	35		T152	33
auto[0]	values[6]	values[0]	442	1			T156	22		T21	27		T31	63
auto[0]	values[6]	values[1]	225	1			T16	30		T139	20		T198	20
auto[0]	values[6]	values[2]	268	1			T3	19		T177	20		T131	2
auto[0]	values[6]	values[3]	289	1			T15	29		T156	21		T163	31
auto[0]	values[6]	values[4]	568	1			T3	20		T54	10		T85	267
auto[0]	values[6]	values[5]	380	1			T15	34		T21	20		T198	20
auto[0]	values[6]	values[6]	270	1			T16	19		T162	20		T163	27
auto[0]	values[6]	values[7]	308	1			T156	21		T21	28		T59	45
auto[0]	values[7]	values[0]	204	1			T21	21		T175	20		T172	23
auto[0]	values[7]	values[1]	431	1			T49	39		T156	21		T192	20
auto[0]	values[7]	values[2]	267	1			T9	20		T49	23		T156	20
auto[0]	values[7]	values[3]	618	1			T132	4		T59	21		T199	35
auto[0]	values[7]	values[4]	410	1			T3	20		T12	4		T38	8
auto[0]	values[7]	values[5]	326	1			T104	28		T78	25		T180	35
auto[0]	values[7]	values[6]	317	1			T5	20		T52	49		T157	14
auto[0]	values[7]	values[7]	461	1			T3	24		T21	20		T175	25
auto[1]	values[0]	values[0]	4	1			T162	1		T173	1		T200	1
auto[1]	values[0]	values[1]	4	1			T176	1		T59	1		T134	1
auto[1]	values[0]	values[2]	3	1			T5	1		T78	1		T172	1
auto[1]	values[0]	values[3]	15	1			T156	3		T174	2		T78	3
auto[1]	values[0]	values[4]	8	1			T45	3		T176	2		T201	3
auto[1]	values[0]	values[5]	4	1			T172	1		T180	3		-	-
auto[1]	values[0]	values[6]	2	1			T174	1		T202	1		-	-
auto[1]	values[0]	values[7]	15	1			T152	4		T203	3		T204	1
auto[1]	values[1]	values[0]	5	1			T32	2		T78	1		T205	1
auto[1]	values[1]	values[1]	5	1			T31	1		T206	2		T207	1
auto[1]	values[1]	values[2]	4	1			T134	2		T208	2		-	-
auto[1]	values[1]	values[3]	3	1			T170	1		T209	1		T210	1
auto[1]	values[1]	values[4]	5	1			T173	1		T211	2		T212	1
auto[1]	values[1]	values[6]	11	1			T9	1		T162	1		T175	1
auto[1]	values[1]	values[7]	15	1			T3	2		T18	4		T19	1
auto[1]	values[2]	values[0]	9	1			T213	4		T200	1		T214	1
auto[1]	values[2]	values[1]	16	1			T152	2		T85	7		T180	3
auto[1]	values[2]	values[2]	3	1			T199	1		T53	1		T215	1
auto[1]	values[2]	values[3]	15	1			T8	2		T18	2		T163	2
auto[1]	values[2]	values[4]	10	1			T32	2		T216	4		T217	2
auto[1]	values[2]	values[5]	1	1			T218	1		-	-		-	-
auto[1]	values[2]	values[6]	8	1			T5	2		T48	1		T85	1
auto[1]	values[2]	values[7]	14	1			T3	1		T163	4		T21	3
auto[1]	values[3]	values[0]	2	1			T219	1		T220	1		-	-
auto[1]	values[3]	values[1]	3	1			T16	2		T45	1		-	-
auto[1]	values[3]	values[2]	18	1			T177	2		T85	2		T170	1
auto[1]	values[3]	values[3]	3	1			T49	2		T221	1		-	-
auto[1]	values[3]	values[4]	8	1			T48	2		T222	1		T223	1
auto[1]	values[3]	values[5]	3	1			T224	1		T207	1		T135	1
auto[1]	values[3]	values[6]	2	1			T159	1		T19	1		-	-
auto[1]	values[4]	values[0]	5	1			T18	1		T221	1		T225	1
auto[1]	values[4]	values[1]	10	1			T134	2		T135	4		T210	1
auto[1]	values[4]	values[2]	2	1			T42	1		T209	1		-	-
auto[1]	values[4]	values[3]	9	1			T3	2		T9	2		T16	1
auto[1]	values[4]	values[4]	4	1			T15	1		T219	1		T135	1
auto[1]	values[4]	values[5]	10	1			T16	1		T172	5		T221	2
auto[1]	values[4]	values[6]	6	1			T22	2		T226	2		T53	1
auto[1]	values[4]	values[7]	4	1			T59	4		-	-		-	-
auto[1]	values[5]	values[0]	4	1			T9	1		T227	2		T223	1
auto[1]	values[5]	values[1]	1	1			T201	1		-	-		-	-
auto[1]	values[5]	values[2]	10	1			T16	1		T49	1		T32	2
auto[1]	values[5]	values[3]	6	1			T197	1		T228	3		T229	2
auto[1]	values[5]	values[4]	5	1			T196	1		T224	2		T230	1
auto[1]	values[5]	values[5]	5	1			T162	1		T224	2		T225	2
auto[1]	values[5]	values[6]	6	1			T45	3		T231	1		T209	1
auto[1]	values[5]	values[7]	7	1			T78	1		T152	3		T232	1
auto[1]	values[6]	values[0]	3	1			T224	2		T134	1		-	-
auto[1]	values[6]	values[1]	5	1			T31	2		T225	2		T233	1
auto[1]	values[6]	values[2]	5	1			T3	1		T219	3		T229	1
auto[1]	values[6]	values[3]	6	1			T156	2		T163	2		T175	1
auto[1]	values[6]	values[4]	10	1			T85	2		T196	1		T232	3
auto[1]	values[6]	values[5]	13	1			T15	2		T21	2		T30	1
auto[1]	values[6]	values[6]	3	1			T16	1		T209	1		T217	1
auto[1]	values[6]	values[7]	1	1			T192	1		-	-		-	-
auto[1]	values[7]	values[0]	3	1			T218	2		T234	1		-	-
auto[1]	values[7]	values[1]	12	1			T49	1		T156	1		T235	4
auto[1]	values[7]	values[2]	3	1			T78	1		T180	1		T236	1
auto[1]	values[7]	values[3]	8	1			T59	2		T212	1		T230	3
auto[1]	values[7]	values[4]	4	1			T38	2		T162	1		T210	1
auto[1]	values[7]	values[5]	1	1			T237	1		-	-		-	-
auto[1]	values[7]	values[6]	2	1			T238	1		T239	1		-	-
auto[1]	values[7]	values[7]	4	1			T3	2		T21	1		T214	1