Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1713

1

T1

15

T3

7

T4

11

auto[1]

1725

1

T1

16

T3

11

T4

15

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1785

1

T3

9

T9

7

T45

1

auto[1]

1653

1

T1

31

T3

9

T4

26

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2748

1

T1

31

T3

13

T4

26

auto[1]

690

1

T3

5

T9

2

T43

7

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	714	1			T1	6		T3	4		T4	7
valid[1]	678	1			T1	8		T3	5		T4	7
valid[2]	668	1			T1	8		T3	2		T4	2
valid[3]	660	1			T1	4		T3	2		T4	6
valid[4]	718	1			T1	5		T3	5		T4	4

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	110	1			T3	1		T9	1		T45	1
auto[0]	auto[0]	valid[0]	auto[1]	184	1			T1	4		T3	1		T4	1
auto[0]	auto[0]	valid[1]	auto[0]	106	1			T3	1		T39	1		T49	1
auto[0]	auto[0]	valid[1]	auto[1]	161	1			T1	4		T3	1		T4	3
auto[0]	auto[0]	valid[2]	auto[0]	110	1			T9	1		T50	1		T161	1
auto[0]	auto[0]	valid[2]	auto[1]	153	1			T1	3		T4	1		T6	4
auto[0]	auto[0]	valid[3]	auto[0]	97	1			T9	2		T46	1		T43	1
auto[0]	auto[0]	valid[3]	auto[1]	149	1			T1	2		T4	4		T6	5
auto[0]	auto[0]	valid[4]	auto[0]	120	1			T39	1		T49	1		T19	1
auto[0]	auto[0]	valid[4]	auto[1]	184	1			T1	2		T4	2		T6	4
auto[0]	auto[1]	valid[0]	auto[0]	118	1			T43	1		T39	1		T18	4
auto[0]	auto[1]	valid[0]	auto[1]	150	1			T1	2		T3	1		T4	6
auto[0]	auto[1]	valid[1]	auto[0]	106	1			T3	1		T39	2		T18	1
auto[0]	auto[1]	valid[1]	auto[1]	177	1			T1	4		T3	1		T4	4
auto[0]	auto[1]	valid[2]	auto[0]	100	1			T39	1		T49	1		T50	1
auto[0]	auto[1]	valid[2]	auto[1]	174	1			T1	5		T3	1		T4	1
auto[0]	auto[1]	valid[3]	auto[0]	109	1			T43	1		T39	1		T49	2
auto[0]	auto[1]	valid[3]	auto[1]	163	1			T1	2		T3	2		T4	2
auto[0]	auto[1]	valid[4]	auto[0]	119	1			T3	1		T9	1		T39	1
auto[0]	auto[1]	valid[4]	auto[1]	158	1			T1	3		T3	2		T4	2
auto[1]	auto[0]	valid[0]	auto[0]	71	1			T3	1		T39	1		T306	1
auto[1]	auto[0]	valid[1]	auto[0]	65	1			T3	1		T39	1		T19	1
auto[1]	auto[0]	valid[2]	auto[0]	53	1			T156	2		T19	2		T20	1
auto[1]	auto[0]	valid[3]	auto[0]	74	1			T43	2		T50	1		T156	1
auto[1]	auto[0]	valid[4]	auto[0]	76	1			T3	1		T43	1		T115	1
auto[1]	auto[1]	valid[0]	auto[0]	81	1			T9	1		T50	1		T18	1
auto[1]	auto[1]	valid[1]	auto[0]	63	1			T39	1		T49	1		T50	1
auto[1]	auto[1]	valid[2]	auto[0]	78	1			T3	1		T43	1		T39	1
auto[1]	auto[1]	valid[3]	auto[0]	68	1			T43	1		T161	1		T20	1
auto[1]	auto[1]	valid[4]	auto[0]	61	1			T3	1		T9	1		T43	2

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal