Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45479

1

T3

334

T5

39

T9

168

auto[1]

18199

1

T1

464

T3

88

T4

324

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46917

1

T1

464

T3

279

T4

324

auto[1]

16761

1

T3

143

T5

21

T9

58

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	32792	1			T1	244		T3	187		T4	173
others[1]	5266	1			T1	32		T3	40		T4	25
others[2]	5395	1			T1	29		T3	40		T4	31
others[3]	6132	1			T1	39		T3	46		T4	35
interest[1]	3516	1			T1	25		T3	32		T4	14
interest[4]	21485	1			T1	154		T3	126		T4	104
interest[64]	10577	1			T1	95		T3	77		T4	46

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	14660	1			T3	96		T5	6		T9	60
auto[0]	auto[0]	others[1]	2455	1			T3	17		T5	3		T9	10
auto[0]	auto[0]	others[2]	2462	1			T3	21		T5	1		T9	6
auto[0]	auto[0]	others[3]	2698	1			T3	16		T5	3		T9	11
auto[0]	auto[0]	interest[1]	1659	1			T3	12		T5	1		T9	4
auto[0]	auto[0]	interest[4]	9516	1			T3	67		T5	3		T9	36
auto[0]	auto[0]	interest[64]	4784	1			T3	29		T5	4		T9	19
auto[0]	auto[1]	others[0]	9554	1			T1	244		T3	30		T4	173
auto[0]	auto[1]	others[1]	1439	1			T1	32		T3	8		T4	25
auto[0]	auto[1]	others[2]	1521	1			T1	29		T3	8		T4	31
auto[0]	auto[1]	others[3]	1722	1			T1	39		T3	13		T4	35
auto[0]	auto[1]	interest[1]	909	1			T1	25		T3	9		T4	14
auto[0]	auto[1]	interest[4]	6329	1			T1	154		T3	19		T4	104
auto[0]	auto[1]	interest[64]	3054	1			T1	95		T3	20		T4	46
auto[1]	auto[0]	others[0]	8578	1			T3	61		T5	14		T9	33
auto[1]	auto[0]	others[1]	1372	1			T3	15		T9	4		T45	5
auto[1]	auto[0]	others[2]	1412	1			T3	11		T5	2		T9	4
auto[1]	auto[0]	others[3]	1712	1			T3	17		T9	5		T45	10
auto[1]	auto[0]	interest[1]	948	1			T3	11		T5	2		T9	6
auto[1]	auto[0]	interest[4]	5640	1			T3	40		T5	8		T9	22
auto[1]	auto[0]	interest[64]	2739	1			T3	28		T5	3		T9	6

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal