Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2370230	1			T1	2		T2	20028		T3	1
all_values[1]	2370230	1			T1	2		T2	20028		T3	1
all_values[2]	2370230	1			T1	2		T2	20028		T3	1
all_values[3]	2370230	1			T1	2		T2	20028		T3	1
all_values[4]	2370230	1			T1	2		T2	20028		T3	1
all_values[5]	2370230	1			T1	2		T2	20028		T3	1
all_values[6]	2370230	1			T1	2		T2	20028		T3	1
all_values[7]	2370230	1			T1	2		T2	20028		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18570384

1

T1

16

T2

160224

T3

8

auto[1]

391456

1

T14

65

T17

83

T19

91080

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18937603

1

T1

16

T2

160126

T3

8

auto[1]

24237

1

T2

98

T13

127

T14

157

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2357667	1			T1	2		T2	19963		T3	1
all_values[0]	auto[0]	auto[1]	11219	1			T2	65		T13	65		T14	41
all_values[0]	auto[1]	auto[0]	1115	1			T14	7		T17	9		T127	1
all_values[0]	auto[1]	auto[1]	229	1			T14	6		T17	3		T19	1
all_values[1]	auto[0]	auto[0]	2320979	1			T1	2		T2	19995		T3	1
all_values[1]	auto[0]	auto[1]	7231	1			T2	33		T13	31		T14	39
all_values[1]	auto[1]	auto[0]	41700	1			T14	7		T17	4		T19	1
all_values[1]	auto[1]	auto[1]	320	1			T14	3		T17	4		T19	2
all_values[2]	auto[0]	auto[0]	2340982	1			T1	2		T2	20028		T3	1
all_values[2]	auto[0]	auto[1]	2851	1			T13	31		T14	38		T17	15
all_values[2]	auto[1]	auto[0]	26166	1			T14	3		T17	4		T19	22760
all_values[2]	auto[1]	auto[1]	231	1			T14	5		T17	5		T19	7
all_values[3]	auto[0]	auto[0]	2308191	1			T1	2		T2	20028		T3	1
all_values[3]	auto[0]	auto[1]	208	1			T14	1		T17	5		T19	5
all_values[3]	auto[1]	auto[0]	61623	1			T14	8		T17	4		T21	2
all_values[3]	auto[1]	auto[1]	208	1			T17	4		T19	2		T127	1
all_values[4]	auto[0]	auto[0]	2349681	1			T1	2		T2	20028		T3	1
all_values[4]	auto[0]	auto[1]	234	1			T14	4		T17	4		T19	4
all_values[4]	auto[1]	auto[0]	20099	1			T14	6		T17	8		T19	1
all_values[4]	auto[1]	auto[1]	216	1			T14	2		T17	3		T19	1
all_values[5]	auto[0]	auto[0]	2300448	1			T1	2		T2	20028		T3	1
all_values[5]	auto[0]	auto[1]	211	1			T14	3		T17	7		T19	1
all_values[5]	auto[1]	auto[0]	69375	1			T14	2		T17	4		T19	22768
all_values[5]	auto[1]	auto[1]	196	1			T14	1		T17	4		T19	1
all_values[6]	auto[0]	auto[0]	2284637	1			T1	2		T2	20028		T3	1
all_values[6]	auto[0]	auto[1]	204	1			T14	5		T17	2		T19	1
all_values[6]	auto[1]	auto[0]	85160	1			T14	6		T17	11		T19	22765
all_values[6]	auto[1]	auto[1]	229	1			T17	5		T19	3		T127	4
all_values[7]	auto[0]	auto[0]	2285417	1			T1	2		T2	20028		T3	1
all_values[7]	auto[0]	auto[1]	224	1			T14	3		T17	3		T19	2
all_values[7]	auto[1]	auto[0]	84363	1			T14	3		T17	7		T19	22765
all_values[7]	auto[1]	auto[1]	226	1			T14	6		T17	4		T19	3