Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	31449	1			T2	59		T3	2		T5	10
auto[SpiFlashAddrCfg]	6144	1			T2	22		T13	51		T14	22
auto[SpiFlashAddr3b]	7204	1			T2	17		T3	6		T13	46
auto[SpiFlashAddr4b]	6053	1			T2	11		T11	2		T13	47

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29089

1

T2

53

T3

8

T5

10

auto[1]

21761

1

T2

56

T13

129

T14

29

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26557

1

T2

55

T5

10

T13

191

auto[1]

24293

1

T2

54

T3

8

T11

2

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	35130	1			T2	75		T3	2		T5	10
values[1]	856	1			T2	3		T13	8		T14	2
values[2]	1167	1			T2	6		T13	11		T14	2
values[3]	1187	1			T2	2		T13	2		T14	1
values[4]	1237	1			T3	2		T13	13		T14	4
values[5]	1161	1			T2	2		T13	12		T14	1
values[6]	1158	1			T2	7		T13	10		T14	2
values[7]	1157	1			T3	4		T13	10		T14	4
values[8]	7797	1			T2	14		T11	2		T13	57

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26752

1

T3

8

T5

10

T11

2

auto[1]

24098

1

T2

109

T14

142

T18

210

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

48149

1

T2

89

T3

8

T5

10

write

2701

1

T2

20

T13

22

T14

17

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

15444

1

T2

38

T3

2

T5

10

valids[0x1]

35406

1

T2

71

T3

6

T13

194

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1247	1			T2	4		T3	2		T13	6
internal_process_ops[0x5a]	1283	1			T2	2		T3	4		T13	4
internal_process_ops[0x05]	20243	1			T2	14		T13	86		T14	46
internal_process_ops[0x35]	1229	1			T2	7		T13	11		T14	3
internal_process_ops[0x15]	1262	1			T2	3		T13	9		T14	4
internal_process_ops[0x03]	897	1			T2	1		T13	7		T14	1
internal_process_ops[0x0b]	831	1			T13	6		T16	2		T17	6
internal_process_ops[0x3b]	837	1			T11	2		T13	7		T14	1
internal_process_ops[0x6b]	831	1			T2	1		T13	11		T16	2
internal_process_ops[0xbb]	862	1			T13	9		T16	4		T17	7
internal_process_ops[0xeb]	815	1			T3	2		T13	8		T14	1

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

49524

1

T2

100

T3

8

T5

10

auto[1]

1326

1

T2

9

T13

9

T14

12

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

48964

1

T2

102

T3

8

T5

10

auto[1]

1886

1

T2

7

T13

11

T14

8

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9348

1

T3

2

T5

10

T13

113

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6006

1

T13

52

T16

12

T17

89

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1687

1

T13

21

T17

19

T18

1

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1414

1

T13

24

T17

19

T18

5

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2008

1

T3

6

T13

22

T17

23

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1692

1

T13

18

T16

2

T17

21

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1743

1

T11

2

T13

25

T17

25

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1499

1

T13

21

T16

4

T17

24

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

101

1

T13

1

T33

2

T35

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

82

1

T13

1

T17

2

T33

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

83

1

T13

6

T33

2

T34

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

81

1

T13

1

T16

2

T33

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

102

1

T17

1

T39

6

T33

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

80

1

T13

2

T33

2

T19

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

74

1

T17

2

T33

4

T35

3

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

79

1

T13

4

T17

1

T35

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

124

1

T13

4

T39

2

T33

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

67

1

T33

3

T36

1

T19

4

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

68

1

T13

2

T33

3

T35

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

81

1

T17

3

T33

5

T35

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

114

1

T33

2

T35

2

T36

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

73

1

T17

2

T36

3

T19

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

72

1

T17

2

T33

3

T35

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

74

1

T13

1

T33

2

T34

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9164

1

T2

29

T14

76

T18

47

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6206

1

T2

22

T14

3

T18

49

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1215

1

T2

6

T14

9

T18

14

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1152

1

T2

12

T14

8

T18

21

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1450

1

T2

9

T14

13

T18

14

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1412

1

T2

5

T14

5

T18

19

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1110

1

T2

1

T14

4

T18

20

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1043

1

T2

5

T14

7

T18

9

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

103

1

T2

3

T14

2

T43

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

88

1

T2

1

T18

3

T43

4

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

91

1

T2

4

T43

4

T73

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

96

1

T14

1

T18

3

T43

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

72

1

T14

1

T142

2

T73

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

97

1

T14

2

T18

1

T43

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

88

1

T2

2

T14

1

T43

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

84

1

T2

2

T14

1

T18

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

45

1

T43

1

T73

1

T143

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

81

1

T2

2

T14

6

T142

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

72

1

T18

1

T142

1

T73

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

104

1

T2

1

T14

2

T43

4

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

76

1

T144

4

T73

2

T145

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

59

1

T2

2

T18

3

T73

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

90

1

T2

2

T14

1

T18

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

100

1

T2

1

T18

1

T43

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3256	1			T5	10		T13	47		T16	4
auto[0]	values[0]	valids[0x1]	14469	1			T3	2		T13	148		T16	8
auto[0]	values[1]	valids[0x1]	458	1			T13	8		T17	2		T18	3
auto[0]	values[2]	valids[0x0]	410	1			T13	9		T17	1		T18	1
auto[0]	values[2]	valids[0x1]	259	1			T13	2		T17	2		T33	1
auto[0]	values[3]	valids[0x0]	437	1			T13	2		T17	4		T33	9
auto[0]	values[3]	valids[0x1]	254	1			T17	4		T33	4		T35	1
auto[0]	values[4]	valids[0x0]	499	1			T3	2		T13	12		T16	4
auto[0]	values[4]	valids[0x1]	225	1			T13	1		T34	3		T35	2
auto[0]	values[5]	valids[0x0]	402	1			T13	6		T17	5		T33	17
auto[0]	values[5]	valids[0x1]	251	1			T13	6		T17	2		T33	2
auto[0]	values[6]	valids[0x0]	423	1			T13	8		T17	6		T33	10
auto[0]	values[6]	valids[0x1]	241	1			T13	2		T17	6		T18	1
auto[0]	values[7]	valids[0x0]	446	1			T13	5		T17	7		T33	7
auto[0]	values[7]	valids[0x1]	238	1			T3	4		T13	5		T17	3
auto[0]	values[8]	valids[0x0]	2798	1			T11	2		T13	35		T17	43
auto[0]	values[8]	valids[0x1]	1686	1			T13	22		T16	4		T17	14
auto[1]	values[0]	valids[0x0]	3006	1			T2	21		T14	23		T18	23
auto[1]	values[0]	valids[0x1]	14399	1			T2	54		T14	85		T18	91
auto[1]	values[1]	valids[0x1]	398	1			T2	3		T14	2		T18	6
auto[1]	values[2]	valids[0x0]	277	1			T2	2		T14	2		T18	2
auto[1]	values[2]	valids[0x1]	221	1			T2	4		T18	3		T43	3
auto[1]	values[3]	valids[0x0]	297	1			T2	1		T18	3		T43	7
auto[1]	values[3]	valids[0x1]	199	1			T2	1		T14	1		T43	5
auto[1]	values[4]	valids[0x0]	305	1			T14	3		T18	2		T43	9
auto[1]	values[4]	valids[0x1]	208	1			T14	1		T18	1		T43	4
auto[1]	values[5]	valids[0x0]	302	1			T18	4		T43	3		T142	9
auto[1]	values[5]	valids[0x1]	206	1			T2	2		T14	1		T18	1
auto[1]	values[6]	valids[0x0]	320	1			T2	5		T14	2		T18	6
auto[1]	values[6]	valids[0x1]	174	1			T2	2		T18	6		T142	2
auto[1]	values[7]	valids[0x0]	311	1			T14	3		T18	8		T142	1
auto[1]	values[7]	valids[0x1]	162	1			T14	1		T18	4		T43	7
auto[1]	values[8]	valids[0x0]	1955	1			T2	9		T14	5		T18	29
auto[1]	values[8]	valids[0x1]	1358	1			T2	5		T14	13		T18	21