Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2840957

1

T1

1

T2

6549

T3

230

auto[1]

18934

1

T2

9

T13

78

T14

42

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

898310

1

T1

1

T2

34

T3

230

auto[1]

1961581

1

T2

6524

T13

22182

T14

5041

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	505201	1			T1	1		T2	3		T3	187
auto[524288:1048575]	369922	1			T2	752		T3	9		T5	49
auto[1048576:1572863]	283142	1			T13	562		T14	2285		T17	2585
auto[1572864:2097151]	326240	1			T2	1421		T3	27		T11	1008
auto[2097152:2621439]	337541	1			T5	79		T13	3049		T14	8
auto[2621440:3145727]	370972	1			T2	256		T5	70		T11	280
auto[3145728:3670015]	304702	1			T2	3868		T3	6		T5	42
auto[3670016:4194303]	362171	1			T2	258		T3	1		T5	41

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1980570

1

T1

1

T2

6558

T3

70

auto[1]

879321

1

T3

160

T5

299

T11

2529

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2513336

1

T1

1

T2

6036

T3

230

auto[1]

346555

1

T2

522

T5

93

T13

2489

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	146445	1			T1	1		T2	1		T3	187
auto[0]	auto[0]	auto[0:524287]	auto[1]	320237	1			T13	2363		T17	3214		T18	3230
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	148459	1			T2	14		T3	9		T5	49
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	183636	1			T2	730		T13	3927		T14	259
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	54635	1			T13	6		T14	1		T17	1
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	192701	1			T13	518		T14	2284		T17	2584
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	90970	1			T2	2		T3	27		T11	1008
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	187775	1			T2	901		T13	5657		T14	1
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	102807	1			T5	34		T13	7		T14	2
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	191972	1			T13	3040		T14	1		T17	2092
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	113128	1			T5	70		T11	280		T13	7
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	201704	1			T2	256		T13	642		T14	311
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	112627	1			T2	3		T3	6		T11	3
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	136794	1			T2	3862		T13	130		T14	2
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	123790	1			T2	2		T3	1		T5	41
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	190740	1			T2	256		T13	3350		T14	129
auto[0]	auto[1]	auto[0:524287]	auto[0]	1210	1			T2	2		T5	6		T17	5
auto[0]	auto[1]	auto[0:524287]	auto[1]	34194	1			T18	2950		T33	1497		T34	257
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	192	1			T14	2		T17	1		T33	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	35899	1			T14	2015		T17	1		T33	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	279	1			T18	9		T33	1		T35	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	32675	1			T18	388		T19	2701		T73	128
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	383	1			T2	1		T13	1		T34	6
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	44424	1			T2	517		T34	2		T35	525
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	246	1			T5	45		T17	2		T18	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	40280	1			T17	1999		T33	1		T35	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	696	1			T33	3		T43	1		T19	13
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	53568	1			T13	2488		T33	518		T43	256
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	342	1			T2	2		T5	42		T14	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	52596	1			T14	5		T18	869		T43	3287
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	211	1			T34	4		T43	2		T142	2
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	45342	1			T34	1		T43	1		T142	228
auto[1]	auto[0]	auto[0:524287]	auto[0]	292	1			T17	3		T18	2		T33	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	2516	1			T17	54		T18	5		T36	18
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	160	1			T2	6		T17	1		T18	2
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1111	1			T2	2		T17	11		T18	6
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	192	1			T13	2		T36	2		T19	4
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1879	1			T13	36		T36	32		T19	11
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	188	1			T13	1		T14	1		T17	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1995	1			T13	2		T14	9		T17	3
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	173	1			T13	2		T14	1		T17	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1544	1			T14	4		T17	25		T33	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	163	1			T13	2		T17	1		T36	4
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1290	1			T13	5		T36	19		T19	6
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	179	1			T2	1		T13	2		T14	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1540	1			T13	8		T14	9		T33	4
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	166	1			T13	2		T14	1		T33	3
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	1528	1			T13	16		T14	4		T33	4
auto[1]	auto[1]	auto[0:524287]	auto[0]	40	1			T33	1		T34	1		T22	2
auto[1]	auto[1]	auto[0:524287]	auto[1]	267	1			T22	1		T290	14		T32	8
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	43	1			T14	1		T17	1		T33	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	422	1			T14	1		T144	5		T147	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	48	1			T18	4		T147	1		T273	4
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	733	1			T18	20		T147	16		T273	66
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	57	1			T34	2		T35	3		T19	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	448	1			T34	49		T35	13		T19	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	52	1			T33	1		T35	2		T43	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	467	1			T33	19		T35	12		T43	2
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	40	1			T33	1		T19	2		T147	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	383	1			T33	1		T19	11		T147	51
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	49	1			T14	2		T43	4		T142	2
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	575	1			T14	7		T43	7		T142	92
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	48	1			T34	1		T43	1		T142	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	346	1			T34	4		T142	20		T19	9

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1621180	1			T1	1		T2	6027		T3	70
auto[0]	auto[0]	auto[1]	877240	1			T3	160		T5	220		T11	2529
auto[0]	auto[1]	auto[0]	340872	1			T2	522		T5	14		T13	2489
auto[0]	auto[1]	auto[1]	1665	1			T5	79		T34	2		T35	4
auto[1]	auto[0]	auto[0]	14590	1			T2	9		T13	74		T14	31
auto[1]	auto[0]	auto[1]	326	1			T13	4		T33	2		T34	1
auto[1]	auto[1]	auto[0]	3928	1			T14	11		T17	1		T18	24
auto[1]	auto[1]	auto[1]	90	1			T33	1		T34	1		T35	4